JPH05158866A - Still picture processor - Google Patents

Abstract

PURPOSE:To perform an access to a picture memory by continuous address values, and to efficiently operate a high speed data transfer by interposing an address converting part. CONSTITUTION:A DMA transfer controller 22 is activated by receiving the information of a transfer start address and the number of transfer bites from a main controller 21, and mainly operates the data transfer between a picture memory 2 in a picture processor 38 and an input and output interface controller 23. An address conversion ROM 1 in the picture processor 38 converts the address values received through an address bus 45 of a CPU bus 43 from the DMA transfer controller 22 into the actual address values to the picture memory 2. In the case of the memory constitution in which picture data are expanded in one part on the picture memory 2, the address conversion ROM 1 operates an address conversion so that the DMA transfer controller 22 can perform an access to the picture memory by the continuous address values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention records / stores / stores image information, particularly still image information, stored in a recording medium such as an optical disk.
The present invention relates to a technique effectively applied to a still image processing device for display processing.

[0002]

2. Description of the Related Art In recent years, with the advent of recording media having an enormous storage capacity such as optical discs, image data of, for example, ultrasonic diagnostic equipment for medical use has been accumulated as image files.

In this type of still picture information, 66 in the horizontal direction.
One screen is composed of a pixel row of 0 dots (approx. 768 dots when approximated by a squared value) and 490 dots (approx. 512 dots when approximated by a squared value) in the vertical direction. Therefore,
In order to display one still image, the frame memory is
It was necessary to have a structure of 68 × 512 bytes.

However, this type of general-purpose image memory (VRA
Since M) has a structure of 512 × 512 bytes, two sets of 1024 × 512 (=
524288) Byte configuration.

By the way, in this type of image processing apparatus, when the data expanded in the image memory is written in the optical disk, or the data stored in the optical disk is expanded in the image memory, the data transfer processing efficiency is improved. Therefore, it is conceivable to perform the DMA transfer by using a DMA transfer control device different from the main control device.

In the DMA transfer, the main controller only notifies the transfer start address on the image memory and the number of transfer bytes to the DMA transfer controller, and the subsequent data transfer does not go through the main controller and the DMA transfer controller does not. Executed under the control of.

[0007]

However, as shown in FIG. 8, when the image memory configuration and the image data configuration do not match, that is, the horizontal data number is 768 bytes as the image data. Thus, the image memory has a structure of 1024 bytes, and an unnecessary area (remaining area) of 256 × 512 bytes is generated.

When the DMA transfer is performed with the image data of such a format, the start address (100
000h address) and transfer byte number (768 bytes) are DM
Instructed by the A transfer control device, one line of data (10
DMA transfer of addresses 0000h to 1002FFh) is executed. When the data transfer for one line is completed, the DMA transfer control device notifies the transfer completion, and the main control device sends the next start address (100400h).
The address) and the number of transfer bytes (768 bytes) are instructed to the DMA transfer control device.

As described above, since the DMA transfer control device repeats activation every time one line of data is transferred, the overhead for carrying out the transfer becomes large and the processing efficiency becomes poor. For example, in order to transfer data for 512 lines, it is necessary to repeat 512 times the DMA transfer control device activation cycle, and it has been difficult to realize high-speed processing, which is an advantage of DMA transfer.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is, when image data is expanded only in a part of the image memory as described above, or when image data is expanded in a part of the image memory. Efficient DMA when deploying
To make the transfer feasible.

[0011]

According to the present invention, a main control device for outputting a transfer start address and a transfer byte number on the image memory to a bus prior to data transfer together with the image memory for storing image data is provided. A DMA transfer control device activated by a transfer start address and the number of transfer bytes fetched from the bus, sequentially incrementing an address value from the transfer start address, and accessing the image memory until the number of transfer bytes is reached; An address that is interposed between the image memory and that converts the address input value received from the DMA transfer control device into an address output value that skips the remaining area other than the image data storage portion on the image memory and outputs the address. A still image processing device having a conversion unit.

[0012]

According to the above-mentioned means, the main control device can activate the DMA transfer control device by designating the transfer start address and the number of bytes of all data of one image without being aware of the image development state on the image memory. Good.

The continuous address value output from the DMA transfer control device is converted by the address conversion unit to access the image memory. Therefore, the address of the extra area on the image memory is skipped and the transfer is executed. To be done.

Therefore, the main controller can transfer all the data for one image by only starting the DMA transfer controller once, and it is possible to dramatically improve the data transfer efficiency.

The first configuration of the address conversion unit is
Further, it is possible to use an address conversion table in which an address output value paired with each address input value is registered. In this address conversion table, a continuous address from the DMA transfer control device may be registered in the address input value, and an address value that skips the extra area may be registered in the address output value.

In the second configuration, for example, as described above, the address output value is not determined in advance for all the address input values, and the address value received from the DMA transfer control unit is an extra area in one frame. When it corresponds to the start address of, the logic circuit may output the value obtained by adding the number of bytes of the extra area in the same frame to the start address as the address output value.

[0017]

[Embodiment 1] Next, an embodiment of the present invention will be described with reference to the drawings. The image processing apparatus 31 of this embodiment is used as a medical image processing system as shown in FIG. 2, for example, is connected to a medical ultrasonic diagnostic apparatus 32 through a video input and a video output, and is connected to another apparatus. It is connected to an output device 33 such as a video printer through a video output.

The image processing apparatus 31 uses an optical disk 34 as a recording medium, and has an optical disk drive device 35 on which the optical disk 34 can be mounted from the front side of the image processing apparatus 31.

Further, the image processing apparatus 31 may be connected with a wired remote controller 36, a wireless remote controller, a foot switch 37 or the like shown in order to improve operability.

The internal configuration of the image processing device 31 is as shown in FIG. 1, and mainly includes the image processing section 38 and the main control section 4.
0 and the above-mentioned optical disk drive device 35,
A power supply unit 41 and an operation panel 42 are attached to this.

The main controller 40 and the image processor 38 are C
They are connected by a PU bus 43, and the main controller 40 and the optical disk drive device 35 are connected by an input / output interface bus 44.

The internal structure of the main controller 40 is as shown in FIG. 4, and the main controller 21 and the DMA transfer controller 22 are provided.
And an input / output interface control device 23. The CPU bus 43 described above is composed of an address bus 45 and a data bus 46, and can input / output mutually with each unit. A bus use right control line 47 for notifying and declaring the bus use right is set between the main controller 21 and the DMA transfer controller 22.

Further, the input / output interface controller 2
The above-mentioned input / output interface bus 44 is set between the optical disc drive device 3 and the optical disc drive device 35.
The main control unit 40 is a part that controls the entire image processing apparatus 31, and the main control apparatus 21 is configured by a processor element for 16-bit processing or 32-bit processing.

The DMA transfer control device 22 is mainly for performing data transfer between the image memory 2 in the image processing unit 38, which will be described later, and the above-mentioned input / output interface control device 23. It is activated by receiving the information of the transfer start address and the number of transfer bytes from, and notifies the main controller 21 of the transfer completion when the data transfer is completed.

Next, the internal structure of the image processing unit 38 will be described with reference to FIG. In the figure, an address conversion ROM 1 as an address conversion unit converts an address value received from the DMA transfer control device 22 through the address bus 45 of the CPU bus 43 into an actual access address value to the image memory 2. This is to enable access as continuous addresses even in the case of a memory configuration in which image data is expanded in a part of the memory 2. An address conversion table 48 is provided inside this, and details thereof will be described later.

The image memory 2 is used to fetch and display image data and is composed of a dual port RAM. The control register 3 connected to both the address bus 45 and the data bus 46 is a register for changing the control state of the image processing unit 38, and the registered contents of this register are rewritten by the main control unit 21.

A video input from the outside, for example, from the medical ultrasonic diagnostic apparatus 32, passes through the input buffer 4, and then the input low-pass filter 5 → A / D converter 6 → capture /
It is stored in the image memory 2 via the display switch 7.

Here, the synchronizing signal in the video signal from the outside is separated by the synchronizing signal separating circuit 11, and the presence or absence of the synchronizing signal is detected in the synchronizing signal detecting circuit 12. If there is a sync signal (external sync) at this time,
The sync signal selection circuit 13 sends this external sync signal to the image memory control unit 14 and the sync signal delay circuit 16.

On the other hand, when there is no external synchronization, the synchronization signal selection circuit 13 selects and outputs the synchronization signal (internal synchronization) from the synchronization signal generation circuit 15. The synchronizing signal generating circuit 15 is for making it possible to display a still image even when there is no video input signal from the outside.

The input low-pass filter 5 described above has an A / D
A filter that reduces the frequency component of the video signal input to the A / D converter 6 to ½ or less of the sampling frequency in order to prevent aliasing error due to conversion sampling, and the video input signal (analog (Data) is binarized or multivalued in the A / D converter 6 and converted into image data (digital value). The capture / display switching unit 7 switches between the writing and reading modes of the image memory 2, and the switching is controlled by the image memory control unit 14. The operation state of the image memory control unit 14 is determined by the control register 3 described above. Therefore, the instructions for writing and reading in the image memory 2 are
By rewriting the control register 3 by the main control device 21, the image memory control unit 14 → capture / display switching unit 7 is operated and executed.

Data can be read from the image memory 2 by taking in / display switching device 7 D / A converter 8 output low pass filter 9 sync signal adding circuit 10 output buffer 17 (or output buffer 18). Is output through the route.

Here, the image data converted into analog data in the D / A converter 8 is cut by the output low-pass filter 9 to eliminate unnecessary frequency components of 1/2 or more of the sampling frequency contained in the video signal, The sync signal adding circuit 10 combines the sync signal and the sync signal to generate a video output signal. The sync signal delay circuit 16 connected to the preceding stage of the sync signal adder circuit 10 is a circuit for matching the delay of the video signal due to internal processing and the timing of the sync signal.

Next, the contents of the address conversion table 48 provided in the address conversion ROM 1 will be described. In the address conversion table 48, as shown in FIG. 5, an address input value and an address output value are registered as a pair.

Here, the address allocation on the image memory 2 is, as shown in FIG. 8, addresses 100000h to 17FF.
Although the address is FFh, the actual image data is 10,000
The range from 0h to 17FEFFh (a surplus area), and the diagonal range from addresses 100300h to 17FFFFh is a surplus area 50.

Therefore, also in the address conversion table 48, the address value corresponding to the above-mentioned extra area 50 is skipped and the address output value is set. That is, the first address of the first line is 1 as the transfer start address.
When the address 00000h is designated, the transfer address value is sequentially incremented to 100001h, 100002h, .... Then, up to the address 1002FFh, the address input value and the address output value are the same value, but the address input value becomes the spare area 50 100300h.
At the address, the address output value is shifted to the address 100400h, which is the start address of the next line.

Since the address value of the spare area 50 is skipped by setting the address output value of the conversion table in this manner, the address value from the DMA transfer control device 22 can be set to a continuous value. Therefore, one DM
With A transfer, it is possible to transfer all image data for one sheet.

Next, a specific example of the data transfer will be described based on the flow charts of FIGS. 6 and 7. First, the main controller 21 rewrites the contents of the control register 3 of the image processing unit 38 via the CPU bus 43 (step 6).
01). The control register 3 controls the image memory control unit 14 to input the video input image data from the input buffer 4 → the input low-pass filter 5 → the A / D converter 6 → the capture / display switching device 7 into the image data of one frame. It is expanded in the memory 2 (602).

Next, the main control unit 21 instructs the optical disk drive unit 35 through the input / output interface control unit 23 and the input / output interface bus 44 to prepare for writing (603).

Next, the main control unit 21 uses the CPU bus 43.
To the DMA transfer control device 22 through the image memory 2
The start address (address 100000h) and the number of transfer bytes (768 × 512 = 393216 bytes) are notified (604).

Here, the bus use right is transferred between the main controller 21 and the DMA transfer controller 22, and the bus use right is transferred to the DMA transfer controller 22 (605). Next, the DMA transfer control device 22 outputs the head address (N: 100000h address) of the image memory 2 received above to the address bus 45 of the CPU bus 43 (6).
06).

The address conversion ROM 1 which has received the address from the address bus 45 stores the address conversion table 48.
The address value is converted based on the above, and the image memory 2 is accessed by this address output value (607). Here, the start address (address 100000h) is as shown in FIG.
According to the address conversion table 48, the converted address output has the same address value (address 100000h).
This address on the image memory 2 (address 100000h)
Is output to the data bus 46 (608). This data is sent to the input / output interface controller 23 by D
MA transfer (609), transfer to the optical disk drive device 35 through the input / output interface bus 44,
It is written on the optical disk 34 in the optical disk drive device 35 (609, 610).

Next, the DMA transfer control device 22 increments the address value (N) (612), and the next address (address 100001h) is obtained as described above (step 6).
06-610), the data of this address is DMA-transferred.

In this embodiment, in this DMA transfer, as shown in the address conversion table 48 of FIG. 5, even if the address input value is a continuous value, the corresponding address output value is stored in the spare area 50. It is set to skip.

Therefore, in this embodiment, it is not necessary to restart the DMA transfer for the data transfer of the second line (100400h-) after the data transfer of the first line (100000h-1002FFh) is completed.
The data of one image (data in the diagonal range of 100000h to 17FEFFh) is once for the DMA transfer control device 22.
All can be transferred by starting.

When it is detected in step (611) that the data transfer of the final address (15FFFFh by the address of the CPU bus) is completed, the DMA transfer control device 22 returns the bus use right to the main control unit 40 ( 61
3).

Next, the main controller 40 instructs the optical disk drive unit 35 through the input / output interface controller 23 and the input / output interface bus 44 to write the data remaining in the buffer to the optical disk 34 (614). Then, the optical disc drive device 35 is instructed to cancel the write preparation mode (615), and the data transfer for one image is completed.

As described above, in this embodiment, the address conversion table 48 is used to access the continuous addresses received from the DMA transfer control device 22 in conformity with the state of the image data expanded in the image memory 2. Unlike the prior art, it is not necessary to repeat the activation / completion of the DMA transfer every 768 bytes, and extremely high-speed and efficient data transfer can be realized.

Although the address conversion table 48 is set in the address conversion ROM 1 in the image processing unit 38 in this embodiment, the address bus 4 is set in the main control unit 40.
5 may be connected.

[0049]

[Embodiment 2] FIG. 9 shows the configuration of an address conversion unit (a portion corresponding to the address conversion ROM 1 in Embodiment 1) which is another embodiment of the present invention. That is, in this embodiment, the address conversion unit uses the middle 12
It has a conversion circuit 53 for converting only bits. As shown in FIG. 10, the conversion circuit 53 has a function of outputting the upper 4 bits and the lower 8 bits of the input address as the input values as they are, and converting only the middle 12 bits.

As shown in FIG. 11, the conversion circuit 53 has a counter 51 and an addition circuit 52. The counter 51 is a ternary counter that is incremented by the count pulse of the increment detector 54,
It is reset by a clear pulse from the column detector 55. The 0-column detector 55 has a function of outputting a clear pulse when it is detected that the middle 12-bit address is 000h.

The adder circuit 52 has a function of adding the value of the counter 51 and the value of the middle 12 bits of the address and outputting the result. Since the counter 51 is a ternary counter, the input middle address is multiplied by 1/3 here. Then, in the adder circuit 52, it is added with a 3/3 times address, that is, the original address. As a result, the input middle 12-bit address is multiplied by 4/3 and output. At this time, values below the 0th place are truncated and an integer value is output. FIG. 10 shows what kind of output address an input address is converted by using the circuit configuration of this embodiment.

As described above, even if the logic circuit configuration according to the second embodiment is used, the address conversion can be performed so as to skip the spare area 50 as in the first embodiment. According to the present embodiment, since the address conversion is realized by the logic circuit, it is possible to deal with the case where the frame memory has a large scale.

Incidentally, instead of the counter 51, FIG.
As shown in, a comparison circuit 56 for comparing the start address of the extra area to be skipped with the input address is provided, and when an address input (medium 12-bit address value) exceeding these set values is made. , 1h may be added and output.

[0054]

According to the present invention, when the image information is expanded only in a partial area of the image memory, or when the image data is expanded in a part of the image memory, the address is transferred when the image data is transferred. Since it is possible to access the image memory with continuous address values through the interposition of the conversion unit, efficient and high-speed data transfer processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus that is an embodiment of the present invention.

FIG. 2 is a configuration diagram of an image processing system using the image processing apparatus according to the first embodiment.

FIG. 3 is a functional block diagram showing an internal configuration of an image processing unit in the image processing apparatus according to the first embodiment.

FIG. 4 is a functional block diagram showing an internal configuration of a main control unit in the image processing apparatus according to the first embodiment.

FIG. 5 is an explanatory diagram showing an address conversion table in the image processing apparatus according to the first embodiment.

FIG. 6 is a flow diagram (1) showing operation steps when outputting image data.

FIG. 7 is a flowchart (2) showing operation steps in the case of outputting image data.

FIG. 8 is an explanatory diagram showing an address arrangement of image data on an image memory.

FIG. 9 is a block diagram showing the configuration of an address conversion unit according to the second embodiment.

FIG. 10 is an explanatory diagram showing correspondence between input addresses and output addresses in the second embodiment.

FIG. 11 is a block diagram showing an internal configuration of a conversion circuit according to the second embodiment.

FIG. 12 is a block diagram showing a modification of the address conversion unit in the second embodiment.

[Explanation of symbols]

 1 ... Address conversion ROM 2 ... Image memory 3 ... Control register 4 ... Input buffer 5 ... Input low-pass filter 6 ... A / D converter 7 ... Acquisition / display switching device 8 ... D / A Converter 9. Output low-pass filter 10. Synchronous signal adder circuit 11. Synchronous signal separation circuit 12. Synchronous signal detection circuit 13. Synchronous signal selection circuit 14. Image memory control unit 15. Synchronous signal generation circuit 16 ・ ・ Synchronous signal delay circuit 17, 18 ・ ・ Output buffer 21 ・ ・ Main controller 22 ・ ・ DMA transfer controller 23 ・ ・ I / O interface controller 31 ・ ・ Image processing device 32 ・ ・ Medical ultrasonic diagnostic device 33 .. Output device (video printer) 34 .. Optical disc 35 .. Optical disc drive device 36 .. Wired remote controller 37 .. Foot Switch 38. Image processing unit 40. Main control unit 41. Power supply unit 42 .. Operation panel 43 .. CPU bus 44 .. Input / output interface bus 45 .. Address bus 46 .. Data bus 47 .. Bus use Right control line 48 ... Address conversion table 49 ... Image data expansion area 50 ... Extra area 51 ... Counter 52 ... Addition circuit 53 ... Conversion circuit 54 ... Increment detection section 55 ... 0 column detection section 56 ...・ Comparison circuit

Claims (4)

[Claims] 1. A still image processing apparatus for transferring image data expanded in a part of an image memory to a recording medium through a bus or expanding image data stored in the recording medium in a part of an image memory through a bus. A main controller that outputs the transfer start address and the number of transfer bytes on the image memory to the bus before the data transfer together with the image memory that stores the image data, and the transfer start address and the transfer byte fetched from the bus. A DMA transfer control device that is activated by a number, sequentially increments an address value from a transfer start address and accesses the image memory until the number of transfer bytes is reached, and is interposed between the DMA transfer device and the image memory, The address input value received from the DMA transfer control device is used as an image data storage portion on the image memory. Still image processing apparatus characterized by comprising an address conversion unit for converting the address output value to skip over areas of the home. 2. The still image processing according to claim 1, wherein the address conversion unit has an address conversion table in which a pair of address output values is registered for each address input value. apparatus. 3. The address conversion unit includes an address counter that counts each time an address is received from the DMA transfer control unit, and an adder circuit that adds byte values corresponding to an extra area. The still image processing apparatus according to claim 1. 4. The address counter extracts middle bits of an input address and repeats counting at a constant cycle,
The still image processing apparatus according to claim 3, wherein the address counter and the input address are added by the adder circuit and output.