JPS62243075A - Image data transfer device - Google Patents

Abstract

PURPOSE:To transfer an image data in a short time by bringing it to a compression processing or an expansion processing, by providing an image data compressing/expanding means between the first and the second image storage means, and executing the processing. CONSTITUTION:An image memory 11 is connected to a frame memory 16 of a display 15 through interfaces 12, 13 and a data compressing/expanding circuit 14. A direct memory access controller DMAC 17 generates a continuous address, and controls the circuit 14 and the memory 16. In this way, an image data from the memory 11 is compressed in the course of its transfer and transferred to the memory 16, and also, the compressed image data from the memory 16 can be transferred to the memory 11 by expanding it in the course of its transfer. Accordingly, the circuit constitution can be simplified, and also, the image data can be transferred in a short time.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an image data transfer device.

[Conventional technology]

For example, when compressing an image stored in the image memory, decompressing it, and displaying it on a display, it is necessary to transfer the image data between the frame memory for display and the image memory. As such an image data transfer apparatus, there is a conventional one having the configuration shown in FIG. This image data transfer device includes an image memory 1 and a memory 4 located at a different address from the frame memory 3 of the display 2, reads an image compressed and stored in the image memory 1, and decompresses the image. When writing to the frame memory 3, first, the direct memory access controller (to DM8) 5 continuously generates addresses for the image memory l and the memory 4, and
Read the compressed image data 6 stored in the memory 4, transfer it to the memory 4, and write it.Next, the compressed image data 6 is read from the memory 4, and the processor 7 decompresses it and stores it in the frame memory. 3, the image is expanded. Further, when reading an image stored in the frame memory 3, compressing it, and writing it to the image memory 1, the image data is similarly read from the frame memory 3, and the processor 7 performs compression processing on the image data. Write to memory 4, then DMAC
5, the compressed image data 6 written in the memory 4 is read out and transferred to the image memory l.

[Problem that the invention seeks to solve]

However, in such a conventional image data transfer device, since the memo I74 is required in addition to the frame memory 3, the configuration is complicated, and the transfer of image data between the image memory 1 and the frame memory 3 is complicated. There is a problem in that it takes a long time to transfer data because it is performed via this memory 4.

The present invention has been made in view of these conventional problems, and is an image data transfer system that has a simple configuration and is appropriately configured to compress or expand image data and transfer it in a short time. The purpose is to provide equipment.

[Means for solving problems]

In order to achieve the above object, the present invention provides an image data compression/expansion means between the first image storage means and the second image storage means, and uses the image data compression/expansion means to store another image storage means. The image data from the first image storage means is compressed during the transfer and transferred directly to the second image storage means, and the compressed image data from the second image storage means is , and is expanded during the transfer and directly transferred to the first image storage means.

〔Example〕

FIG. 1 shows a first embodiment of the invention. In this embodiment, an image memory 11 of an image data recording device for recording and reproducing image data is connected to a disk recorder 1 via an interface 12, 13 and a data compression/expansion circuit 14.
The data compression/expansion circuit 14 and frame memory 16 are controlled by a DMAC 17 that generates continuous addresses, and the image memory 11 is connected to the frame memory 16 of the image memory 11.
The image data is transferred between the frame memory 16 and the frame memory 16.
This is done directly via the data compression/expansion circuit 14.

Whether or not to perform compression processing or expansion processing on image data is set via a CPII (Central Processing Unit) from a keyboard (not shown) or the like. Further, whether compression processing or expansion processing is to be performed is set depending on the transfer direction of the image data.

FIG. 2 shows an example of the circuit configuration of the data compression/expansion circuit 14 shown in FIG. This data compression/expansion circuit 14 is
From the data bus 31 on the frame memory 16 side to the buffer 3
8-bit actual image data input via 2 and
A subtracter 35 obtains difference data between the predicted value inputted via the buffer 34 from the predictor 33 that predicts according to a predetermined prediction function, and performs compression processing on this difference data to convert it into a 4-bit converted value. 4-bit output data latches 3B and 39 that latch this 4-bit converted value via a buffer 37.
, the converted values output from these output data latches 38 and 39 are stored in the image memory 11 as 8-bit data in correspondence with the upper 4 bits and lower 4 bits, respectively.
A buffer 40 for outputting to the image memo side, an 8-bit input data latch 42 that launches 8-bit data input from the image memo side via the buffer 41, and 8-bit data from this input data latch 42. Decompression processing is performed on the converted value inputted via the buffer 44 from the selector 43 that divides the converted value into the upper 4 bits and the lower 4 bits, or on the converted value input manually from the nonlinear quantizer 36 via the buffer 37. A representative value setter 45 converts the representative value into an 8-bit representative value, an adder 46 that calculates added data of the representative value and the predicted value inputted from the pre-S unit 33 via the buffer 34, and frames the added data. Memo In
a buffer 47 for outputting to the data bus 31 on the 6 side;
Column number latch 48 and data bus 3 for launching the horizontal image data number (hereinafter referred to as column number) of an image input from a keyboard (not shown) or the like via the CPU
A counter 49 counts up each time one image data is input from 1 to the data bus 31, or each time one image data is output to the data bus 31.The values of both the column number latch 48 and the counter 49 are compared. , a comparator 50 that controls the buffer 34, the nonlinear quantum unit 36, and the representative value setter 45, a basic clock generation circuit 51 for a data compression/expansion circuit that outputs control signals to each element according to the operation timing, and a DMAC 17. A control signal is output to the basic clock generation circuit 51 for the data compression/expansion circuit in response to the activation signal 19 of the AC.
Data compression/data compression that outputs a processing end signal 21 to 17.
A 1/P circuit 52 for expansion circuit is provided.

Here, each buffer 32, 37, 40, 41, 44.4
7 is controlled according to each process when compression processing or expansion processing is selected depending on the transfer direction of image data. Also,
Initialization of the data compression/expansion circuit 14 is performed by inputting an initialization signal via the CPU from a keyboard (not shown) or the like.

The operation of this embodiment will be explained below.

The data compression/decompression circuit 14 performs compression processing on two pieces of 8-bit input image data, outputs one piece of compressed 8-bit image data, and outputs one piece of compressed 8-bit image data. By executing decompression processing on 8-bit input image data, two pieces of 8-bit image data are output.

First, a method of calculating predicted values in the data compression/expansion circuit 14 will be explained.

FIG. 3 shows an image 53 stored in the frame memory 16.
, the position of data (hereinafter referred to as initial image data) serving as an initial value for prediction is shown. The initial image data 54 is the image data in the shaded area of the image 53, that is, the image data at the top of the image 53 (first line) and the image data at the beginning of each line (first kamura). Image data 54 is transferred to buffer 34 and nonlinear quantizer 36 based on the output of comparator 50 that compares data from column latch 48 and counter 49.
and by controlling the representative value setter 45,
Even during execution of compression processing or expansion processing, the data is transferred as is without any processing being performed.

The predicted value is calculated by taking into account not only the immediately previous image data but also the change in the image data immediately above the ■ line. That is, it is determined by the following equation.

x=c+ (B-A) In the above equation, X represents a predicted value, and A, B, and C represent each image data having the positional relationship shown in FIG.

FIG. 4 shows the operation when image data from the frame memory 16 is compressed and transferred directly to the image memory 11.

In the compression process, the DMAC 17 uses the frame memory 1
6 to read out one piece of image data stored in the frame memory 16, and read out one piece of image data stored in the frame memory 16.
A start signal 19 is output to the /F circuit 52. In response to this activation signal 19, a control signal is sent from the data compression/expansion circuit I/F circuit 52 to the data compression/expansion circuit basic clock generation circuit 51, thereby controlling the operations of each section. That is, the read 8-bit image data is input from the data bus 31 on the frame memory 16 side to the subtracter 35 via the buffer 32.
5, difference data between the predicted value calculated by the predictor 33 and input via the buffer 34 is obtained. This difference data is input to the non-linear quantizer 36, subjected to compression processing, non-linearly converted to a 4-bit converted value, and latched into the output data latch 38 via the buffer 37, as well as representative value setting. The data is inputted to a device 45, subjected to decompression processing, and converted into a representative value. FIG. 5 shows the correspondence among these difference data, converted values, and representative values. The representative value is added to the predicted value of the next image data input from the data bus 31 in the adder 46, and the result is adopted as a new predicted value and set in the predictor 33. In this way, by partially performing decompression processing during the compression process, it is possible to prevent errors from accumulating during the decompression process.

After performing the above processing, the basic clock generation circuit 51 for the data compression/expansion circuit
A control signal is output to the circuit 52, thereby causing the data compression/expansion circuit 1/F circuit 52 to output a processing end signal 21 to the DMAC 17. Upon receiving this processing end signal 21, the DMAC 17 continues to control the frame memo 6 to read the next image data, and sends an activation signal 1 to the data compression/expansion circuit 1/F circuit 52.
Outputs 9. As a result, the data compression/expansion circuit 14
In the same operation as described above, the input image data is compressed and converted into a 4-bit converted value, and this time, after launching this 4-bit converted value into the output data latch 39, Continuing to perform the same operation, DMAC17
At the same time, the 4-bit converted values latched in the output data latches 38 and 39 are compressed into 8 bits and 7 bits corresponding to the upper 4 bits and lower 4 bits, respectively. The resulting image data is output to the image memo January 1 side via the buffer 40. Thereafter, in the same manner, the two 8-bit input image data from the frame memo January 6 are sequentially processed into one compressed 8-bit image data and transferred to the image memo January 1.

FIG. 6 shows the operation when compressed image data from the image memory 11 is expanded and transferred directly to the frame memory 16.

In decompression processing, DMAC17 is for data compression/decompression circuit! A start signal 19 is output to the /F circuit 52. As a result, the data compression/expansion circuit I/F circuit 52
reads out one piece of compressed image data stored in the image memory 11, and outputs a control signal to the basic clock generation circuit 51 for the data compression/expansion circuit. The 8-bit compressed image data input from the image memo January 1 side via the buffer 41 is input to the input data latch 4.
The selector 43 selects one of the 4-bit converted values corresponding to the upper 4 bits and the lower 4 bits.

The selected 4-bit converted value is input to a representative value setter 45 via a buffer 44, where it is expanded and converted into a representative value. This representative value is added to the predicted value output from the predictor 33 via the buffer 34 in the adder 46, and is output as 8-bit image data via the buffer 47 to the data bus 31 of the 16 frame memories. .

The basic clock generation circuit 51 for the data compression/expansion circuit is
After outputting the image data to the data bus 31, a control signal is output to the 1/F circuit 52 for data compression/expansion circuit. The INF circuit 52 for the data compression/expansion circuit receives the control signal from Miko and sends a processing end signal 21 to the DMAC 17.
This causes DMAC17 to output frame memory 1.
6 to transfer the image data to the frame memory 16, and output a start signal 19 to the 1/F circuit 52 for the data compression/expansion circuit. As a result, the data compression/expansion circuit 14 switches the selector 43 and performs the same operation on the other remaining 4-bit converted value,
Image data is output to the data bus 31, and then the DMAC
A processing end signal 21 is output to the terminal 17. Thereafter, in a similar operation, one compressed 8-bit input image data from the image memory 11 is sequentially expanded into two 8-bit image data and transferred to the frame memory.

According to this embodiment, the compression process of image data or the expansion process of compressed image data is performed during the DMA transfer period between the image memory 11 and the frame memory 16 without using a separate memory. Therefore, the circuit configuration can be simplified and image data can be transferred in a short time. Furthermore, since the decompression process is performed as part of the compression process, it is possible to prevent errors from accumulating during the decompression process. Furthermore, the compression circuit and the decompression circuit are integrated, and it is possible to select whether to perform compression processing or decompression processing depending on the transfer direction of the image data, so that the data compression/decompression circuit 14
It is also easy to configure itself.

FIG. 7 shows a second embodiment of the invention. In this embodiment, a transfer control means having an image enlargement/reduction function is added to the circuit configuration of the first embodiment. That is, the data compression/expansion circuit 14 and the frame memory 16
A thinning circuit 22 as described in Japanese Patent Application No. 59-206978 is provided between the data compression/expansion circuit 14 and the frame memory 16 by the DMAC 23 which generates continuous or discontinuous addresses. When transferring image data from the memo 16 to the image memory 11, not only is the image data stored in the frame memory 16 compressed and transferred directly to the image memo 1, but also the image data stored in the frame memory 16 is The DMAC 23 accesses and compresses the image data discontinuously so that it becomes an enlarged or reduced image, and directly transfers it to the image memo January 1. Also, from the image memory 11 to the frame memory 16
In transferring the image data to the frame memory 11, the compressed image data sequentially output from the image memory 11 is not only decompressed and transferred directly to the frame memory 11, but also the compressed image data sequentially output from the image memo January 1 Decompress the image data,
To create an enlarged or reduced image, the I4C 23 generates discontinuous addresses for the frame memory 16, and to create a reduced image, the thinning circuit 22 thins out the image data and transfers it directly to the frame memory 16. It is something.

The operation of this embodiment will be explained below.

When enlarging or reducing the image stored in the frame memory 16 and compressing the image data and transferring it directly to the image memo January 1, the DMAC 23 enlarges or reduces the image data stored in the frame memory 16. Access is made discontinuously to obtain a reduced image, and the image data selected thereby is input to the data compression/expansion circuit 14. The selected image data is compressed and compressed by sending the number of columns corresponding to each image to the column number latch 48 (see FIG. 2) in advance via the CPU from a keyboard (not shown) or the like. By executing the compression operation described in the first embodiment in accordance with each image in the decompression circuit 14, the enlarged or reduced image of the image stored in the frame memo January 6 is directly converted into an image as compressed image data. Forward the memo on January 1st.

In addition, when decompressing the image stored as compressed image data in the image memo January 1, enlarging or reducing it, and transferring it directly to the frame memo January 6, the decompression method described in the first embodiment can be used. According to the operation, the image data is expanded in the data compression/expansion circuit 14, and this data compression/expansion circuit 14 expands the image data.
In order to make the image data expanded and sequentially output from the expansion circuit 14 into an enlarged or reduced image, the DMAC 23 generates discontinuous addresses for the frame memory board, and when the image data is to be made into a reduced image, the thinning circuit 22 By thinning out the image data, the image data of the enlarged or reduced image stored in the image memory 11 as compressed image data is directly transferred to the frame memory 16.

Furthermore, when an enlarged or reduced image stored as compressed image data in the image memory 11 is transferred directly to the frame memory, the number of columns corresponding to each image is first input via the CPU from a keyboard (not shown) or the like. It is set in the latch 48 for the number of columns in advance, and data compression/
The decompression circuit 14 executes the decompression operation described in the first embodiment according to each image, and sequentially outputs the image data. The image data sequentially output from the data compression/expansion circuit 14 is enlarged or The image data of the reduced image is directly transferred to the frame memory 16.

Note that the image data of the original image is compressed or expanded and transferred directly to the image memory 11 or frame memory 16 in the same manner as in the first embodiment.

According to this embodiment, image data compression processing, compressed image expansion processing, and image enlargement or reduction processing can be performed between the image memo 1 and the frame memory 16 without using a separate memory. Since this can be done during the transfer period, the circuit configuration can be simplified and image data can be transferred in a short time not only for the original image but also for enlarged or reduced images.

In the third embodiment of the present invention, the thinning circuit 22 and the DHAC 23 in the circuit configuration of the second embodiment are used for processing images of various sizes and enlarged or reduced images, as described in Japanese Patent Application No. 59-206978. At the same time, the same microprogram controls the setting of the number of columns according to each image in the data compression/expansion circuit 14 and the initialization of the data compression/expansion circuit 14.

That is, a microprogram corresponding to the transfer of each image is selected from the keyboard or the like via the CPU, and it is also selected whether to perform compression processing or expansion processing. At the beginning of this selected microprogram, an initialization signal for the data compression/expansion circuit 14 is output, and then the number of lines and columns of each image is set, and the data compression/expansion circuit 14 is output.
The decompression circuit 14 is set to an initial state corresponding to each image.

Thereafter, according to the selected microprogram, each operation described in the first and second embodiments is executed to directly transfer image data.

According to this embodiment, data thinning, address generation, and initial settings of the data compression/expansion circuit 14 are performed by a microprogram, so in addition to the effects of the second embodiment, images of various sizes and Transfer of the image data of the enlarged or reduced image can be realized with the same circuit configuration by preparing a plurality of microprograms corresponding to each one.

〔Effect of the invention〕

As described above, according to the present invention, during the DMA transfer period performed between the first image storage means and the second image storage means, the image data being transferred is compressed or decompressed. Since the processing is performed, images can be transferred directly without using a separate memory. Therefore, the circuit configuration can be simplified and image data can be transferred in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing an example of the configuration of the data compression/expansion circuit shown in FIG. 1. FIGS. 3, 4, and 5 6 is a diagram for explaining the operation of compressing image data from the frame memory and directly transferring it to the image memory in the first embodiment. FIG. FIG. 7 is a block diagram showing a second embodiment of the present invention. FIG. 8 is a block diagram showing a conventional technique. 11... Image memory 12.13 Interface 14... Data compression/expansion circuit 15... Disable 16... Frame memory 17... DHAC 22... Thinning circuit 23...
mouth? IAC31...Data bus 32.34.37.4
0.41.44.47... Buffer 33... Predictor 35... Subtractor 36... Nonlinear quantizer 38, 39... Latch 42 for output data... Lunch 43 for input data ... Selector 45 ... Representative value setter 46 ... Adder 48 ... Column number latch 49 ... Counter 50 ... Comparator 5
1... Basic clock generation circuit for data compression/expansion circuit 52... 17F circuit for data compression/expansion circuit Fig. 3 5L Fig. 4 Fig. 5 Fig. 6 Fig. 7

Claims (1)

[Scope of Claims] 1. Provided between a first image storage means and a second image storage means, the image data from the first image storage means is compressed during transfer, and the image data is directly compressed and At the same time, the compressed image data from the second image storage means is decompressed and directly transmitted to the first image storage means.
1. An image data transfer device comprising image data compression/expansion means for transferring image data to an image storage means. 2. The image data compression/decompression means has integrally configured compression means for performing compression processing and decompression means for performing decompression processing, and selects which processing to perform depending on the transfer direction of the image data. An image data transfer device according to claim 1, characterized in that it is configured as follows. 3. The image data transfer apparatus according to claim 2, wherein the compression means is configured such that the decompression means partially performs decompression processing while the compression processing is being executed. 4. The image data compression/expansion means has a transfer control means for controlling and transmitting the image data as it is or as an enlarged or reduced image, and the image data from the first image storage means is transferred as it is. , or control the image to be an enlarged or reduced image, compress it and directly transfer it to the second image storage means, and expand the compressed image data from the second image storage means and leave it as it is. 4. The image data transfer apparatus according to claim 1, wherein the image data transfer apparatus is configured to control the image so that the image becomes a , enlarged or reduced image and directly transfers the image to the first image storage means. 5. The image data transfer device according to claim 4, wherein the image data compression/expansion means is configured to be controlled by a microprogram.