JPH05108810A - Image processor - Google Patents

Abstract

PURPOSE:To attain a high speed processing by a DMA transfer by providing a binary compressing and expanding means, a color pallet means which converts binary image data into color image data, and a color compressing and expanding means. CONSTITUTION:At the time of the compressing processing of the binary image data, the image data stored in an image memory 5 as two-dimensional data are read through a gate 15, image bus 3, and gate 19 by a word access, and compressed and encoded into code data by a binary compressing and expanding circuit 11. Then, the code data are written through a gate 20, image bus 3, and gate 16 in an image memory 6 by a word. At that time, the by-pass of a color pallet circuit 12 is operated. And also, at the time of expanding the binary image data, the code data in the image memory 5 are read by the word access, and expanded and decoded into the two-dimensional data by the binary compressing and expanding circuit 11, and written in the image memory 6 as the word.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for image processing of image data, and more particularly to compression / expansion, expansion / reduction / rotation of binary image data and color image data, and binary image data. The present invention relates to an image processing device capable of performing image processing of combination with color image data at an extremely high speed.

[0002]

2. Description of the Related Art Conventionally, image processing of binary image data and color image data, that is, data compression / expansion, enlargement / reduction / rotation, and composition are performed separately. When performing the synthesizing process of, it was necessary to perform by software. However, since the synthesis processing of the binary image data and the color image data is performed by software, the processing takes a long time.

[0003]

As described above, the conventional image processing method has a problem that the processing takes a long time.

An object of the present invention is to perform image processing such as compression / expansion, enlargement / reduction / rotation of binary image data and color image data, and image processing of combining binary image data and color image data at an extremely high speed. Another object is to provide an extremely reliable image processing device.

[0005]

In order to achieve the above object, according to the present invention, an image memory for storing binary image data and color image data, and an address calculating means for calculating and giving an address of the image memory, Memory control means for controlling the access mode and access size of the image memory, an image bus for DMA transfer of image data in the image memory, and a gate for inputting / outputting image data to / from the image bus, respectively. Binary compression / expansion means having a plurality of systems and further for compressing / expanding binary image data;
A color palette means for converting the value image data into color image data and a color compression / expansion means for compressing / expanding the color image data are provided.

[0006]

Therefore, in the image processing apparatus of the present invention, by adopting the above means, the compression / expansion and the expansion / reduction / rotation of the binary image data and the color image data can be performed at an extremely high speed by the DMA transfer. Can be processed. Further, since the binary image data can be color-converted by the color palette, the combining process with the color image data can be processed at extremely high speed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the overall configuration of an image processing apparatus according to the present invention. The image processing apparatus of this embodiment is a central processing unit (hereinafter referred to as CPU).
1, system bus 2, two image buses 3, 4
, Two image memories 5 and 6, two address calculation circuits 7 and 8, two memory control circuits 9 and 10, and
A value compression / expansion circuit 11, a color palette circuit 12,
Color compression / expansion circuit 13 and 12 gates 14-2
It is composed of 5 and.

Here, the CPU 1 controls the entire apparatus such as a mode for image processing and setting of parameters. The system bus 2 connects the CPU 1 to each circuit in the device and enables the control by the CPU 1. In addition, image buses 3 and 4
Is for performing the DMA transfer of the image data in the image memories 5 and 6.

On the other hand, the image memories 5 and 6 are for storing binary image data and color image data, respectively. Also, the address calculation circuits 7 and 8
Is for calculating and supplying the addresses of the image memories 5 and 6. Further, the memory control circuits 9 and 10 control the access modes and access cycles of the image memories 5 and 6.

On the other hand, the binary compression / expansion circuit 11 compresses / expands binary image data. Also,
The color palette circuit 12 converts binary image data into color image data using a color palette. Further, the color compression / expansion circuit 13 performs compression / expansion of color image data.

On the other hand, the gates 14 to 25 are for inputting / outputting image data to / from the image buses 3 and 4. That is, the gate 14 inputs / outputs image data between the image memory 5 and the image bus 4. Further, the gate 15 inputs and outputs image data between the image memory 5 and the image bus 3. Further, the gate 16 inputs / outputs image data between the image memory 6 and the image bus 4. The gate 17 inputs / outputs image data between the image memory 6 and the image bus 3. On the other hand, the gate 18 inputs the image data of the image bus 4 to the binary compression / expansion circuit 11. Further, the gate 19 inputs the image data of the image bus 3 to the binary compression / expansion circuit 11. Further, the gate 20 outputs the image data from the binary compression / expansion circuit 11, the image data from the color palette circuit 12, or the bypassed image data to the image bus 4. Furthermore, the gate 21 is provided with image data from the binary compression / expansion circuit 11, image data from the color palette circuit 12,
Alternatively, bypass the bypassed image data to the image bus 3
Is output to. On the other hand, the gate 22 outputs the image data of the image bus 4 to the color compression / expansion circuit 13
Is what you enter. Further, the gate 23 applies the image data of the image bus 3 to the color compression / expansion circuit 13
Is what you enter. Further, the gate 24 outputs the image data from the color compression / expansion circuit 13 or the bypassed image data to the image bus 4. Furthermore, the gate 25 is for color compression /
The image data from the expansion circuit 13 or the bypassed image data is output to the image bus 3. Next, the operation of the image processing apparatus of this embodiment configured as described above will be described with reference to FIG. First, referring to FIG. 2, the types of image data that can be processed,
The structures and access modes of the image memories 5 and 6 will be described.

The image data includes binary image data and color image data, each of which has a data structure of two-dimensional data and code data. The two-dimensional data is, for example, raw data of an image input by raster scanning from an image scanner or the like, and is stored in an image memory set in a two-dimensional address space. The code data is coded data that is coded by the compression process and is stored in the image memory set in the linear address space.

On the other hand, the two-dimensional data access in the binary image data includes a word access for accessing in units of 16 dots and a dot access for accessing in units of 1 dot (data length 1 bit). Further, in the case of accessing the two-dimensional data in the color image data, only dot access is performed in units of 1 dot (data length 24 bits). Further, in the case of code data, both binary image data and color image data are accessed by word access of 1 word / 16 bit length.

The structure and access mode of the image data are the same as those of the address calculation circuits 7 and 8 in FIG.
It is determined by the memory control circuits 9 and 10. That is, the address calculation circuits 7 and 8 can perform address calculation of the linear address space and the two-dimensional address space. In the case of a two-dimensional address space, address calculation corresponding to enlargement / reduction / rotation can be performed in an arbitrary rectangular area by setting parameters. In addition, the memory control circuits 9 and 10
Accesses the image memories 5 and 6 according to the set access mode. Next, the specific operation will be described.

In FIG. 1, in the CPU 1, the mode of each circuit for image processing is passed through the system bus 2.
The entire apparatus is controlled, such as setting parameters. The image processing is basically performed simultaneously with the DMA transfer between the image memory 5 and the image memory 6.

Image processing in the DMA transfer from the image memory 5 to the image memory 6 will be described below. It goes without saying that DMA transfer (image processing) from the image memory 6 to the image memory 5 is also possible. First, image processing of binary image data will be described.

First, in the case of compression of binary image data, the image data stored in the image memory 5 as two-dimensional data is read out by word access through the gate 15, the image bus 3 and the gate 19. Then, the binary compression / expansion circuit 11 compresses and encodes the code data. Then, the encoded code data is written in words to the image memory 6 through the gate 20, the image bus 3, and the gate 16. At this time, the color palette circuit 12 is bypassed. This operation is performed in the area set by CPU 1.

In the case of the binary image data decompression process, the flow of the image data is performed in the same manner as in the compression process, the code data of the image memory 5 is read by word access, and the binary compression is performed.・ Expansion circuit 11
Is expanded and decoded into two-dimensional data, and the decoded two-dimensional data is written in the image memory 6 in words.

Further, in the case of enlarging / reducing / rotating binary image data, the flow of image data is compressed / reduced.
The expansion processing is performed in the same manner as in the case of the expansion processing, but the binary compression / expansion circuit 11 and the color palette circuit 12 are bypassed, and the image memories 5 and 6 are dot-accessed. At this time, the size of the enlargement / reduction / rotation and the rotation angle are determined by the CPU 1
Is determined by the address calculation circuits 7 and 8.

On the other hand, the two-dimensional image data is converted into color data of 1 dot / 24 bits by the color palette circuit 12. In the color palette circuit 12, 2
The value image data is converted into color data of 1 dot / 24 bit by the palette set by the CPU 1. This converted color data is 1 dot / 24 bi
It is written in the image memory in the dot access mode of t. Next, image processing of color image data will be described.

First, in the case of compression processing of color image data, the image data stored in the image memory 5 as two-dimensional data is read out by word access through the gate 15, the image bus 3 and the gate 23. The color compression / expansion circuit 13 compresses and encodes the code data. Then, the encoded code data is written in words to the image memory 6 through the gate 24, the image bus 4 and the gate 16.

Further, in the case of the expansion processing of the color image data, the flow of the image data is performed in the same manner as in the compression processing, the code data of the image memory 5 is read out by word access, and the color compression / expansion is performed. The circuit 13 decompresses and decodes the two-dimensional data, and the decoded two-dimensional data is stored in the image memory 6 as 1 dot / 24b.
Written by it.

Further, in the case of enlarging / reducing / rotating color image data, the flow of the image data is performed in the same manner as in the case of compressing / expanding, but at this time, the image memories 5 and 6 are accessed by dot access. The color compression / expansion circuit 13 is bypassed.

Furthermore, in this embodiment, since the binary image data is converted into the color data by the color palette circuit 12, the binary image data and the color image data can be combined. At this time,
The synthesis area is arbitrarily designated by the address calculation circuits 7 and 8.

As described above, the image processing apparatus of this embodiment has a CPU1 for controlling the entire apparatus such as a mode for image processing and setting of parameters, and a CPU1.
And a circuit in the device, and a system bus 2 for enabling control by the CPU 1, an image memory 5,
Image buses 3 and 4 for performing DMA transfer of 6 image data, image memories 5 and 6 for storing binary image data and color image data, and addresses of image memories 5 and 6 are calculated and supplied. Address calculation circuits 7 and 8 and image memory 5
6, memory control circuits 9 and 10 for controlling access modes and access cycles, a binary compression / expansion circuit 11 for compression / expansion of binary image data, and binary image data into color image data by a color palette. A color palette circuit 12 for conversion and a color compression / expansion circuit 13 for compression / expansion of color image data.
And gates 14 to 25 for inputting and outputting image data to and from the image buses 3 and 4.

Therefore, compression / expansion, enlargement / reduction / rotation of binary image data and color image data are performed.
It is possible to process at extremely high speed by the DMA transfer. Also, the binary image data is color palette circuit 1
Since it is possible to perform color conversion by 2, there is no need to perform a combining process of the binary image data and the color image data by software as in the conventional case, and the combining process with the color image data can be processed at an extremely high speed. The present invention is not limited to the above embodiment, but can be implemented in the same manner as described below.

(A) In the above embodiment, by adding an interface circuit, it becomes possible to communicate with other devices. In this case, the image memory is
It can be used as a second high-speed accessible memory other than the main memory. (B) In the above embodiment, an image can be input / output by adding the interface circuit of the input / output device.

[0029]

As described above, according to the present invention, 2
Value image data and color image data compression
An extremely reliable image processing apparatus capable of performing image processing such as expansion, enlargement / reduction / rotation, and synthesis of binary image data and color image data at an extremely high speed can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a view for explaining the operation of the same embodiment.

[Explanation of symbols]

1 ... CPU, 2 ... System bus, 3, 4 ... Image bus, 5, 6 ... Image memory, 7, 8 ... Address calculation circuit, 9, 10 ... Memory control circuit, 11 ... Binary compression / expansion circuit, 12 ... Color palette circuit, 13 ... Color compression
Expansion circuit, 14-25 ... Gate.

Claims (1)

[Claims] 1. An image memory for storing binary image data and color image data, address calculation means for calculating and giving an address of the image memory, and memory control for controlling an access mode and an access size of the image memory. Means, an image bus for performing a DMA transfer of the image data in the image memory, and a plurality of gates for inputting / outputting the image data to / from the image bus.
Binary compression / expansion means for compressing / expanding value image data, color palette means for converting the binary image data into color image data, and color compression / expansion means for compressing / expanding the color image data. An image processing apparatus comprising: