JPS63300363A - Image processing system - Google Patents

Abstract

PURPOSE:To speed up display processing by performing writing in an image memory and enlarging/reducing operation in parallel. CONSTITUTION:When a host CPU outputs a certain command, a microprocessor 11 sets parameters in respective circuits. When image data is sent from a peripheral device through a system bus, the data is supplied to an expanding circuit 14 through a FIFO memory 12. Here, the expanded data becomes write data in the image memory, and is enlarged or reduced by an enlarging/reducing circuit 15 through a selector 18 and supplied as display data to a monitor through the FIFO memory 13. Consequently, the processing speed for display is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing method suitable for use in a system using a large-capacity optical disk memory for external storage.

(Prior Art) Conventionally, for example, when an image in an optical disk device is displayed on a monitor, this is done through hardware called an image processor. The function of this image processor is to decompress compressed data recorded on the optical disk device, enlarge or reduce the data, and send it to a monitor for display. Third
An example of the configuration of this type of system is shown in the figure.

In the figure, shi is the above-mentioned image processor, 32 is a host CPU, j j is an OCR device, 34 is an image scanner device, 35 is a former disk device, and 36 is a magnetic disk device, which are commonly connected to the system path. There is.

There were two methods for realizing the above as shown below. One is to expand or reduce the data after it is expanded or compressed into an image memory, and then send it to the monitor.The other is to directly send the expanded data to the expansion or reduction circuit without having an image memory. This method is to input the information and send it to the monitor. The former is shown in FIG. 4, and the latter is shown in FIG. 4 and 5 both show the internal configuration of the image processor 31 shown in FIG. 3. In the diagram, 31 is the microprocessor, 312
．． 313 is a FIFO memory, 314 is an expansion circuit, 315
316 is a compression circuit, and 317 is an image memory.

(Problems to be solved by the invention) However, in the former case, it takes time to display the image on the monitor, and in the latter case, when the same image is enlarged and displayed, the data must be retrieved from the optical disk again. Therefore, there was a drawback that it took more time than necessary to display the image.

The present invention has been made in view of the above-mentioned circumstances, and provides a method for writing to an image memory in an image processor.
An object of the present invention is to provide an image processing method that improves display processing speed by performing enlargement and reduction operations in parallel.

[Structure of the Invention] (Means for Solving the Problems) The image data realized by the present invention consists of an expansion circuit that obtains compressed data as input and converts it into a raw image, and an output of this expansion circuit. An image memory that stores image data, a selector that receives the decompression circuit output and image memory output as input, selects and outputs one of them to the enlarging/reducing circuit according to a host command, and obtains the selector output and performs enlarging/reducing processing. It is composed of an enlargement/reduction circuit for outputting image data, and is configured to perform data writing to the image memory and enlargement/reduction processing of the image by the enlargement/reduction circuit in parallel.

(Function) In the above configuration, when a certain command is issued from the CPU, the microprocessor sets parameters for each circuit. When image data is sent from the peripheral device via the system path, the data is supplied to the decompression circuit via the FIFO memory. The expanded data here becomes write data to the image memory, and is also subjected to scaling processing in the scaling circuit via the selector, and is then sent to the FIF
o The data is supplied as display data to the monitor via the memory.

This improves the processing speed for display.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, numeral 1 is a microprocessor that serves as the control center of the system and mediates host commands. 1
2 and 13 are FIFO memories, which absorb the difference between the processing speed of the image processor and the transfer speed of the system path. Reference numeral 14 denotes an expansion circuit 5, which expands compressed data obtained via the FIFO memory 12 and supplies it to an image memory 17 and a selector 18, which will be described later. 15 is an enlargement/reduction circuit.

The enlarging/reducing circuit 15 obtains input data via the selector 18 and supplies the result of enlarging/reducing processing to a monitor (not shown) via the FIFO memory 13.

16 is a compression circuit. The compression circuit 16 performs compression processing on the output of the image memory 17, which will be described later, and transfers it to the FIFO memory 12.
to the system path via.

17 is an image memory for storing image data. 18 is a selector. The selector 18 is the expansion circuit 14
The image memory 17 output and input are obtained, one of which is selected by a host command and supplied to the enlargement/reduction circuit 15.

FIG. 2 is a diagram cited for explaining the operation of the embodiment of the present invention, in which ■ indicates the state in which data is stored in the image memory, and ■ and ■ indicate the states displayed on the monitor.

The table shown below shows the image data from the host.

This is a list of commands (CMD) for the operations that are issued.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail in comparison with the conventional example.

First, the general operation of the image processing system shown in FIG. 3 will be explained. By starting from the CPU 32, the OCR device 33, image scanner device 34,
Image data is transferred from the optical disk device A35, the magnetic 7"4 disk device 36, etc. to the image data processor 31. The image data processor 31 performs processing such as decompression on the data transferred via the system path. After doing
The image is enlarged, the same size, or reduced and sent to the monitor 32 for display.

Next, the operation of the conventional image processor shown in FIGS. 4 and 5 will be explained. First, in the example shown in Figure 4, microgloss,
Step 31 interprets the commands sent from the host CPC 32 and sends them to the expansion circuit 314, expansion/reduction circuit 315, and image memory 317, including the expansion format, /# parameters such as expansion/reduction, the start address of the image memory, and data. It sets the transfer length, etc. and performs overall control.

Next, when image data is transferred from an optical disk device 315 or the like, it is encoded in an expansion circuit 314 via a FIFO memory 312 provided to absorb the system path transfer speed and image processing speed. Convert the data into normal data. The decompressed data is
The image is once stored in the image memory 317. 2 in FIG. 2 shows the storage state after buffering in the image memory. After all the images are buffered in the image memory 317, the enlargement/reduction circuit 315 operates. The enlargement/reduction circuit 315 performs enlargement, equal size or reduction, etc. on the data in the image memory 312, and uses a FIF for absorbing transfer speed.
The data to be displayed is transferred to the monitor 317 through the O memory 313. ■ and ■ shown in FIG. 2 are the display states on the monitor 317, where ■ is reduced to 1/3, and ■ is the rectangular area abed displayed at the same size. The compression circuit 316 is for encoding raw data that has not been encoded from the image scanner device 34 or the like, and is used when storing the compressed data in the magnetic disk device 36 or the like.

FIG. 5 shows another conventional example that does not have an image memory, in which data from the decompression circuit 314 directly passes through the enlarging/reducing circuit 315 and is sent to the monitor 3 via the FIFO memory 313.
Transferred to 12.

Comparing the above two conventional examples, in the former case, the display is delayed due to buffering in the image memory 317, but once stored in the image memory, the display of enlargement, cropping, etc. of the same image is not possible in the latter case. It's early.

Furthermore, in the latter case, data must be fetched from the peripheral device each time, which requires extra loading time for each enlargement/reduction process. Therefore, the embodiment of the present invention shown in FIG. 1 is provided as a feature that, while writing the output data from the decompression circuit 14 into the image 17, the enlarging/reducing circuit 15 is operated at the same time, and the display data can be transferred to the monitor. This is what I did.

Table 1 above shows an overview of commands from the host CPU 32 to the image processor 31 and their operations. explain.

First, when CMD 1 is output from the host CPU 32, the microprocessor 1 sets the quantity meter etc. in each control circuit. When data is sent from a peripheral device through the system path, it is poured into the decompression circuit 14 via the FIFO memory 12. The decompressed data becomes write data in the image memory 17, passes through the selector 18, and is converted into 1 by the enlarging/reducing circuit 15.
/3, and the display data is transferred to the monitor via the FIFO memory 13.

A supplementary explanation with reference to FIG. 2 is that the state of writing to the image memory 17 (2) and the display state of the monitor (2) proceed simultaneously. Note that when CMD 4 in Table 1 is executed, the selector 18 selects the output of the image memory 17.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(1) Data from peripheral devices can be stored in the image memory and displayed on the monitor at the same time.

(2) Having image memory improves the display speed when cutting out and enlarging the same image0

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram cited to explain the operation of the embodiment of the present invention, and FIG. 3 is a block diagram showing an example of the configuration of a general image processing system. , 4 and 5 are block diagrams showing conventional examples of image-zo processors. 11...Microprocessor, 12.13...FI
FO memory, 14... Expansion circuit, 15... Enlargement/reduction circuit, 16... Compression circuit, 17... Image memory, 18... Selector. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] An expansion circuit that receives compressed data as input and converts it into a raw image; an image memory that stores the output of this expansion circuit as image data; and an image memory that receives the output of the expansion circuit and the image memory output as input and follows host commands. , a selector that selects and outputs either one to the scaling circuit, and a scaling circuit that obtains the output of this selector, performs scaling processing, and outputs it, and writes data to the image memory and uses the scaling circuit to output the image. An image processing method characterized by performing enlargement/reduction processing in parallel.