JPH11328008A - Memory lsi with data processing function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a memory LSI and a memory system which can reduce the data transfer volume, suppress the transfer loss at the time of transferring variable length compressed data, and extend the effective data band width, by compressing data at the time of transfer of data having redundancy and regularity like graphics data. SOLUTION: The timing of the end of reading from a memory LSI 1 is detected by a compression end detection circuit 7 and is outputted as a synchronizing signal 8 to an external controller. This synchronizing signal becomes an issue permission signal for a following instruction. Therefore, the following instruction is quickly issued even if the data length of compressed data outputted from the memory LSI 1 is not fixed and the time required for reading compressed data is not fixed as the result. Consequently, the effective data band width is extended.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic random access memory (DRAM),
The present invention relates to a large-capacity semiconductor memory LSI used for configuring a main storage system or a graphics memory system in a computer system, and more particularly to a memory LSI having a data compression and / or expansion function.

[0002]

2. Description of the Related Art Generally, in a computer system composed of an arithmetic processing unit (CPU) and a memory LSI, C
With the improvement in PU performance, it is necessary to increase the data bandwidth of the memory LSI. For this reason, technical development for improving the data bandwidth of DRAMs, which have a slower access time than other memory LSIs, has been actively conducted.

A technique generally used to improve the data bandwidth of such a memory LSI is to increase the operating frequency of an external interface. At present, the highest data bandwidth is realized by Rambus technology which realizes a data bandwidth of about 600 Mbit / sec per signal line. However, it is technically very difficult to raise the operating frequency further than this because of timing deviation between signal lines, disturbance of the signal waveform due to impedance mismatch of the bus, noise at the time of external or switching, and the like.

As described above, it is difficult to improve the data bandwidth by simply increasing the operating frequency of the external interface on an extension of the existing technology. For this reason, proposals have been made to compress the data to be transferred itself and reduce the amount of transfer to realize an equivalently high-bandwidth memory system.

[0005] One such proposal is Steven A. Przzyb.
"New DRAM Technologies" by ylski, Second Editio
n, MicroDesign Resources, pp. 124-127. The technology proposed here is shown below. Also,
The corresponding drawing is shown in FIG. In the following, the term “frame buffer” is a word indicating a memory area used particularly for drawing a screen.

In the frame buffer 100, two storage areas, that is, an uncompressed drawing data storage area 102 and a compressed drawing data storage area 101 are provided. That is, for the same data, the storage area for uncompressed data is 1
At 02, the storage area for compressed data is 101.
Each is configured as an aggregate of blocks corresponding to a certain area on the screen. Each block of the compressed drawing data area has a marker indicating whether the data of the block is valid or invalid.

When drawing a certain block, the graphics controller 103 first refers to the compressed drawing data of the block. If the compressed drawing data is valid, drawing is performed using the compressed drawing data. When this is invalid, drawing is performed using the uncompressed drawing data of the block. In the latter case, the graphics controller 103
Compresses the non-compressed drawing data of the read block and writes the compressed data in the corresponding block of the compressed drawing data area 101 of the frame buffer. Marks the written compressed drawing data as valid.

The graphics controller 103 and the like
When rewriting the drawing data, writing is performed on the non-compressed drawing data area 102. At this time, the block in the compressed drawing data area 101 corresponding to the rewritten block is marked as invalid. That is, only the newly rewritten block of the compressed drawing data is marked invalid.

According to the above procedure, the amount of data transfer required for drawing a screen can be greatly reduced. Although this prior art document does not specifically mention a method for compressing graphics data, for example, "A Techn
ique for High-PerformanceData Compression ", IEEEE
Computer, Jun 1984, pp.8-19, Terry A. Welch, etc., describe a method for compressing data with redundancy and regularity, and implement the method described in software or hardware. It should be realized. The extent to which the data transfer amount can be reduced by this technique depends on the compression method and the type of image data.
Is expected to be about 1/10 compression.

[0010]

According to the above-mentioned conventional technique using the data compression technique, the amount of data transfer required for screen drawing can be greatly reduced as compared with the case where no compression is performed. However, this conventional technique has the following problems.

A first problem is that the reduction in data transfer amount does not immediately lead to an effective increase in data bandwidth. Generally, a memory LSI has a fixed time from when an instruction is issued from a memory controller to when data transfer starts and ends. This is because the memory controller schedules the use time of the data bus collectively, thereby minimizing the idle time during which data is not transferred on the data bus, and increasing the effective data bandwidth of the data bus. . However, since the data length of the compressed data is not fixed, it is not possible to effectively expand the data bandwidth using the general scheduling method described here.

When this scheduling method is used with the compressed data being regarded as a fixed length, there is only a wasteful space on the data bus by the amount of data reduced by compression. It does not increase the bandwidth. The useless space is generated in the lossless compression because there is no guarantee that the compression can always be performed to a certain ratio or less in any case. In irreversible compression, a fixed length can be used, but there is a problem that the compression performance is poor.

A second problem is that it is impossible to compress data transfer except when drawing a screen. That is,
The data transfer amount when writing data to the memory LSI cannot be reduced. Therefore, when the screen is frequently rewritten, the conventional technique cannot be said to be an effective means.

A third problem is that when the compressed data is invalid, the drawing data is read from the memory LSI, and then the compressed data is written to the memory LSI. That is, useless data transfer for writing compressed data is performed between the memory LSI and the graphics control LSI for a certain period. Therefore, when the screen is frequently rewritten, the effective data bandwidth becomes small, and the conventional technology cannot be said to be an effective means.

An object of the present invention is to reduce the amount of data transfer by performing data compression when transferring data having redundancy and regularity such as graphics data, and to transfer data during variable-length compressed data transfer. An object of the present invention is to realize a memory LSI and a memory system capable of suppressing loss and expanding an effective data bandwidth.

[0016]

A memory LSI with a data processing function according to the present invention has an external input / output terminal, a control circuit, a memory cell array, and a data compressor, and compresses data stored in the memory cell array and outputs the compressed data to an external output terminal. And means for outputting the output end timing to the outside.

Further, the memory with data processing function L of the present invention
The SI has an external input / output terminal, a control circuit, a memory cell array, and a compressed data decompressor, means for inputting compressed data, means for decompressing the compressed data and writing it to the memory cell array, and termination of decompression processing. Means for outputting timing.

Further, the memory with data processing function L of the present invention
The SI may have both of these two functions. That is, external input / output terminals, control circuits, memory cell arrays,
It has a data compressor and a compressed data decompressor, has means for compressing data stored in the memory cell array and externally outputting the data, and means for outputting the output end timing to the outside, and furthermore, It is characterized by having means for inputting data, means for expanding the compressed data and writing it to the memory cell array, and means for receiving the input end timing.

Further, the memory with data processing function L of the present invention
The SI has means for compressing and temporarily storing data stored in the memory cell array, means for externally outputting the stored data, and means for enabling these two operations to be separately operated from the outside. .

Further, the memory with data processing function L of the present invention
The SI is a means for temporarily storing compressed data input from the outside, a means for expanding the stored compressed data and writing it to the memory cell array, and a means for enabling these two operations to be separately operated from the outside And

Further, the memory array of the present invention is capable of storing any number of memories L without data compression and compressed data decompression functions.
A memory array is formed by arranging an SI and an arbitrary number of the above-mentioned memory LSIs with a data processing function, and connected to a memory controller via a bus.

Further, the memory array of the present invention comprises a memory L
Data that is difficult to compress is written into the SI, and compressible data is written into the memory LSI with the data processing function.

According to the present invention, not only the data stored in the memory cell array is compressed and output to the outside, but also the output end timing is output to the outside. Therefore, when a plurality of pieces of compressed data are output, it is possible to reduce the idle time during which the bus is not used, which is generated between the pieces of compressed data, and it is possible to increase the effective data bandwidth at the time of reading data.

According to the present invention, not only is the compressed data decompressed and written into the memory cell array, but also the input end timing is output. Therefore, when a plurality of pieces of compressed data are input, it is possible to reduce the idle time in which the bus is not used between the pieces of compressed data, and it is possible to increase the effective data bandwidth at the time of writing data.

According to the present invention, the operation of compressing and temporarily storing data stored in the memory cell array and the operation of externally outputting the temporarily stored data can be separately operated from the outside. I do. Therefore, during the data compression processing, the memory bus can be used for data transfer of another memory LSI, so that the effective data bandwidth at the time of data reading can be increased.

According to the present invention, the operation of temporarily holding compressed data input from the outside and the operation of expanding the temporarily held compressed data and writing it to the memory cell array are separately performed from the outside. Operable. Therefore, the memory bus can be used for data transfer of another device during the data decompression process,
It is possible to increase the effective data bandwidth at the time of writing data.

Also, a part of the normal memory LSI constituting the memory array is replaced with the memory LSI of the present invention, and data which is difficult to compress is written in the normal memory LSI, and the compressible data is written in the memory LSI of the present invention. By writing, a memory array having a large effective bandwidth can be realized only by adding a part of the interface (adding the signal of the end of compression and the end of decompression).

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a memory LSI 1 with a data compression function includes a memory cell array 2, a data compressor 3, a compressed data buffer 4, a control circuit 5, an address generation circuit 6, a compression end detection circuit 7, and a synchronization signal output terminal 8. ,order/
A data input / output terminal 9 is provided. A data transfer line 200 is used to transfer uncompressed data.

The control circuit 5 inputs a compressed data read command and inputs / outputs data from a command / data input / output terminal. The compressed data read command includes a position (head address) at which data reading from the memory cell array 2 is started. The address generation circuit 6 is provided by the control circuit 5
A read request and a start address are received, and addresses continuous from the start address are issued to the memory cell array 2. The issuance is performed until data of the image size to be compressed is read. The memory cell array 2 reads stored data according to the address issued from the address generation circuit 6. The memory cell array 2 can read stored data and store data under the control of the control circuit 5. The data compressor 3 compresses data read from the memory cell array 2 using a reversible method. The compressed data buffer 4 temporarily stores the data (compressed stream) compressed by the data compressor 3 and outputs the compressed stream to the command / data input / output terminal 9 under the control of the control circuit 5. The compression end detection circuit 7 monitors the address generation circuit 6 and the compressed data buffer 4, detects the end timing of the compressed stream transfer performed through the instruction / data input / output terminal, and outputs the same to the synchronization signal output terminal 8. The control device (not shown) outside the LSI 1 can issue the subsequent instruction promptly by receiving this output signal, so that the subsequent instruction can be issued promptly. Therefore, the effective data bandwidth can be increased.

Next, a detailed configuration of the compression end detection circuit 7 will be described. This compression end detection circuit 7 can be realized by combining, for example, a counter and a comparator.

FIG. 2 is a block diagram showing a configuration example of the compression end detecting circuit 7 according to the embodiment of the present invention. FIG.
, The end-of-compression detection circuit 7 includes a counter 10, a first
Comparator 11, delay circuit 12, second comparator 13, AN
It has a D gate 14 and a driver 15. The counter 10 is controlled by the control circuit 5, and initializes the value held at the start of the compression processing to zero. The counter 10 increases the value held by one each time a data read request from the address generation circuit 6 to the memory cell array 2 occurs.

The first comparator 11 calculates the number of read requests required for the memory cell array 2 from the size of the image to be compressed, and calculates the result of this calculation and the number of times the read request output from the counter 10 has been made. By performing the comparison, a read request end signal is output.

The delay circuit 12 converts the read request end signal output from the first comparator 11 from when the read request is issued from the address generation circuit 6 to when the corresponding data is processed by the data compressor 3. Delay for hours.

The second comparator 13 converts the compressed stream in the buffer by the next compressed stream transfer operation based on the remaining amount of the compressed stream held in the compressed data buffer and not output to the command / data input / output terminal. It detects whether all can be transferred and outputs it.

The AND gate 14 detects from the outputs of the delay circuit 12 and the second comparator 13 that the compression processing has been completed and that all the compressed streams have been transferred in the next transfer processing. The driver 15 outputs the detection result to the synchronization signal output terminal 8.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG.

Normally, a data read command is sent to a memory LSI
, And the time from when the data is read from the memory LSI to the data bus, and the period thereof are fixed. Therefore, the external control device (memory controller) that issues the instruction can issue the subsequent instruction so as to effectively reduce the vacancy of the data bus (the time when the bus is not used for data transfer). However, when data is output after being compressed as in the present embodiment, the period of reading from the memory cell array can be fixed, but the period of reading from the storage device cannot be fixed.

Therefore, in the present embodiment, the timing of the end of reading from the storage device (memory LSI 1) is detected by the compression end detecting circuit 7, and this is output to the external control device as a synchronization signal. This synchronizing signal becomes the issuance permission signal for the subsequent instruction. Therefore, even if the data length of the compressed data output from the memory LSI 1 is not constant and the time required to read the compressed data is not constant, the subsequent instruction can be issued promptly. Therefore, the effective data bandwidth can be increased. Here, the instruction / data transfer is performed in a synchronous manner using an external clock, and the time from when the instruction is issued to when the data is read is set as a t1 cycle.

When the memory LSI 1 with the data compression function receives the compressed data read command (R1), the control circuit 5 transfers the head address (A1) to the address generation circuit 6. The address generation circuit 6 issues a continuous address and a read request to the storage device 2 as many times as necessary to read image data to be compressed (here, six times) based on the received head address. The data compressor 3 is a storage device 2
The compression processing is performed on the data read out from the. And the result is output to the compressed data buffer 4. “Compressor” in the time chart of FIG. 3 indicates the processing of the compressor, and data specified by the address is processed in the next cycle. The control circuit 5 sequentially outputs the compressed stream held in the compressed data buffer 4 to the instruction / data input / output terminal 9 after t1 cycles after the issuance of the compressed read instruction (R1). “Data” in FIG. 3 is the compressed data to be read. The number of cycles required for “output data 1” in FIG. 3 changes depending on the data length after compression.

Here, the reversible compression method will be briefly described. In general, each pixel value of the image data and its adjacent pixel value have a gradual change amount. The following is an example of an image compression unit using this property. First, the image is scanned in the raster scan order, and a difference value between each pixel and the previous pixel is calculated. The difference value obtained as a result of the calculation has a high probability of becoming smaller due to the above-described properties. By utilizing this, it is possible to compress the image data by encoding the difference value with a variable length code.

The compression end detection circuit 7 sets the compression end terminal 8 to a low level (prohibition of subsequent instruction issuance) at the start of the transfer of the compressed stream. The compression end detection circuit 7 holds the number of times a read request from the address generation circuit 6 has been generated by the counter 10. When the value held in the counter 10 reaches the number of times (six times) necessary to read an image, the first comparator 11 and the delay circuit 12 output the result to the AND gate 14. On the other hand, the second comparator 13
Detects whether the remaining compressed stream that has not been output to the compressed data buffer 4 can be output to the instruction / data input / output terminal within the t1 cycle, and compares the result with the AND gate 1
4 is output. When the above two conditions are satisfied, the AND gate 14 sets the synchronization signal terminal to High level (permission of issuing a subsequent instruction (here, R2) in this case) through the driver 15.

Next, the effect of the first embodiment of the present invention will be described. In the present embodiment, the output of the synchronization signal main terminal is monitored, and a subsequent instruction (R2) is issued from the external control device, so that the space of the instruction / data input / output terminal is reduced, and efficient compressed stream transfer is performed. And the data bandwidth can be effectively increased. For example, if the image data is compressed to an average of 25%, the available time can be reduced by 75% and the data bandwidth can be increased about four times.

(Second Embodiment) Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, a memory LSI 1 with a compressed data decompression function includes a memory cell array 2, a compressed data decompressor 20, a compressed data buffer 4, a control circuit 5, an address generation circuit 6, an expansion end detection circuit 21, a synchronization signal output. A terminal 8 and an instruction / data input / output terminal 9 are provided.

The control circuit 5 inputs a compressed data write command and inputs / outputs data from a command / data input / output terminal 9. The memory cell array 2 is used for the compressed data write command.
Contains the start address for writing data. Writing to the memory LSI 1 with the compressed data decompression function is performed by inputting data compressed using a reversible method through the command / data input / output terminal 9.

The address generation circuit 6 receives a signal from the control circuit 5
A write request and a start address are received, and addresses continuous from the start address are issued to the memory cell array 2. The issuance is performed until data of the image size to be expanded is written. The memory cell array 2 includes an address generation circuit 6
The data is written according to the address issued from.

The memory cell array 2 can read stored data and write data under the control of the control circuit 5. The compressed stream is temporarily written into the compressed data buffer 4 through the command / data input / output terminal 9 and the control circuit 5, and the compressed stream is output to the compressed data decompressor 20 under the control of the control circuit 5. The compressed data decompressor 20 decompresses the compressed stream from the compressed data buffer 4 to the original data by inverse conversion of the above-mentioned compression method, and outputs it to the memory cell array 2.
The decompression end detecting circuit 21 monitors the compressed data decompressor 20 to detect the end timing of the decompression processing and outputs it to the synchronization signal output terminal 22. The control device (not shown) outside the LSI 1 can issue the subsequent instruction promptly by receiving this output signal, so that the subsequent instruction can be issued promptly. Therefore, the effective data bandwidth can be increased.

Next, the operation of the circuit of FIG. 4 will be described with reference to FIG.

Normally, the time from when a write command is issued to a memory LSI to when data input to the memory LSI is started and the time period are fixed. For this reason, the external control device (memory controller) that issues instructions has a free data bus (a time when the bus is not used for data transfer).
It is possible to issue subsequent instructions to effectively reduce However, when inputting compressed data as in the present embodiment, the time until data input is started is fixed, but the transfer period is not fixed.

Therefore, in the present embodiment, the timing of the end of writing to the storage device (memory LSI 1) is detected by the decompression end detection circuit 21 and is output to an external control device as a synchronization signal. This synchronizing signal becomes the issuance permission signal for the subsequent instruction. Therefore, even if the data length of the compressed data input to the memory LSI 1 is not constant, and as a result, the time required to write the compressed data is not constant, the subsequent instruction can be issued promptly. Therefore, the effective data bandwidth can be increased.

Here, the transfer of the instruction / data input / output terminal is of a synchronous type using a clock, and the time from the issuance of a compressed data write instruction to the start of data transfer is t2 cycle. The time from the issuance of the compressed data write command to the start of the decompression process is fixed, and this is defined as t3 cycle.

When the memory LSI 1 with compressed data decompression function receives the compressed data write command (W1), the control circuit 5 transfers the head address (A1) to the address generation circuit 6. The address generation circuit 6 issues a continuous address and a write request to the memory cell array 2 as many times as necessary to write image data (here, six times) based on the received start address.

The compressed data buffer 4 starts writing the compressed stream obtained through the instruction / data input / output terminal 9 and the control circuit 5 after t2 cycles from the issuance of the compressed data write command. Compressed data decompressor 2
0 reads the compressed stream from the compressed data buffer 4, reversibly expands the compressed stream, and outputs the original data to the memory cell array 2. The transfer end output terminal 8
The decompression completion detection circuit 21 sets the Low level (prohibition of subsequent instruction issuance) at the same time as the start of transfer of the compressed stream, and sets the High level (permission of subsequent instruction issuance) as early as t3 cycles at which the decompression process ends.

Next, effects of the present embodiment will be described. In the present embodiment, the output of the synchronization signal output terminal is monitored, and a subsequent instruction (W2) is issued from the external control device, thereby reducing the vacancy of the instruction / data input / output terminal and efficiently transferring the compressed stream. It is possible to
The effective data bandwidth at the time of writing can be increased. For example, if the image data is compressed to an average of 25%, the available time can be reduced by 75% and the data bandwidth can be increased about four times.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. This embodiment combines the functions of the LSIs of the first and second embodiments. In other words, the LSI has a data compression / holding function (data compressor 3 and compressed data buffer 4) and a compression end detection / synchronization signal output function (compression end detection circuit 7 and synchronization signal output terminal 8) of the LSI of FIG. An LSI having both the compressed data decompression function (compressed data decompressor 20 and compressed data buffer 4 ') and the decompression end detection / synchronization signal output function (decompression end detection circuit 21 and synchronization signal output terminal 8') of the LSI of FIG. It is.

Data transfer between the external control device and the present memory LSI is performed using compressed data. For this reason, the compressor and the decompressor are used as follows.

At the time of reading: The original data (uncompressed data) stored in the memory cell array is read, and the data is compressed by the compressor 3 and output to the outside. The compression end detection circuit 7 outputs a synchronization signal from the output terminal 8 at the same timing as in the time chart of FIG.

At the time of writing: input compressed data is expanded into original data by an expander, and the original data is stored in a memory cell array. The expansion end detection circuit 21 outputs a synchronization signal from the output terminal 8 'at the same timing as in the time chart of FIG.

The embodiment of FIG. 6 has the effects of the embodiments of FIGS. 1 and 4.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
An embodiment will be described in detail with reference to the drawings.
This embodiment includes a means for compressing data stored in a memory cell array in a reversible manner and temporarily storing the data, a means for externally outputting the temporarily stored data, and a method for externally performing these two operations. Means that can be operated separately.

Referring to FIG. 7, a memory LSI 1 with a data compression function includes a memory cell array 2, a data compressor 3, a compressed data buffer 4, a control circuit 5, an address generation circuit 6, an output end detection circuit 30, and a synchronization signal output terminal 8. , An instruction / data input / output terminal 9.

The control circuit 5 inputs a data compression command and a compressed data read command from a command / data input / output terminal and inputs / outputs data. The data compression instruction includes a position (head address) at which data reading from the memory cell array 2 is started. The output end detection circuit 30 monitors the compressed data buffer 4, detects the end timing of the compressed stream transfer performed through the command / data input / output terminal, and outputs it to the synchronization signal terminal 8. The control device (not shown) outside the LSI 1 can issue the subsequent instruction promptly by receiving this output signal, so that the subsequent instruction can be issued promptly. Therefore, the effective data bandwidth can be increased.

Next, a detailed configuration of the output end detection circuit will be described. This output end detection circuit can be realized by combining, for example, a subtractor and a comparator.

FIG. 8 is a block diagram showing a configuration example of the output end detection circuit 30 according to the fourth embodiment of the present invention. In FIG. 8, the output end detection circuit 30 includes a subtractor 35.
And a difference comparator 36. The compressed data buffer 4 includes a read address register 31, a write address register 32, and a second memory cell array 3.
Three. The second memory cell array 33 writes the compressed data from the data compressor 3 to the location specified by the write address register 32. Also, the second
The memory cell array 33 outputs data at a location designated by the read address register 31 to the instruction / data input / output terminal 9 through the control circuit 5. When data is output from the second memory cell array 33, the read address register 31 changes the held address to the next address. When data is written to the second memory cell array 33, the write address register 32 changes the held address to the next address. Subtractor 34
Calculates the difference between the addresses held in the read address register 31 and the write address register 32. The difference comparator 35 detects that the difference value is equal to or smaller than a certain value, and outputs the result to the synchronization signal output terminal 8.

Next, the operation of the circuit of FIG. 7 will be described with reference to FIG.

Here, the instruction / data transfer is of a synchronous type using an external clock, and the time from the issuance of the instruction to the reading of the data is t4 cycle. When the memory LSI 1 with the data compression function receives the data compression instruction (C), the data read from the storage device 2 is compressed by the data compressor 3 and the compressed data is written to the compressed data buffer 4. Writing to the compressed data buffer 4 is performed at a location specified by the write address register 32. The write address register 32 initializes its value to 0 when receiving the compression instruction. The write address register increments the stored address by one each time data is written to the compressed data buffer 4.

Upon receiving the compressed data read command (R), the memory LSI 1 with a data compression function starts reading the compressed data stored in the compressed data buffer 4 after t4 cycles. The compressed data is output from the location specified by the address held in the read address register 31 and output from the instruction / data input / output terminal 9 through the control circuit 5. The read address register is initialized to 0 when a read command is received,
Each time the compressed data is read, the stored address is incremented by one.

The subtractor 34 calculates the difference between the values held in the read address register 31 and the write address register 32. The difference comparator 35 sets the synchronization signal terminal 8 to Low level when the difference value is 3 or more,
Notifies to the outside that the next instruction cannot be processed. Also,
When the difference value is 2 or less, the comparator 35 sets the synchronization signal terminal 8 to High level, and notifies the outside that the next command is received and can be processed.

Next, the effect of this embodiment will be described. In the embodiment of FIG. 1, when the data processing capacity of the compressor is low, the rate at which the image is substantially compressed is limited by the data processing capacity of the compressor. In the present embodiment, by dividing the operations of compression and data transfer, it is possible to increase the effective data bandwidth without being limited by the data processing capability of the compressor. This will be described with specific numerical values. Data transfer capacity of external memory bus 800 MB / s Data processing capacity of compressor 1600 MB / s. Assume that image data can be theoretically compressed to an average of 25%. In the embodiment of FIG. 1, 800/1600 = 1/2, that is, the compression ratio cannot be substantially increased to more than 50% due to the limitation of the data processing capacity of the compressor. On the other hand, in the embodiment of FIG.
Can be compressed up to.

The compression and data transfer operations of the LSI (third embodiment) shown in FIG. 6 may be separately operable from outside.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 10, a memory LSI 1 with a compressed data decompression function includes a memory cell array 2, a compressed data decompressor 20, a compressed data buffer 4, a control circuit 5, an address generation circuit 6, an input end detection circuit 40, an instruction / data An input / output terminal 9 is provided. The control circuit 5 inputs a compressed data decompression command, a compressed data write command, a compressed data transfer end command, and inputs / outputs data from the command / data input / output terminal 9. In the compressed data decompression instruction, the position (start address) at which data writing to the memory cell array 2 is started
It is included. The input end detection circuit 40 is controlled by the control circuit 5 and controls the operation and stop of the compressed data buffer 4.

Next, the operation of the circuit of FIG.
This will be described with reference to FIG.

Here, the transfer of the instruction / data input / output terminal is of a synchronous type using an external clock, and the time from the issuance of the instruction to the reading of the data is t5 cycle.

Upon receiving the compressed data write command (W), the memory LSI 1 with compressed data decompression function starts receiving data through the command / data input / output terminal 9 after t5 cycles under the control of the input end detection circuit 40. The received data is written to the compressed data buffer 4 through the control circuit 5. When the memory LSI 1 with compressed data decompression function receives the compressed data transfer end command (E), the input end detection circuit 40 stops the writing operation of the compressed data buffer 4. Further, when the memory LSI 1 with the compressed data decompression function receives the compressed data decompression command (D), the compressed data stored in the compressed data buffer 4 is read out by the compressed data decompressor 20 and decompressed by the compressed data decompressor 20. The written data is written to the memory cell array 2.

Next, the effect of the present embodiment will be described. In the present embodiment, the memory bus can be used for data transfer of another device during the data decompression process, so that the effective data bandwidth at the time of data writing can be increased. .

In the LSI (third embodiment) shown in FIG. 6, the operations of decompressing compressed data and transferring data may be separately operable from outside. Further, the LSI shown in FIG.
With regard to the above, each of the operations of compression and data transfer and the operations of decompression and data transfer of compressed data may be separately operable from outside.

(Sixth Embodiment) Next, a sixth embodiment (memory array) of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 12, the memory controller 5
1 has an arbitrary number of memory LSIs via a memory bus 53.
50 and an arbitrary number of memory LSIs 1 with a data compression function and / or a compressed data decompression function. The memory LSI 50 is a normal memory and does not have a data compression function and a compressed data decompression function. Compressible data is written into the memory LSI1, and non-compressible data is written into the memory LSI50.

Memory LSI 50 and Memory Controller 5
Data transfer between 1 is performed with uncompressed data,
The data transfer between the memory LSI 1 and the memory controller 51 performs the above-described compressed data transfer. Memory LSI1
Is any of the LS described in the first to fifth embodiments.
Use I. All of the plurality of memory LSIs 1 may be LSIs having both compression / decompression functions. A part of the plurality of memory LSIs 1 may be a memory LSI with a compression function, a part may be a memory LSI with a decompression function, and the other may be a memory LSI 1 having both a compression / decompression function.

When reading compressed data from the memory LSI 1, the compressed data is expanded in the memory controller 51 and transferred to the arithmetic unit 52. For writing to the memory LSI 1, the data is compressed and transferred by the memory controller 51.

Next, effects of the present embodiment will be described. In the present embodiment, since the expansion of the interface unit is only the compression end and expansion end signals, it can be applied to a memory system in which the current memory LSI is used. Similarly, the speed of the interface can be increased.

(Another Embodiment) In the embodiment described above, compression is all performed by a reversible method. One example has been described in the first embodiment. When compressed by an irreversible method, data cannot be completely restored. However, when dealing with image data, some errors are allowed,
An irreversible compression technique can be used. However, compressed data may have a variable code length even in irreversible compression. That is, even if the original image data has the same size, it is preferable to use a compression method in which the data size after compression differs depending on the image. An example of this is a compression method using DCT (Discrete Cosine Transform). This is to reduce the amount of information by decomposing image data into frequency components by DCT and removing visually insensitive high frequency components.

[0085]

The first effect is that the effective data bandwidth at the time of reading data from the memory LSI can be increased. Therefore, the present invention can be applied to a frame buffer of a computer system.

The reason is that the data stored in the memory cell array is compressed in a reversible manner and output to the outside,
This is because a means for outputting the output end timing to the outside is provided.

The second effect is that the effective data bandwidth at the time of writing data to the memory LSI can be increased. Therefore, even when data rewriting frequently occurs, the present invention can be applied as a frame buffer of a computer system.

The reason is that there are means for expanding the data compressed by the reversible method and writing it to the memory cell array, and means for receiving the input end timing of the compressed data.

The third effect is that the speed of the interface can be increased as in the case of a generally used memory LSI. For this reason, the conventional memory LSI
In this case, the effective bandwidth can be increased.

The reason is that the expansion of the interface section is only the compression end and expansion end signals, and these expanded signals can be applied to the same high-speed technology as the data bus.

The fourth effect is that the present invention can be applied to a memory system in which a current memory LSI is used.

The reason is that the expansion of the interface unit is only the compression end and expansion end signals, and these expanded signals can be realized with the same configuration as the data bus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment (first embodiment) of a memory LSI with a data compression function according to the present invention.

FIG. 2 is a detailed block diagram of a compression end detection circuit of FIG. 1;

FIG. 3 is a time chart for explaining the first embodiment of the present invention.

FIG. 4 is a memory LS with a compressed data decompression function according to the present invention.
FIG. 11 is a block diagram showing a configuration of an embodiment I (second embodiment).

FIG. 5 is a time chart for explaining a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a memory LSI with a data compression function and a compressed data decompression function according to an embodiment (third embodiment) of the present invention.

FIG. 7 is a block diagram showing a configuration of a memory LSI with a data compression function according to an embodiment (fourth embodiment) of the present invention.

8 is a detailed block diagram of the output end detection circuit of FIG.

FIG. 9 is a time chart for explaining a fourth embodiment of the present invention.

FIG. 10 is a memory L with a compressed data decompression function according to the present invention.
FIG. 14 is a block diagram illustrating a configuration of an SI according to a fifth embodiment;

FIG. 11 is a time chart for explaining a fifth embodiment of the present invention.

FIG. 12 is a memory L with a data compression / decompression function according to the present invention;
FIG. 16 is a block diagram illustrating a configuration of an SI according to a sixth embodiment;

FIG. 13 is a block diagram of a memory system using a conventional data compression transfer.

[Explanation of symbols]

Reference Signs List 1 Memory LSI with data compression function and / or compression data expansion function 2 Memory cell array 3 Data compressor 4, 4 'Compressed data buffer 5 Control circuit 6 Address generation circuit 7 Compression end detection circuit 8, 8' Synchronization signal output terminal 9 Command / data input / output terminal 10 Counter 11 First comparator 12 Delay circuit 13 Second comparator 14 AND gate 15 Driver 20 Compressed data decompressor 21 Decompression end detection circuit 30 Output end detection circuit 31 Read address register 32 Write Address register 33 Second memory cell array 34 Subtractor 35 Difference comparator 40 Input end detection circuit 50 Memory LSI 51 Memory controller 52 Arithmetic unit 53 Memory bus 100 Frame buffer 101 Compressed drawing data area 102 Uncompressed drawing data Pass 103 graphics controller

Claims (9)

[Claims] A means for compressing data stored in the memory cell array and outputting the compressed data to the outside, and an output end timing for outputting the output end timing to the outside; A memory LSI with a data processing function. Means for inputting compressed data, means for inputting compressed data, means for writing the compressed data into the memory cell array, and expansion processing. Output means for outputting the end timing of the memory LSI. 3. An external input / output terminal, a control circuit, a memory cell array, a data compressor and a compressed data decompressor, means for compressing data stored in the memory cell array and externally outputting the data, Means for outputting compressed data, means for inputting compressed data, means for expanding and writing the compressed data to the memory cell array, and means for receiving the input end timing. Memory LSI with a data processing function. 4. A means for compressing and temporarily storing data stored in a memory cell array, a means for externally outputting the stored data, and a means for enabling these two operations to be separately operated from the outside. 4. The memory LSI with a data processing function according to claim 1, comprising: 5. A means for temporarily storing compressed data input from the outside, a means for expanding the stored compressed data and writing it to the memory cell array, and these two operations can be separately operated from the outside. 4. The memory LSI with a data processing function according to claim 2, further comprising: 6. A memory array in which an arbitrary number of memory LSIs having no data compression and compressed data decompression functions and a memory LSI with a data processing function according to claim 1, 2, 3, 4 or 5 are arranged. A memory array to configure and connect to a memory controller via a bus. 7. The memory array according to claim 6, wherein hard-to-compress data is written to the memory LSI, and compressible data is written to the memory LSI with the data processing function. 8. The method according to claim 1, wherein data compression is performed reversibly.
6. The memory LSI with a data processing function according to 2, 3, 4, or 5. 9. The memory array according to claim 6, wherein data compression is performed reversibly.