JPS60254280A - Picture processor - Google Patents

Abstract

PURPOSE:To process a picture with high efficiency through expansion if only the pictures of a desired area by storing the transfer data to a memory after compressing it and also providing a table that holds the addresses storing the head data of each scan. CONSTITUTION:The compressed picture data is transferred from a CPU1, and a picture processor 2 receives this data through an interface circuit 3 and writes it successively to a memory 4. At the same time, the compressed data received by the circuit 3 is sent to an EOL decision circuit 5. Then an EOL pattern of the section mark showing the head of a line is detected. When the writing of the compressed data is through to the memory 4, a table showing the heads of each line is added to an address table 7. An expansion circuit 9 expands the data of the memory by the address extracted from the table 7 in order to obtain an original picture of only a desired area.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an image processing device capable of efficiently performing image processing on compressed image data transferred from a central processing unit (CPU). Prior Art and Problems Conventionally, when compressed image data is processed between a central processing unit (CPU) and an image processing device, there is a method in which the CPU decompresses the compressed image data and transfers it as original image data to the image processing device, and There are two methods in which compressed image data is received as-is by an image processing device and decompressed by the image processing device.In the former, the CPU generally does not have special dedicated hardware to decompress the image data into the original image. , is performed by software ◎As a result, the burden is placed on the CPU, and
A large amount of data (original image) must be transferred, which is not good in terms of time or efficiency.Also, the latter method involves receiving compressed image data from the CPU, decompressing it, and storing it in memory, or compressing it once in memory. There is a method of storing image data and then reading out the stored compressed image data again to decompress it. The data length of the compressed image data sent from the CPU is variable and short, but the data length decompressed on the image processing device side is constant and long, so it fluctuates over an hour. There may be a problem in absorbing temporal fluctuations in the decompression operation with the interface, or even if the part you want to actually process is a limited area of the compressed image data sent from the CPU, all There are problems such as having to decompress, which wastes time and memory resources.

(c) Purpose of the Invention The purpose of the present invention is to reduce the load on the interface with the CPU by converting data transferred from the CPU into compressed data, and to store the compressed data in the memory so that the image processing device only requires a small amount of memory. Furthermore, it is an object of the present invention to provide an image processing device that can perform efficient image processing by decompressing only the necessary portion of the image by creating a table that holds addresses storing the first data of each scan. .

(d) Structure and object of the invention According to the present invention, in an image processing device connected to a central processing unit, which includes an interface circuit, a memory address control circuit, a memory, and an image processing unit, an a detection circuit that stores the compressed image data in the memory without decompressing it, and detects a line delimiter signal of the compressed image data; and the memory corresponding to the address of the line delimiter detected by the detection circuit. The image processing unit is equipped with an address table indicating storage addresses in the address table, and an expansion circuit for extracting and decompressing data in the memory from the table address of a portion of the address table where image processing is to be performed. This is achieved by providing an image processing device characterized in that it outputs images to a destination.

(e) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

Recently, facsimiles have been increasingly used as image input devices to central processing units (CPUs).

3- As a result, the image data is compressed data based on the MH compression method, etc., and the CPU is designed to handle this compressed data. However, when processing an image becomes complex, such as moving, framing, reducing, or enlarging an image written on paper, the processing is performed using dedicated hardware rather than software. This makes it possible for image processing devices to handle compressed data.

FIG. 1 shows a configuration diagram of an embodiment of an image processing device of the present invention, in which l is a CPU, 2 is an image processing device, 3 is an interface circuit, 4 is a memory, 5 is an EOL determination circuit, and 6
is a table address control circuit, 7 is an address table,
8 is a memory address control circuit.

9 is an expansion circuit, 10 is an image processing unit 0CPU
The compressed image data is transferred from I, and the image processing device 2 receives this data through the interface circuit 3 and sequentially writes it into the memory 4. At the same time, the compressed data received by the interface circuit 3 is sent to the EOL determination circuit 5. The 0 image data that is displayed is compressed data, as shown in Figure 2, and 1
Data amount a for the first scan, data amount s for the second scan,
In the data amount C1 of the third scan, there is a delimiter P indicating the beginning of the line. This delimiter P
There is an EOL determination circuit 5 as a detection circuit for detecting the EOL pattern. When the EOL determination circuit 5 detects the line delimiter P.

The interval table address control circuit 6 writes the address at which the cut symbol P 1i1i0L is currently written in the memory 4 into the address table 7 as shown in the third column. Address A of this memory 4 is generated by a memory address control circuit 8.

Further, the table address control circuit 6 updates the table address B using a signal from a circuit that accesses the memory.

When the compressed data has been written to the memory 4, a table indicating the beginning of the data of each line is created in the address table 7. Then, the decompression circuit 9 retrieves the memory address A that contains the first data of the part to be subjected to image processing from the address table 7, and decompresses the data in the memory 4 from that address to obtain the original image of only the necessary part. By sending this original image to the image processing unit 10, processing it, and writing the result to memory, the image is expanded to only the necessary area for the compressed image data, making it more efficient in terms of time and memory resources. This allows for better image processing.

(f) Effect of the Invention As explained in detail above, the image processing device of the present invention has C.
I want to store the compressed image data transferred from the PU in memory without decompressing it, detect the line delimiter, create an address table that stores the first data of each line, and perform image processing from this address table. By finding the first line of a part, expanding only the necessary part into the original image, and performing image processing, it is possible to handle large amounts of transferred original image data, like a conventional image processing device.
Alternatively, since all of the transferred compressed image data is not decompressed, the amount of transferred data at the ink face on the image processing device side can be reduced, and only the necessary parts can be restored to the original image.

Efficient image processing becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an image processing apparatus of the present invention, FIG. 2 is a diagram for explaining line delimiters of compressed image data, and FIG. 3 is a diagram showing an address table of the present invention. be. In the figure, l is a CPU, 2 is an image processing device, 3 is an interface circuit, 4 is a memory, 5 is an EOL determination circuit, 6
is a table address control circuit, 7 is an address table,
8 is a memory address control circuit. 9 indicates the decompression circuit, 10 indicates the image processing unit〇brown 1
Country V: 3rd

Claims (1)

[Claims] In an image processing device having an interface circuit, a memory address control circuit, a memory, and an image processing unit connected to a central processing unit, compressed image data transferred from the central processing unit is stored in the memory without being expanded. a detection circuit for detecting a line delimiter of the compressed image data; an address table indicating a storage address in the memory corresponding to the address of the line delimiter detected by the detection circuit; and an image of the address table. An image processing apparatus comprising: an expansion circuit that extracts and expands data in the memory based on a table address of a portion desired to be processed, and outputs original image data from the expansion circuit to the image processing unit.