JP2862121B2 - Image processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit, and more particularly to an image processing circuit for performing high-speed image data expansion processing.

[0002]

2. Description of the Related Art When reading and expanding image data compressed and recorded on a recording medium such as a magneto-optical disk, a hard disk or a floppy disk, usually,
Since the processing speed of the decompression circuit is faster than the data reading speed of the recording medium, an operation of storing a required amount of data read from the recording medium in a memory and transferring the data to the processing circuit is performed.

[0003]

As described above, the fact that the writing speed of the memory or the processing speed of the decompression processing circuit is faster than the reading speed of the compressed data from the recording medium means that there is an empty space during the operation of the memory. It means you have time. In view of the above, the present invention starts reading data when a required amount of compressed data is taken from a recording medium into a memory, transfers the data to a decompression processing circuit, and starts decompression processing. Another object of the present invention is to provide a method for speeding up the decompression process.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a memory unit for recording compressed image data taken from an external memory, and a decompression process for compressed image data read out and transferred from the memory unit. A decompression processor unit, an image processing control unit that outputs a control signal for decompression processing,
A first counter which counts the number of data recorded in the memory unit and outputs a signal at a required count value; and a second counter which counts the number of data transferred to the decompression processor unit, adds a required value, and outputs the result. A comparison circuit that compares the number of data from the external memory with a value from a second counter and outputs a signal when the number reaches the same number; and a signal from the first counter that turns on a signal from the comparison circuit. And an ON / OFF circuit for sending a decompression control signal from the image processing control section to the decompression processor section during the period of turning off and on.

[0005]

With the above arrangement, in the image processing circuit according to the present invention, when decompressing compressed image data recorded in an external memory such as a magneto-optical disk, data read from the external memory is stored in the memory. When the number of addresses for writing and writing data reaches a required amount, reading is started and transferred to the decompression processor to start decompression processing. The decompression process is interrupted when the number of data to be transferred becomes smaller than a required value than the number of write data addresses, and the decompression process is interrupted when the number of write data addresses reaches the required amount. To continue.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image processing circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a main part of an embodiment of an image processing circuit according to the present invention. In FIG. 1, reference numeral 1 denotes an external memory, which is composed of a recording medium capable of recording / reproducing image data, for example, a magneto-optical disk, a hard disk, a floppy disk, or the like, and records image data and the like which have undergone required compression processing. 2 is a memory unit, which is compressed image data read from the external memory 1,
Alternatively, compressed image data or the like for recording in the external memory 1 is recorded. 3 is DMA (direct memory ac)
cess) The control unit 4 is a CPU, and the DMA control unit 3 or the CPU 4 controls writing / reading between the external memory 1 and the memory unit 2 and the like. Reference numeral 5 denotes a compression / decompression processor which performs decompression processing of compressed image data or compression processing of uncompressed image data. Reference numeral 6 denotes an image processing control unit which controls the compression / decompression processor unit 5 and controls writing of the data processed by the compression / decompression processor unit 5 to the memory unit 2. Reference numeral 7 denotes a data input unit for inputting uncompressed image data and the like. Reference numeral 8 denotes a frame memory for recording image data from the data input unit 7.
Reference numeral 9 denotes a monitor for displaying on a screen based on the image data read from the frame memory 8.

Next, the operation of the image processing circuit according to the present invention will be described with reference to the detailed block diagram of the main part of the memory section 2 shown in FIG. First, when decompressing the compressed image data, under the control of the DMA controller 3 or the CPU 4, the compressed data and addresses read from the external memory 1 are input from the data terminal 11, latched in the buffer 12, and , And sequentially input during an I / O (data input / output operation) period to record one image. The compressed image data recorded in the memory 13 is read out, latched in the buffer 14, and sent out from the data terminal 15 to the compression / decompression processor unit 5. The memory 13 switches the switch 16 via the memory control circuit 16 based on a required memory switching clock signal, and performs a data input / output (I / O) operation or a compression / expansion (C / D) operation. Switch to.

In reading the compressed image data from the external memory 1, a memory address signal for each data from the DMA control unit 3 or the CPU 4 is supplied to an address terminal.
Input from 18 and + m via I / O interface 19
It is input to the circuit 20 and counts. The + m circuit 20 outputs a signal when the number of input signals reaches a required value, and is turned on by this signal.
The / OFF circuit 21 is turned on, and the image processing control unit 6 input from the terminal 22 via the C / D interface 23
The expansion control signal is sent to the compression / expansion processor unit 5 via the terminal 24. The compression / decompression processor unit 5
The expansion processing of the compressed image data transferred from the memory 13 is started based on the expansion control signal.

The number of data transferred from the memory 13 to the compression / decompression processor section 5 is counted by a counter 25, a signal from the counter 25 is applied to a + n circuit 26, and a predetermined required value is added. Input to the comparison circuit 27. Comparison circuit 27
Compares the value from the + n circuit 26 with the number of address signals input from the address terminal 18 via the buffer 28,
When the value from the n circuit 26 becomes equal to the number of address signals, a signal is output, the ON / OFF circuit 21 is turned off, and the transmission of the decompression control signal to the compression / decompression processor 5 is stopped.
Interrupt the decompression process. Thereafter, the comparison circuit 27 continues to compare the value from the + n circuit 26 with the number of address signals from the address terminal 18. When the value from the + n circuit 26 becomes smaller, a signal is output. The circuit 21 is turned on to output a decompression control signal to the compression / decompression processor 5, and the decompression processing of the interrupted image data is continued. Note that the switch 30 is off during the decompression processing operation.

When the transfer of the compressed image data from the external memory 1 to the memory 13 is completed, the operation of the + m circuit 20 is inhibited based on the transfer end flag from the CPU 4 and turned on.
The ON / OFF circuit 21 is turned on, and all the compressed image data remaining in the memory 13 is transferred to the compression / decompression processor unit 5 to perform decompression processing. The compression / decompression processor unit 5 stops the decompression processing according to the end code of the compressed image data. With the above operation, even if the reading speed of the data from the external memory 1 and the decompression processing speed of the compression / decompression processor unit 5 are different, there is no problem in the decompression processing of the compressed image data.

The memory capacity of the memory 13 is, for example,
The high-definition signal compressed to 1/10 is set to be capable of recording two images, and the image data is input to the monitor 9 via the frame memory 8 to check the expanded image, and the image is displayed on the screen. While the next compressed image can be captured while the compression ratio is 1/10 or less (1/5
) To use the full capacity for one image,
Alternatively, when the compression ratio is 1/10 or more, compressed data of two or more images can be taken.

Next, the operation of compressing image data will be described. Uncompressed image data is input from the data input unit 7,
The image data is input to the compression / decompression processor unit 5 via the frame memory 8, and compression processing is performed according to a signal from the image processing control unit 6. The compressed image data is input to the memory unit 2 via the image processing control unit 6 and recorded. When writing the data in the memory unit 2 to the external memory 1, the data is transferred to the external memory 1 with information such as the data amount to be recorded in the header area of the data and the data compression ratio.

That is, the image data compressed by the compression / expansion processor 5 is buffered from the data terminal 15.
14, latched, input to the memory 13 during the C / D period, write is performed, the number of addresses of input data is counted by the counter 25, latched in the buffer 29, and
The data is input to the memory 13 during the C / D period of the memory 13 via the memory and written. Then, the switch 30 is turned on by a signal from the I / O interface 19, and an end code based on the last address recorded in the counter 25 is sent out.
To record. After the writing of the compressed image data to the memory 13 is completed, a control signal is output to the CPU 4 or the DMA control unit 3 via the I / O interface 19 to control the external memory 1 to write the compressed image data. Information such as the length and the compression ratio is added to the data header area, and the compressed image data in the memory 13 is read and transferred to the external memory 1 for recording.

When the recording capacity of the memory 13 is set to the capacity of two compressed images and the number of frames of the frame memory 8 is set as appropriate, when multiple images are continuously compressed, for example, While the previously processed compressed image data is transferred to the external memory 1 (I / O period), the next image data can be subjected to the compression processing (C / D period) in parallel with this. The image compression processing speed after the eye can be increased. Alternatively, two images having different compression ratios can be written, compared, selected, and written to an external memory.

[0015]

As described above, according to the image processing circuit of the present invention, the memory circuit is operated by switching between the data input / output operation and the image decompression processing by the clock, and the compressed image data is stored in the memory. Can be started when the required amount is input, so that when a plurality of compressed images are continuously expanded, the processing results of the second and subsequent images can be obtained earlier than before. Also, the recording capacity of the memory is set to about two compressed images, and the I / O
By selectively using the period and the C / D period, while confirming the decompressed image, the decompression process of the next image is performed in parallel with this, or the transfer of the compressed image and the next image compression The processing speed can be increased by performing the processing in parallel or the like. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an embodiment of an image processing circuit according to the present invention.

FIG. 2 is a main block diagram of a memory circuit of the image processing circuit according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 external memory 2 memory unit 3 DMA control unit 4 CPU 5 compression / decompression processor unit 6 image processing control unit 7 data input unit 8 frame memory 11 data terminal (compressed image data input / output) 13 memory 15 data terminal (uncompressed image data Input) 16 Memory control circuit 17 Switch 18 Address terminal 20 + m circuit 21 ON / OFF circuit 22 terminal (expansion control signal input) 24 terminal (expansion control signal output) 25 Counter 26 + n circuit 27 Comparison circuit

Claims (3)

(57) [Claims] 1. A memory means for recording compressed image data taken from an external memory, a decompression processor means for decompressing compressed image data from a memory means, and an amount of data recorded in the memory means. A memory unit for recording compressed image data fetched from an external memory; and a compressed image data read from the memory unit and transferred. A decompression processor unit that performs decompression processing, an image processing control unit that outputs a control signal for decompression processing, a first counter that counts the number of data recorded in the memory unit, and outputs a signal with a required count value;
A second counter that counts the number of data transferred to the decompression processor unit, adds a required value and outputs the result, and compares the number of data from the external memory with the value from the second counter. A comparison circuit for outputting a signal; turned on by a signal from the first counter; turned off by a signal from the comparison circuit; and sent a decompression control signal from the image processing control unit to the decompression processor during the on period. An image processing circuit composed of an ON / OFF circuit. 2. A data input unit for inputting uncompressed image data, and a compression processor unit for compressing image data from the data input unit, and recording the compressed image data from the compression processor unit in the memory unit. 2. The image processing circuit according to claim 1, wherein the compressed image data is read from the memory unit and recorded in the external memory. 3. The storage capacity of the memory unit is reduced to two compressed images.
Set the capacity to record more than the image, and
The second compressed image data can be written during displaying the expanded image of the first compressed image data on the monitor screen, and the like. 2. The image processing circuit according to claim 1, wherein the writing of the second compressed image data from the compression processor unit can be performed while transferring the written first compressed image data to the external memory.