JPS62176898U - - Google Patents
Info
- Publication number
- JPS62176898U JPS62176898U JP6432586U JP6432586U JPS62176898U JP S62176898 U JPS62176898 U JP S62176898U JP 6432586 U JP6432586 U JP 6432586U JP 6432586 U JP6432586 U JP 6432586U JP S62176898 U JPS62176898 U JP S62176898U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- control means
- display
- outputting
- converting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 102100029968 Calreticulin Human genes 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 101100326671 Homo sapiens CALR gene Proteins 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案の一実施例の要部構成図、第２
図は本考案の一実施例の全体構成図、第３図は第
１図の実施例の動作を示すタイムチヤート、第４
図ａ，ｂはＰＤＰ用のタイミング信号のタイムチ
ヤート、第５図はＣＲＴ表示制御装置のタイムチ
ヤート、第６図はＰＤＰ表示制御装置のタイムチ
ヤートである。
１００…マイクロプロセツサ（μｐ）、１０１
…メインメモリ（ＭＭＥＭ）、１０２…表示制御
装置、１０３…変換部、１０４…ＰＤＰ（プラズ
マ表示パネル）、１０５…バス、１…表示制御部
（ＣＲＴＣ）、２―１，２―２…Ｓ／Ｐ変換部、
３―１，３―２…トライステートドライバ、４…
ライト制御回路、５…クロツク制御回路、６…ラ
イトアドレスカウンタ、７…バツフアメモリ、８
…切換器、９…レジスタ、１０…リードアドレス
カウンタ、１１…リード制御回路、１２…ＰＤＰ
タイミング発生回路。
Figure 1 is a configuration diagram of the main parts of an embodiment of the present invention, Figure 2
The figure is an overall configuration diagram of one embodiment of the present invention, FIG. 3 is a time chart showing the operation of the embodiment of FIG. 1, and FIG.
Figures a and b are time charts of timing signals for PDP, Figure 5 is a time chart of a CRT display controller, and Figure 6 is a time chart of a PDP display controller. 100...Microprocessor (μp), 101
...Main memory (MMEM), 102...Display control device, 103...Conversion unit, 104...PDP (plasma display panel), 105...Bus, 1...Display control unit (CRTC), 2-1, 2-2...S/ P conversion section,
3-1, 3-2... tri-state driver, 4...
Write control circuit, 5... Clock control circuit, 6... Write address counter, 7... Buffer memory, 8
...Switcher, 9...Register, 10...Read address counter, 11...Read control circuit, 12...PDP
Timing generation circuit.
Claims (1)
グ信号を作成し、作成した各信号に基づいて表示
装置の表示を制御する制御手段を備えた表示制御
装置において、 前記制御手段からの映像信号をパラレルデータ
に変換して出力する複数の変換手段と、 前記制御手段に与えられるクロツク信号より装
置のタイミング信号を発生すると共にプラズマ表
示装置を走査するためのタイミング信号を発生し
て出力する信号発生手段と、 １画面分の映像信号を格納する記憶手段と、 前記制御手段及び信号発生手段からのタイミン
グ信号に基づいて、前記変換手段を選択し、該出
力データの前記記憶手段への書込みを制御するラ
イト制御手段と、 前記信号発生手段からのタイミング信号に基づ
いて、前記記憶手段からの読出しを制御してパラ
レルデータを出力するリード制御手段とを設けた
ことを特徴とする表示制御装置。[Claims for Utility Model Registration] A display control device comprising a control means for creating a serial video signal and a timing signal for scanning and controlling the display of a display device based on each of the created signals, the control means a plurality of converting means for converting the video signals from the converter into parallel data and outputting the parallel data; and generating a timing signal for the device from a clock signal given to the control means and a timing signal for scanning the plasma display device. a signal generating means for outputting; a storage means for storing video signals for one screen; and selecting the converting means based on timing signals from the control means and the signal generating means, and transmitting the output data to the storage means. A display comprising: a write control means for controlling writing of data; and a read control means for controlling reading from the storage means and outputting parallel data based on a timing signal from the signal generation means. Control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6432586U JPS62176898U (en) | 1986-04-30 | 1986-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6432586U JPS62176898U (en) | 1986-04-30 | 1986-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62176898U true JPS62176898U (en) | 1987-11-10 |
Family
ID=30900382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6432586U Pending JPS62176898U (en) | 1986-04-30 | 1986-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62176898U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276536A (en) * | 1988-04-27 | 1989-11-07 | Fujitsu Ltd | Plasma display |
-
1986
- 1986-04-30 JP JP6432586U patent/JPS62176898U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276536A (en) * | 1988-04-27 | 1989-11-07 | Fujitsu Ltd | Plasma display |
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