JP3349271B2 - Digital still camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital still camera , and more particularly to a digital still camera capable of improving the quality of an image recorded on a recording medium.

[0002]

2. Description of the Related Art In an image handling apparatus, such as a digital still camera, which records image information as image data on a recording medium such as an IC memory card, an I / O used as a recording medium is used.
Since the recording capacity of a C memory card or the like is relatively small, an image signal obtained from an image sensor is recorded in a frame memory in order to increase the number of pieces of image information (photographed subject images) to be recorded. It is usual to compress the image data read in step 1 and record it on a recording medium. At the time of reproduction, the image data read from the recording medium is subjected to decompression processing, which is the reverse processing of the compression, and then the image is reproduced.

[0003]

As described above, in a conventional image handling apparatus, compressed image data is recorded on a recording medium. However, the image targets to be photographed vary widely, from those containing very fine information to extremely simple shapes, and if the compression processing as described above is applied uniformly and recorded on a recording medium, the reproduced image In some cases, there is a problem that the image quality is significantly deteriorated. Further, when a controller exists in each of a frame memory and an IC memory card, there is a problem that the number of I / Os increases, and further, unnecessary noise occurs when a large number of clocks exist in the I / Os. There is also a problem. Further, as will be described later, conventionally, a simple synchronization process of color difference line sequential data has been performed. Therefore, there is a problem that the resolution in the vertical direction of the color is low, and the color blur is conspicuous on the screen.

Accordingly, an object of the present invention is to provide a method for compressing image data.
Adapted to each signal data array of compressed and uncompressed
Digital still camera with easy-to-use recording control
Is to provide. Another object of the present invention is to provide an image
Digital that can prevent image quality degradation when quality is important
It is to provide a still camera.

[0005]

In order to solve the above-mentioned problems, a digital still camera according to the present invention includes a memory capable of temporarily storing generated or supplied image data, and an image data stored in the memory. a memory control means for controlling writing and reading of, n × from the memory
data compression transfer means for performing processing using DCT transformation and compression processing on image data read as block data of n pixels and supplying the processed data to the applied information recording medium; and color information interpolation processing from the memory. Data uncompressed transfer means for supplying the read image data as image data to the applied information recording medium without passing through the image data compression means; and When controlling the writing of image data and supplying the image data to the applied information recording medium by the data non-compression transfer means, the image data subjected to color interpolation processing to the applied information recording medium is used as the image data. Information recording medium control means adapted to control writing of image data to be transmitted; and When supplying image data to the used information recording medium, a control signal relating to the compression processing is supplied to the information recording medium control means, and the image is transferred to the applied information recording medium by the data non-compression transfer means. When supplying data, the operation type of the information recording medium
The clock supplied to control the
The image is transferred to the information recording medium applied by the compression transfer means.
In the same state as when supplying data,
The control signal synchronized with the control signal of the memory by the control means
A control signal is supplied so as to supply the information recording medium control means.
Switching means for switching. here,
The data compression transfer means or the data non-compression transfer means
It is possible to further have a mode setting means for selectively applying
Wear.

[0006]

According to the present invention, the data non-compression transfer means
As image data subjected to color information interpolation processing from memory
The read image data is not passed through the image data compression means.
Supplied to the information recording medium by the information recording medium control means.
To control the writing of image data to the information recording medium
First, the image on the information recording medium by the data
The writing of the image data is controlled when the image data is supplied. Soshi
And information by the data compression and transfer means by the switching means.
When supplying image data to the recording medium,
Control signal is supplied to the information recording medium control means and data is not compressed
When the image data is supplied to the information recording medium by the transfer means
Is related to the color information data of the image data read from the memory.
Color information interpolation on the information recording medium.
Color information interpolation processing to supply as processed image data
Control signal to supply the image data
Switch. Also, the information recording medium is transmitted by the data compression transfer means.
When supplying image data to the body, control signals related to compression processing
For writing image data to the information recording medium
Control signal, and the data
Supply of image data that has been subjected to color information interpolation processing to a recording medium
At the same time as the memory control signal from the memory control means.
Write the expected control signal to the image recording medium
Are supplied as control signals.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a digital still according to the present invention.
It is a basic block diagram of a camera . Mode setting unit 12
Accordingly, a compression mode in which image data is compressed and recorded and a non-compression mode in which image data is not directly compressed and directly transferred to a memory card as a recording medium and recorded are selected.
The subject image signal obtained by the CCD 1, which is an image sensor, is
After a predetermined imaging process is performed by the imaging process circuit 2, A
The image data is converted into digital image data by the / D converter 3 and temporarily stored in the frame memory 4.

In a compression mode in which normal compression processing is performed, image data read from the frame memory 4 is supplied to a DCT (discrete cosine transform) unit 6 via a terminal 5 B of a selector 5.
Is output to Writing / reading from the frame memory 4 is performed in accordance with an address signal from the frame memory controller 10 under the control of the CPU 11. The image data output from the frame memory 4 is DCT-converted by the DCT unit 6, compressed by the compression / decompression unit 7, and then recorded on the memory card 9 via the terminal 8 B of the selector 8.

On the other hand, at the time of reproduction, the image data read from the memory card 9 is expanded by the compression / expansion unit 7 via the terminal 8B of the selector 8, and subjected to inverse DCT (IDCT) conversion by the DCT unit 6. The data is temporarily stored in the frame memory 4 via the terminal 5B of the selector 5. The image data read from the frame memory 4 is converted into an analog signal by the D / A converter 15 and supplied to the monitor system as a reproduction output.

The writing / reading of the memory card 9 is performed by the CP
It is controlled by the memory card controller 14 under the control of U11. The CPU 11 controls the entire apparatus, and sends various control signals based on operation instruction information from various operation units. In this example, predetermined operation control is performed based on the mode setting information from the mode setting unit 12 in which the user selects the compression / non-compression mode.

The above operation is an operation for performing normal compression / decompression processing. However, when a user desires high image quality, for example, when a recorded image contains detailed information accompanied by image quality deterioration,
The user selects an operation without performing the compression / expansion processing by the mode setting unit 12. In this case, selectors 5 and 8
Selects the terminals 5A and 8A respectively by a switching control signal from the CPU 11, and directly transfers the image data read from the frame memory 4 to the memory card 9 via the terminal 5A of the selector 5 and the terminal 8A of the selector 8. Record. This switching control signal is also supplied to the DCT section 6 and the compression / expansion section 7, and in the above-described operation in which the compression / expansion processing is not performed, the operation is stopped to save power.

The selector 13 controls the memory card controller 14 in a compression mode and in a non-compression mode, and controls a control signal from the compression / expansion unit 7 via a terminal 13B in the compression / recording mode. In the recording mode, the frame memory controller 10 is connected via the terminal 13A.
Supplies a signal CONT2 for timing adjustment.

In the above operation, the mode of data transfer from the frame memory 4 in the compression recording mode and the non-compression recording mode is different. In the compression recording mode, data read as block data from the frame memory 4 is stored in the DCT unit 6.
Supplied to That is, as shown in FIG. 3C, the Y signal is obtained for each pixel, while the color signal is two Y signals.
Since one color signal CB1 and one color signal CR1 are obtained for each of the 1 and Y2 signals, as shown in FIG. 2A, two blocks each of the Y signal and one block of the color signal (CB or CR) are nxn. The data is transmitted as pixel block data in the order shown in FIG. In the non-compression recording mode, data to be transmitted is pixel-sequential dot-sequential data as shown in FIG.

FIG. 3 is a block diagram showing a configuration of a storage circuit for Y signals and color signals to the frame memory 4 under the control of the memory controller 10. Frame memory 4
Is a Y0 memory 4A for storing data Y0 and Y1 as Y signals and data CB and CR as color signals, respectively.
One memory 4B, a CB memory 4C, and a CR memory 4D are provided, and each of 4A, 4B, 4C, and 4D has a capacity for a frame by two memory chips for one field.
The data Y0, Y1, CB and CR are stored in the corresponding memories by the chip select signal CS, the write enable signal WE, and the write enable signal WE supplied from the memory controller 10.
It is controlled by an output enable signal OE and an address signal.

FIG. 4 shows a memory map at the time of writing image data to the frame memory 4. In the effective screen area of the memory area, the horizontal direction corresponds to A0 to A8 (7
68 pixels) correspond to the horizontal address, and A9 to A16
(240 lines) corresponds to a vertical address. Here, as described with reference to FIG. 2, since the color signal is half of the Y signal, the horizontal direction is 384 pixels. This address assignment is made for the capacity of the field data. As shown in the figure, two memory chips, A field and B field, can be controlled by the same address. Is provided.

FIG. 5 is a timing chart of the recording process in the non-compression mode in FIG. The clock DCLK from the frame memory controller 10 is a reference clock for operations supplied to the DCT unit 6, the compression / decompression unit 7, and the memory card controller 14. Signal CNT1
Is supplied from the CPU 11 to the frame memory controller 10 and the memory card controller 14, and a data transfer instruction to the memory card 9 is performed. The signal CNT2 is
This signal is supplied from the frame memory controller 10 to the memory card controller 14 for timing adjustment, and is used for resetting the frequency divider and the address counter. The DCLK is divided into two and four at the same timing by the frame memory controller 10 and the memory card controller 14, respectively. In the frame memory controller 10, the select signal 1, the select signal 2, and the frame memory address are stored in the memory card controller 14
Then, a memory card address is generated. The frame memory address signal is latched by DCLK and supplied to each memory. According to the same memory address, for example, address "0", the Y0 memory 4A and the Y1 memory 4 shown in FIG.
The data Y1, Y2, B1 and R1 of the corresponding address are read from the B, CB memory 4C and CR memory 4D, and each memory output is selected by the select signal 1 and the select signal 2 after being latched by DCLK. Furthermore,
The select data is latched by a latch clock obtained by delaying the divide-by-four clock by DCLK, and the timing is matched with a memory card address separately generated by the memory card controller 14, and recording on the memory card is performed. The write enable signal WE to the memory card is generated from the divide-by-4 clock at the timing shown in the figure.

FIG. 6 is a timing chart of the operation of reproducing data from the memory card 9 by the memory controller 14 during the non-compression mode reproduction of FIG. DCL
The outputs of K, CNT1, CNT2, and DCLK divided by 2 and 4 are the same as in FIG. 5, and the divider and the address counter are reset with a delay of 4DCLK from CNT2. As shown in the figure, a memory card address is generated by the memory card controller 14 and the data of the corresponding address is transferred from the memory card 9 to Y1, Y2, B1, R1, Y3, Y.
4, etc. are read out. The read data is DC
The signal is latched by the LK frequency-divided output and supplied to each frame memory. As a result, the CR memory 4 of the frame memory 4
D, CB memory 4C, Y1 memory 4B and Y0 memory 4
Writing to A is performed as a serial / parallel conversion (S / P conversion), and is written as shown in the drawing in accordance with a frame memory address by a write enable signal WE. The timing charts in FIGS. 5 and 6 are shown in pixel units,
This applies regardless of whether the image data is a field or a frame. In the case of frame data, non-interlace and interlace conversion are performed by switching the frame memory for each line during transfer.

FIG. 7 is a diagram showing the configuration of a counter for generating a frame memory address. FIG. 9A shows a counter configuration for storing video rate image data. A 9-bit counter 41 counts DCLK, and A0 to A8.
, And an 8-bit counter 42 counts HD and outputs a vertical address signal consisting of A9 to A16. Fig. (B)
Is a counter configuration for performing color interpolation processing to be described later when data is transferred to the memory card 9 in a recording operation in the non-compression mode. The clock divided by 16 by the counter 43 is counted by the counter 41 having a 9-bit configuration.
When a horizontal read address signal is output to 0 to A8 and the decoder 44 decodes 384, the counter 41 is reset, and the next counter 42 and counter 45 perform a counting operation. The outputs of the counters 42 and 45 are alternately switched by the select signal 2 shown in FIG. 5, and the vertical addresses A9 to A1 for performing the interpolation processing.
6 is generated. When the data to be transferred is frame data, the counter 42 also generates a chip select signal for the frame memory. In this case, the least significant bit is used as the chip select signal, and A9 to A16 are sequentially assigned from the next lower bit. Assign. In the case of field data, A9 to A16 are assigned in order from the lowest. FIG. 7C shows a counter configuration when data is transferred between the frame memory 4 and the memory card 9 when color interpolation is not performed in the reproduction operation and the recording operation in the non-compression mode. Similarly to (B), the clock divided by 16 by the counter 43 is counted by the counter 41 and
When 384 is decoded in step (1), the counter 41 is reset and the output is supplied to the counter 42. The counter 41 generates a horizontal address, and the counter 42 generates a vertical address and a chip select signal of a frame memory.

In the above example, non-compressed transfer control is performed without changing the clock supplied from the frame memory 4 to the card memory controller 14 to that at the time of compression.
A frequency divider is provided in each of the frame memory controller 10 and the memory card controller 14, and the frequency division is performed in synchronization based on a synchronization trigger signal indicating the start of data transfer.

While the embodiment shown in FIG. 1 directly transfers data from the frame memory 4 to the memory card 9, the present invention improves color resolution by performing color interpolation processing. An example will be described with reference to FIG.

Image sensor (complementary color filter type CCD)
When a color difference signal is obtained by calculating a color signal from the CBCR, a CBCR line-sequential output in which CB and CR are alternately output is obtained as shown in FIG. Therefore, the CB signal and the CR signal of each line are delayed by 1H using a line memory or the like, and the CB signal and the CR signal are synchronized as shown in FIG. But,
Since color signals are forcibly assigned to lines that should not exist, color bleeding occurs, and the sense of resolution of colors in the vertical direction decreases.

In this embodiment, for a line having no original color signal, color signals on both sides are used, for example, as shown in (C), (B0 + B1) / 2, (B1 + B2) / 2,
By performing interpolation processing such as (R1 + R2) / 2 and (R2 + R3) / 2, image quality deterioration such as color bleeding is prevented. The configuration of the present embodiment is shown in FIG. 9, and this interpolation processing is performed by the interpolation calculation unit 16 in FIG. In FIG.
Components designated by the same reference numerals as those in FIG. 1 indicate the same components.

In the present embodiment, when the image data read from the frame memory 4 is recorded on the memory card 9 via the selectors 5 and 8, the interpolation operation section 16 performs the interpolation processing of the color signal as described above to write the image data. Put in. The counter configuration for generating the address in the non-compression mode when performing the color interpolation processing is the configuration described with reference to FIG.

FIG. 10 is an operation timing chart of the interpolation processing in the non-compression mode in this embodiment. In synchronization with DCLK as a reference clock of the frame memory, a CNT1 and a CNT2 signal for counter reset and load are generated, and two- and four-divided clocks of DCLK are generated. Two Y signals, R,
Select signal 1 for selecting B signal, Y signal and CR
Alternatively, a select signal 2 for selecting a CB signal is generated, and an address counter carry-in signal and a counter 41 are selected.
In this example, the frame memory addresses in the horizontal direction are generated at timings such as the outputs A0 and A1 shown in FIG. The memory line addresses A9 to A16 in the vertical direction are generated from the counters 42 and 45 as described with reference to FIG. 7B. The counter 42 is reset to 0 by CNT2, whereas the counter 45 is reset. The address value 1 is loaded by CNT2. Therefore, the same address value as that obtained by adding 1 to the address value generated by the counter 42 is generated from the counter 45. by this,
Addresses corresponding to two lines are generated alternately at the timing of the select signal 2. The horizontal and vertical frame memory address signals are latched by DCLK and supplied to each memory. As a result, the Y0 memory 4A, the Y1 memory 4
The data read from the B, CB memory 4C, and CR memory 4D are as shown in the figure. Here, for example, “0” of Y (0, 1) indicates that the vertical line number is “0”, and “1” indicates that the pixel number is “1”.

Next, select signal 1 and select signal 2
The data of the interpolation CB or CR memory is latched by the latch clock of the generated interpolation CB or CR data, and the Y, CR, and CB memory outputs latched by DCLK are selected. At this time, the above-described color signal interpolation processing has been performed. Then, the frequency-divided clock is DCL
The select data is latched by the latch clock delayed by K, and written to the memory card in response to the memory card write enable signal in accordance with the memory card address corresponding to the latch data.

FIG. 11 is a block diagram showing the detailed configuration of the interpolation calculation section 16 of the present embodiment. The CB data and the CR data transferred from the frame memory 4 are latched by the latch circuits 161 and 162 in response to the latch clock. By the selectors 163, 164 and 165, a latch output and an unlatched output are appropriately selected and output. The selectors 164 and 165 control the bit A
9, the switching of the selector 163 is controlled by the inverted output of the bit A9 of the inverter 166. When the A9 output is “L”, the outputs from the selectors 164 and 165 are added by the adder 167, and
The signal is multiplied by で in the multiplier 168 and supplied to the terminal H of the selector 170 as a CB signal. The output of the selector 163 is supplied to the terminal G of the selector 170 as a CR signal. Therefore, when CB is an interpolation signal and CR is a signal not interpolated, and A9 becomes "H" and the line changes,
Control is performed so that R is an interpolation signal and CB is a signal not interpolated. Terminals E and F of the selector 169 are supplied with Y0 data and Y1 data, respectively. As the switching control signal for the selectors 169 and 170, the select signal 1 and the exclusive OR output of the signal of the bit A9 of the counter 43 and the select signal 1 are supplied. Selector 169
And 170 are supplied to the terminals I and J of the selector 172, switched and output by the select signal 2, latched by the latch 173, and then output as card input data. In the above-described example, the color difference signal is interpolated and recorded during non-compression transfer from the frame memory 10 to the memory card 9.

FIG. 12 shows a configuration example of an image file in a memory card for explaining still another example related to the present invention. Normally, image data is located following the header portion, and a start address and an end address as shown are present. A start address, a data capacity, and the like are written in the header, and the CPU performs efficient file management by reading the header. Normally, file management is performed by MSDOS. In this case, files are managed by a connection of clusters that are not always continuous. However, image files are conventionally stored in a memory card due to ease of processing. If the file exists on a discontinuous address, the image cannot be reproduced and displayed.

However, since such a management system is adopted in consideration of compatibility with a personal computer, inconvenience is likely to occur if a discontinuous file which is easily created by a file managed on the personal computer cannot be reproduced. In this example,
In order to solve this problem, as shown in FIG.
The start address and the end address of the discontinuous image data as shown by the shaded portion are obtained from the reading of the header and the search of the FAT, and the transfer is performed based on the start and end addresses.

FIG. 14 is a block diagram showing the basic configuration of this embodiment, and the system configuration is the same as that of the DCT shown in FIG.
The section 6 and the compression / expansion section 7 are omitted. FIG.
Shows an operation timing chart of the example shown in FIG. In FIG. 15, the CPU 107 performs processing of reading the root directory, searching for the FAT, reading the header, and setting the start / end addresses, and thereafter sequentially sets the start / end addresses. CP
U107 sets the CN after setting the start / end address.
The T1 signal is supplied to the frame memory controller 105 and the card controller 110, and the frame memory controller 105
Supplies the card control unit 110 with a CNT2 signal in response to the CNT1 signal. The comparator 109 sends the CNT3 signal to the CPU 107 when the address from the card address counter 108 is equal to or more than the set address from the start / end address setting unit 106, and sends the CNT4 signal as an enable signal to the frame memory address counter 104. Send out.

Now, the recorded image signal is converted by the A / D converter 10
After being converted into a digital signal in the frame memory 10, the frame memory 10
Written in 3. Writing and reading of the frame memory 103 are controlled by an address signal from a frame memory address counter 104 and a control signal from a frame memory controller 105. The image data read from the frame memory 103 is written to the memory card 111 via the bus under the control of the CPU 107. Writing / reading control to / from the memory card 111 is performed by a card address counter 108 and a card control unit 110. At the time of reproduction, the image data read from the memory card 111 is written into the frame memory 103, and is converted into an analog signal by the image data D / A converter 102 read from the frame memory 103 to obtain a reproduced image output.

The CPU 107 controls the start / end address setting unit 106 to supply the start / end address to the card address counter 108 and the comparator 109. The comparator 109 supplies an enable signal to the card address counter 108 and the card control unit 110. The card control unit 110 sends the clock and the CNT2 signal from the frame memory control unit 105 to the CPU 107.
Receives the CNT1 signal. The CPU 107 sends CNT1 to the frame memory control unit 105 and the card control unit 110.
The signal is supplied to the comparator 109 as a CNT3 signal.

In the above example, when the data files in the memory card 111 are managed in the DOS format,
When clusters are scattered and managed by the FAT, a process of setting the file state by the CPU 107, transferring the data to the frame memory 103, and collecting the image data into one unit on the frame memory 103 can be performed. it can.

[0033]

As described above, according to the present invention,
To control the operation timing of the information recording medium control means
The clock to be supplied to the
Without changing, it is possible to supply a control signal suitable for each signal data arrangement at the time of compression and non-compression of image data to the information recording medium control means, so that user-friendly recording control can be performed. Further, the image quality can be selected according to the user's request, and the deterioration of the image quality due to the compression processing of the image data can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an image handling apparatus according to the present invention.

FIG. 2 is a diagram showing states of data transfer in a compression mode and a non-compression mode.

3 is a configuration block diagram of a recording system of a Y signal and a color signal to a frame memory 4 under the control of a memory controller 10 in FIG.

FIG. 4 is a diagram showing a memory map when writing image data to a frame memory 4;

FIG. 5 is a timing chart of a recording process in the non-compression mode in the example of FIG.

FIG. 6 is a timing chart of the operation of reproducing data from the memory card 9 by the memory controller 14 during non-compression mode reproduction in the example of FIG.

FIG. 7 is a configuration diagram of a counter for generating a memory address.

FIG. 8 is a diagram for explaining an embodiment of the present invention.

FIG. 9 is a configuration diagram of the embodiment shown in FIG. 8;

FIG. 10 is an operation timing chart of an interpolation process in a non-compression mode in the embodiment.

FIG. 11 is a detailed configuration block diagram of an interpolation calculation unit 16 in the present embodiment.

FIG. 12 is a diagram for explaining still another example related to the present invention.

FIG. 13 is a diagram for explaining the example shown in FIG. 12;

FIG. 14 is a basic configuration block diagram of the example shown in FIG. 12;

15 is an operation timing chart of the example shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CCD 2 Imaging process part 3, 101 A / D converter 4, 103 Frame memory 5, 8, 13 Selector 6 DCT part 7 Compression / decompression part 9, 111 Memory card 10, 105 Frame memory controller 11, 107 CPU 12 Mode setting part 14, 110 Memory card controller 15, 102 D / A converter 16 Interpolation calculation unit 41, 42, 43 Counter 44 Decoder 104 Frame memory address counter 106 Start / end address setting unit 108 Card address counter 109 Comparator

Claims (2)

(57) [Claims] A memory capable of temporarily storing the generated or supplied image data; a memory control means for controlling writing and reading of image data to and from the memory ; Data compression transfer means for performing processing using DCT transformation and compression processing on the image data read as block data and supplying it to the applied information recording medium; and color information interpolation processing is performed from the memory. Data uncompressed transfer means for supplying image data read as image data to the applied information recording medium without passing through the image data compression means; and transferring the image data to the applied information recording medium. When controlling writing and supplying image data to the information recording medium applied by the data uncompressed transfer means, Information recording medium control means adapted to control writing of image data transmitted as image data subjected to color interpolation processing to an information recording medium to which is applied, and information applied by the data compression transfer means When supplying image data to a recording medium, a control signal relating to the compression processing is supplied to the information recording medium control means, and the image data is supplied to the information recording medium applied by the data non-compression transfer means. In the case, the above information recording medium system
The clock supplied to control the operation timing of the control means
The data applied by the data compression transfer means.
The same condition as when supplying image data to the information recording medium
In state, a digital still camera, characterized in that it and a switching means for switching a control signal to be supplied to the information recording medium control unit a control signal synchronized with the control signal of the memory by the memory control means. 2. The data compression / transfer means or data non-compression
Further provided is a mode setting means for selectively applying the compression transfer means.
The digital still according to claim 1, wherein
camera.