JP2573700B2 - Image recording and playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image recording and decoding apparatus for compressing and encoding digital image data and writing and recording the same in a semiconductor memory, or expanding and decoding image data read from the semiconductor memory and reproducing the same. The present invention relates to a reproducing apparatus, for example, an image recording and reproducing apparatus suitable for a digital electronic still camera.

BACKGROUND ART A digital electronic still camera is known as an image recording and reproducing apparatus of this kind. This digital electronic still camera captures an image of an object scene with a solid-state imaging device and records the image signal by storing the image signal in a semiconductor memory, or reads out image data stored in the semiconductor memory and reads the image signal. It reproduces a world image.

Semiconductor memories used in such image recording and reproducing devices take the form of memory cards. The storage area of the memory card is divided into a plurality of storage units (clusters) having a predetermined storage capacity so as to efficiently store images of a plurality of image sizes. For example, when recording a single image, image data is sequentially written in a plurality of unrecorded continuous numbers or in a plurality of clusters of discontinuous numbers (clusters are numbered consecutively). It is. In this case, the CPU constituting the control unit of the image recording apparatus
Specifies the start address of the first cluster in which the image data is written. Thereafter, the address is automatically incremented by an address register built in the memory card until the writing of the image data of the storage capacity for one class is completed, and the image data is sequentially written. Therefore, when the writing of the image data of one cluster is completed, the CPU
Has to calculate the start address of the cluster where the image data is to be written next, and output the start address to the address register of the memory card. The same applies to an image reproducing apparatus for reading and reproducing an image recorded on a memory card.

However, when the image data is written to a plurality of clusters of the memory card or the image data written to the plurality of clusters is read in this manner, the writing operation or the reading operation of the image data from one cluster to the next cluster is performed. There is a problem that it takes time for the CPU to calculate the start address of the next cluster in order to perform the shift, that is, to switch the cluster, and to output it to the memory card.

In addition, the CPU must wait for the cluster switching request signal to be output on the control bus when performing the address calculation when performing the above-described cluster switching, and may perform other processing within the waiting time. There was a problem that it was difficult.

An object of the present invention is to solve such a problem of the related art, and to write image data in a semiconductor memory such as a memory card.
Another object of the present invention is to provide an image recording / reproducing apparatus which improves the processing speed at the time of cluster switching when image data is read from the semiconductor memory.

DISCLOSURE OF THE INVENTION According to the present invention, an area for storing information of a first storage unit in which image data is encoded and stored is divided into a plurality of storage units having a predetermined storage capacity, and a first storage unit is provided. An image recording apparatus configured to write image data for each storage unit in the means; an encoding means for compressing and encoding the image data and outputting the compressed and encoded image data to the first storage means;
A second storage unit in which address data specifying an unrecorded storage unit in the storage unit is stored in a predetermined order;
Prior to writing of image data, control means for previously searching for unrecorded storage units in the first storage means and storing address data for specifying a required number of storage units in the second storage means; The data amount of the image data encoded by the means is counted, and when the data amount reaches one storage unit of the first storage means, the storage area is set to the next storage unit to be written in the first storage means. A data amount for outputting a switching request signal for instructing to switch over and writing the encoded image data, and outputting a control signal for stopping the output operation of the encoding unit to the encoding unit Counting means, and receiving, from the second storage means, address data of a storage unit to which encoded image data is to be written next in response to the switching request signal output from the data amount counting means; Address generating means for generating a real address on the basis of the address data of the first address, and outputting the generated real address to the first storage means; an output signal of one of the address generating means and the data amount counting means; Switching means for selectively outputting one of the two to the first storage means, and the control means stores address data indicating the required number of storage units in the second storage means, The address data specifying the storage unit in which the image data is to be written first among these storage units is output to the address generation means.

Further, according to the present invention, an area for storing information of the first storage unit in which the image data is encoded and stored is divided into a plurality of storage units having a predetermined storage capacity, and is stored in the first storage unit. An image reproducing apparatus configured to read image data for each unit includes a decoding unit that expands and decodes the compressed / encoded image data read from the first storage unit; A second storage unit in which address data for specifying a storage unit in which image data has been recorded in the storage unit is stored in a predetermined order; and a recorded storage unit in the first storage unit prior to reading of the image data. And control means for storing in a second storage means address data specifying the number of storage units required to reproduce a desired image, and image data decompressed and decoded by a decoding means. When counting the amount of data, the data amount reaches the first storage unit of the first storage means, second
A switching request signal for instructing to switch the storage area to a storage unit to be read next in the first storage means stored in the first storage means and to read the encoded image data, and A data amount counting means for outputting a control signal for stopping the output operation of the decoding means; and a storage unit storing image data to be read next in response to a switching request signal output from the data amount counting means. Address generating means for generating an address and outputting the generated address to the first storage means, and an output signal of the control means or the address generation means being output to the first storage means or image data read from the first storage means Switching means for selectively switching each of these signals or data so as to be input to the decoding means, and the control means specially stores the required number of storage units. The address data after storing in the second storage means, and outputs the address generator an address data identifying the first image data storage unit to be read out of each of these storage units.

DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a main part of an embodiment of an image recording / reproducing apparatus to which the present invention is applied. Referring to FIG. 1, an image recording / reproducing apparatus to which the present invention is applied includes, for example, an orthogonal transform / inverse orthogonal transform unit 10 which converts an image signal (image data) obtained by imaging an object scene with an imaging device in the form of digital data. , Compressed / encoded by the encoding / decoding unit 12 and recorded on the memory card 18, or
This is a device that reads out compressed / encoded image data from 18 and decompresses and decodes it by an encoding / decoding unit 12 and an orthogonal transformation / inverse orthogonal transformation unit 10 and outputs it as a digital image signal to the outside.

The orthogonal transform / inverse orthogonal transform unit 10 is a circuit that orthogonally transforms time-domain image data into frequency-domain image data or orthogonally inverse-transforms frequency-domain image data into time-domain image data. In the present embodiment, the orthogonal transform / inverse orthogonal transform unit 10 divides a screen represented by image data into sections of a predetermined size, and performs orthogonal transform or orthogonal inverse transform on the image data for each section.

For the orthogonal transform, for example, a technique such as Hadamard transform, Fourier transform, or two-dimensional discrete cosine transform is applied, and for the inverse orthogonal transform, the inverse transform of each of the above techniques is applied.

The orthogonally transformed image data is output to the encoding / decoding unit 12 via the signal line 100 at a predetermined transfer rate, and is compressed and encoded. In addition, the compression read from the memory card 18
The encoded image data is decompressed and decoded by the encoding / decoding unit 12.

Image data output from the encoding / decoding unit 12 is sent to the memory card 18 via the selectors 14 and 16.

In this embodiment, the selector 14 has two switches that are linked to each other.
It consists of 141 and 142. Switches 141, 142 contact a,
d is the output of address generator 24 and address line 1
03, connected via control line 104. Also switch 1
The contacts b and e of 41 and 142 are connected to the encoding / decoding unit 12 via a signal line 101 and a control line 102, respectively.

The selector 16 includes two switches 161 and 162 which are linked in the present embodiment, like the selector 14. The contact a of the switch 161 is connected to the CPU 20, MAT-R via the data bus 109.
AM22 and address generator 24 are connected. Switch 16
The contacts b and e of 1,162 are connected to the contacts c and f of the switches 141 and 142, respectively.

The contact d of the switch 162 is connected to the CPU 20 via the control line 110. Further, the contacts c and f of the switches 161 and 162 are connected to the memory card 18 via a signal line 107, a control line 108, a connector (not shown), and the like.

The selector 14 is connected to a control line by a data counter 26 described later.
Switches 141 and 142 are provided by a switching signal output through 114.
Are the address generator 24 or the encoder / decoder.
It can be switched to any one of 12.

The selector 16 is switched to the contacts c and f of the CPU 20 or the selector 14 by a control signal output from the CPU 20 via the control line 111.

Semiconductor switches are used as the switches 141, 142, 161, 162 constituting the selectors 14, 16, for example. However, the present invention is not limited to this, and other switch means may be used. Selector 1
The components 4 and 16 only need to have the function of switching the connection between the functional units described above, and are not limited to the configuration shown in this embodiment.

The memory card 18 is a temporary storage device in which a rewritable semiconductor memory is carried on a card-shaped carrier, and is detachably connected to the apparatus via a connector or the like (not shown) in this embodiment. As shown in FIG. 5, the storage area 70 of the memory card 18 is divided into a plurality of clusters 72 having a predetermined storage capacity and formatted in this embodiment. The cluster 72, which is a storage unit of the storage area 70, may be, for example, 1 / natural number of the image signal data of one frame. Therefore, one frame of image data is written over a plurality of clusters 72. In this case, a plurality of clusters in which an image of one frame is stored,
If the required number of clusters to which no image data has been written continues, the data is written continuously to those clusters. If not, the data is written discontinuously to the unrecorded clusters, that is, the cluster numbers are not continuous. Is written to the unrecorded cluster. The same applies when reading image data.

In this embodiment, the cluster 72 has a storage capacity of, for example, 8 Kbytes. The relative address of each storage area in each cluster 72 is specified by, for example, 13 bits, as will be described later, and when expressed in decimal notation as shown in FIG.
91 is given. (In FIG. 6, the cluster with the cluster number N is shown.) The storage area of the memory card 18 other than the area where the image data is recorded includes a header, a packet attribute, a directory, and a MAT (memory allocation table). A management area is provided. For these management areas, for example, storage areas having a storage capacity of two clusters are allocated. Here, data such as the number of used clusters and the number of unused clusters are stored in the header area, and a table indicating whether each packet is used or unused is stored in the packet attribute area. Here, the packet is one of an aggregate of a series of clusters in which image data forming one image is stored.
A unit is designated.

As shown in FIG. 7, the MAT area of the memory card 18 has a continuous cluster number (# 1,2... N,...). A cluster number to be read or written is stored. For example, in the example shown in FIG. 7, the CPU 20 refers to the MAT so that the cluster number is 1 → 3 → N → N + i → N + j
It is recognized that image recording or reproduction is performed by writing or reading image data in this order.

Further, data having a value that is not normally possible in a storage area corresponding to a cluster number indicating the last cluster in a chain of clusters in which image data forming one image (for example, an image generated from one frame of image data) is stored. For example, data in which all eight bits are "1" (11111111) is stored, and data in which all eight bits are "0" (00000000) is stored in a storage area corresponding to a cluster number indicating an unused cluster.

As shown in FIG. 8, the directory area of the memory card 18 is the cluster of the cluster which is first written or read in the storage area corresponding to the packet number Px (x = 0, 1, 2,... I, i + 1,. Data indicating the cluster number and the type of data (for example, the type of image data or audio data) is stored.

In the packet attribute area, as shown in FIG. 9, the packet is recorded in a storage area corresponding to the packet number Px (x = 0, 1, 2,... I, i + 1,. Data indicating whether there is any data is stored (in this embodiment, for easy understanding, 示 す indicates data indicating an unused state, and x indicates data indicating a used state).

The CPU 20 writes the unrecorded cluster 72 when writing the image data to the memory card 18 and the recorded cluster where the desired image data that has already been written is read from the memory card 18. Before the write operation or the read operation, respectively.
And searches for the cluster number of the corresponding cluster in the MAT-RAM 22 storing the MAT.

Further, the CPU 20 controls the image data conversion operation in the orthogonal transformation / inverse orthogonal transformation unit 10 and the compression / decompression operation of the image data in the encoding / decoding unit 12, and controls switching of the selector 16.

Under the control of the CPU 20, the MAT-RAM 22 sequentially stores the cluster numbers (No) of the clusters 72 to be written or read from the memory card 18 as shown in FIG.

The address generator 24 is connected to the MAT-RAM 2 via the data bus 109.
Based on the cluster number read from 2, a real address of the cluster corresponding to the cluster number is generated and output to the address line 103. That is, the real address 80 generated by the address generator 24 as shown in FIG.
Address data indicating the cluster number read from 22
80A and a relative address 80B of the cluster 72. This real address is assigned, for example, 24 bits, of which the upper 11 bits are the cluster number and the lower 13
Relative addresses are specified by bits.

In the present embodiment, the memory card 18 employs a so-called I / O bus system in which data and addresses are transmitted on the same bus. The address or data to the memory card 18 is transmitted from the address generator 24 to the address line 103 and the signal line 105.
And from the CPU 20 via a data bus 109.

The address generator 24 sends a control signal for controlling data read timing and the like to the MAT-RAM 22 via the control line 113. The address generator 24 outputs various control signals related to writing and reading of data to and from the memory card 18 via the control line 104.

The data counter 26 is a counter for counting the amount of image data encoded or decoded by the encoding / decoding unit 12. Each time the data counter 26 counts the amount of data for one cluster, the control signal for stopping the input / output operation of the encoding / decoding unit 12 via the control line 116.
Make ▼ significant. Further, the data counter 26
A cluster switching request signal for shifting the write operation or the read operation to the next cluster is output to address generator 24 via control line 115. The data counter 26 outputs a control signal (switching signal) for switching the selector 14 to the selector 14 via the control line 114 at the time of cluster switching.

The counting of the data amount by the data counter 26 is actually performed by counting the number of output times of the read signal or the write signal output from the encoding / decoding unit 12 to the memory card 18. This is because a read signal or a write signal is output every time data or an address is output on a signal line in units of 1 byte. Therefore, counting the number of times these signals are output is equivalent to counting the amount of data. It is.

Next, the operation of the image recording / reproducing apparatus according to the present invention shown in FIG. 1 will be described with reference to the flowcharts of FIGS. 2A and 2B and the timing chart of FIG.
First, a switching signal is output from the CPU 20 to the selector 16 via the control line 111, and the selector 16 is in the state shown in FIG.
(0 side) (step 201).

Next, a switching signal is output from the data counter 26 to the selector 14 via the control line 114, and the selector switches to the state shown in FIG. 1 (to the address generator 24 side) (step 202). Further, the CPU 20 refers to the management area of the memory card 18 to search for unrecorded clusters to which image data is to be written or recorded clusters to be read out of image data, and stores data indicating the cluster number of the required number of clusters in MA.
While storing in the T-RAM 22, the cluster number of the first cluster of the packet to be written or read is written in the RAM area in the CPU 20 (steps 203 and 204). Here, the required number of clusters means, for example, when writing image data, the number of clusters according to the image quality mode.

After the cluster number is stored in the MAT-RAM 22, a switching signal is output from the CPU 20 to the selector 16 via the control line 111. As a result, the switches 161 and 162 constituting the selector 16 are switched to the contacts b and e, that is, to the selector 14 (step 205).

Next, the CPU 20 outputs data indicating the cluster number of the first cluster of the packet to be written or read in the memory card 18 to the address generator 24 via the data bus 109. The address generator 24 generates a real address of the corresponding cluster from the address data indicating the cluster number and the start address (relative address) of the cluster, and generates an address line 103 selector 14, a signal line 105, a selector 16, and a signal line 107.
The address is output to the memory card 18 via an address register, and this address is set in an address register in the memory card 18 (step 206).

Next, the selector 14 is switched to the contacts b and e, that is, to the encoding / decoding unit 12 by the switching signal output from the data counter 26 (step 207).

Further, the encoding / decoding unit 12 receives the orthogonally transformed image data from the orthogonal transformation / inverse orthogonal transformation unit 10 when writing image data to the memory card 18, for example.
The compression / encoding of the image data is performed under the control of (step 208). Here, when reading image data from the memory card 18, the encoding / decoding unit 12 decompresses and decodes the image data read from the memory card 18,
In the orthogonal inverse transform unit 10, the orthogonal inverse transform of the decompressed and decoded image data is performed.

The image data compressed / encoded by the encoding / decoding unit 12 is sent to the memory card 18 via the selectors 14 and 16.
Since the top address (real address) of the cluster to be written first in step 206 has already been set in the address register in the memory card 18,
Each time the compressed and encoded image data is input, the above-mentioned start address is incremented by an address register provided in the memory card 18, and the image data is sequentially written. The designation of the cluster address when the image data is read from the memory card 18 is similarly performed.

On the other hand, the data counter 26 counts the number of times a write signal or a read signal (FIG. 3 (a)) output from the control line 102 of the encoding / decoding unit 12 is output. It is calculated (step 209). Data counter 2
If the data amount calculated in 6 has not reached one cluster, the process returns to step 208, and the processing described above is performed (step 210).

When the data amount calculated by the data counter 26 reaches one cluster, that is, when writing or reading of image data for one cluster is completed, the data counter 26 performs encoding / decoding via the control line 116. As shown in FIG. 3D, the time of the signal ▼ is made significant at t0 for the unit 12 (step 211). Further, the data counter 26 outputs a switching signal to the selector 14 via the control line 114, and the selector 14 is switched to the contacts a and d. At the same time, a cluster switching request signal is output to the address generator 24 via the control line 115 at time t1, as shown in FIG. 3 (c) (step 212).

In the address generator 24, the MAT-RAM 22
Then, a control signal for reading data indicating a cluster number of a cluster in which writing or reading of image data is to be performed next is output. As a result, a predetermined cluster number from the MAT-RAM 22, for example, the cluster number of the first written or read cluster is set to N as shown in FIG.
If it is o.1, No. 3 is read as the cluster number.
The address generator 24 generates the start address (real address) of the No. 3 cluster, outputs the start address to the memory card 18 via the selectors 14 and 16, and sets the address in the address register in the memory card 18. (Step 21
3). FIG. 3B shows that the image data D (1) to be written to or read from the No. 1 cluster is output on the signal line 107, and then the 24-bit head address A of the No. 3 cluster is output. After (0-7) 3, A (8-15) 3, A (16-23) 3 are output, the image data D (3) to be written or read to the No.3 cluster is output. The state is shown. In the figure, the head address of the image data or the cluster is output on the signal line 107 in units of 1 byte.

Now, after the start address of the next cluster is output from the address generator 24 to the memory card 18, the data counter
26 is reset, and the data counter 26
The control signal ▲ ▼ output to 12 is rendered insignificant at time t2 (steps 214 and 215). Next, it is determined whether the writing or reading of the image data in the last cluster is completed. When the writing or reading of the image data up to the last cluster is completed, this processing sequence is terminated as it is, otherwise, the process returns to step 208 (step 2).
twenty two). Here, steps 201 to 206 are executed by the CPU 20.
Are involved in this processing sequence, but step 207
Since the processing sequence of steps 216 and 222 involves functional units (hardware) other than the CPU 20, the CPU 20 performs other tasks including the processing of steps 217 to 221.

When one packet of image data compression / encoding or decompression / decoding processing performed by the encoding / decoding unit 12 under the control of the CPU 20 is completed, the encoding / decoding unit 12 outputs An end signal indicating that the compression (decompression) processing has ended is output to the data counter 26 (step 21).
6).

Next, the CPU 20 reads the stored contents from the MAT-RAM 22, and switches the selector 16 to the contacts a and d (the CPU 20 side) (steps 217 and 218). Further, since the recording state of each cluster of the memory card 18 changes, the CPU 20 manages the management area of the memory card 18,
The T area, packet management area (packet attribute area and directory area), and header area are rewritten, and this processing sequence ends (steps 219, 220, and 22).
1).

When the image data is read from the memory card 18, the processing of steps 217 to 221 is not performed because the recording state of the image data in each cluster of the memory card 18 does not change.

In the above embodiment, writing or reading of image data in the memory card 18 is performed in units of one screen. However, when image data of a plurality of screens is continuously recorded in the memory card 18, Is performed as follows. That is, empty areas (clusters) in the memory card 18 for the number of screens to be continuously recorded in advance are searched, and those cluster numbers are collectively stored in the MAT-RAM 22. Next, the processing sequence described above is applied to one screen (one packet),
After the end, the cluster number of the first cluster constituting the next screen is output to the address generator 24, and the above-described image data for one screen is written. In this case, the cluster number of the first cluster on each screen is RAMA of CPU20.
The area may be written in advance and given to the address generator 24, but the MAT may be used without using the RAM area of the CPU 20.
-It may be provided from the RAM 22.

When image data for a plurality of screens is continuously read, addressing of each cluster is performed in exactly the same manner as in the case of the write operation.

Although the present embodiment employs the I / O bus system, the present invention is not limited to this, and a direct bus system in which data and addresses are transferred using separate buses may be employed. When the direct bus system is adopted, an address counter may be added in the memory card 18 in addition to the configuration shown in FIG.

In the present embodiment, it is assumed that the image data to be written to the memory card 18 is compressed / encoded. However, the image recording / reproducing apparatus according to the present invention records the uncompressed / encoded image data. But it is possible to apply.

As described above, according to this embodiment, the cluster switching process at the time of writing or reading image data is configured to be performed by hardware other than the CPU.
During the compression (expansion) processing of the image data, other work can be performed and the processing speed of the CPU can be improved.

Further, by providing the MAT-RAM, it is not necessary to use the RAM area of the CPU for temporarily storing the cluster number.

Further, when recording image data on the memory card, the image data, the MAT area, the packet management area, and the header are written in this order in the memory card. Even if an accident occurs, it is unlikely that incomplete images will be recorded.

As described above, according to the present invention, the CPU serving as the control unit searches in advance for a storage unit (cluster) of a storage area of a storage unit such as a memory card in which image data is to be written or read, and
The cluster number is stored in another storage means, and subsequent cluster switching processing is performed by hardware. Therefore, according to the present invention, cluster switching processing can be performed at high speed. Further, the CPU can perform other tasks while the compression / expansion processing of the image data is being performed by the encoding / decoding unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an image recording / reproducing apparatus to which the present invention is applied. FIGS. 2A and 2B show the contents of a processing sequence of the image recording / reproducing apparatus to which the present invention is applied. Flowchart, FIG. 3 is a timing chart showing an operation state of the image recording / reproducing apparatus to which the present invention is applied, and FIG. 4 is a real address of a cluster generated by an address generator of the image recording / reproducing apparatus to which the present invention is applied. FIG. 5 is an explanatory view conceptually showing a storage area of a memory card of an image recording / reproducing apparatus to which the present invention is applied, and FIG. 6 is a view showing a storage area for one cluster in FIG. 7 to 9 are explanatory diagrams showing the storage contents of a management area of the image recording / reproducing apparatus to which the present invention is applied, and FIG. 10 is an image recording / reproducing apparatus to which the present invention is applied. MAT-R
FIG. 4 is an explanatory diagram showing stored contents of AM. Explanation of codes of main parts 10: orthogonal transform / inverse orthogonal transform unit 12: encoding / decoding unit 14, 16, selector 18: memory card 20, CPU 22, MAT-RAM 24, address generator 26, data counter

Claims (4)

(57) [Claims] 1. A first method in which image data is encoded and stored.
An image recording apparatus, wherein an area for storing information of the storage unit is divided into a plurality of storage units having a predetermined storage capacity, and image data is written to the first storage unit for each storage unit. An encoding unit for compressing and encoding the image data and outputting the compressed and encoded image data to the first storage unit; and address data for specifying an unrecorded storage unit in the first storage unit in a predetermined order. And a second storage unit stored in the first storage unit, before writing the image data, previously searching for an unrecorded storage unit in the first storage unit and storing address data for specifying a required number of each storage unit in the second storage unit. A control unit that stores the image data in the storage unit, and a data amount of the image data encoded by the encoding unit is counted, and when the data amount reaches one storage unit of the first storage unit, A switch request signal for instructing to switch the storage area to a storage unit to be written next in the first storage unit and to write the encoded image data is output, and to the encoding unit, Data amount counting means for outputting a control signal for stopping the output operation of the storage unit; and an address of the storage unit to which encoded image data is to be written next in response to a switching request signal output from the data amount counting means. Reading data from the second storage means, generating a real address based on the address data,
Address generating means for outputting to the first storage means; and selectively outputting one of an output signal of the address generating means and the data amount counting means and an output signal of the control means. Switching means for outputting to the first storage means, the control means stores address data indicating the required number of storage units in the second storage means, An image recording apparatus for outputting address data specifying a storage unit to which image data is to be written to an address generating means. 2. The image recording apparatus according to claim 1, wherein
A first signal selector for selectively outputting one of the output signals of the address generator and the encoder; an output signal of the first signal selector and the controller; And a second signal selecting means for selectively outputting either one of the second signal selecting means and the second signal selecting means when searching for an unrecorded storage unit in the first storage means. The means is switched to the control means, and the input of the second signal selection means is switched to the first signal selection means after the address data specifying the required number of storage units is stored in the second storage means. The second signal selection means is switch-controlled, and the data amount counting means receives an input of the first signal selection means, and the control means issues an address data which specifies the storage unit in which the image data is to be written first. Switching to the address generating means before outputting to the generating means, and switching to the encoding means when the control means outputs the address data, and switching to the encoding means when the encoding amount of the image data reaches one storage unit. An image recording apparatus, comprising: switching control of a first signal selection unit so as to switch to an address generation unit. 3. A first method in which image data is encoded and stored.
An image storage device configured to divide an area for storing information of the storage unit into a plurality of storage units having a predetermined storage capacity, and to read out image data for each storage unit in the first storage unit In the apparatus, a decoding unit that expands and decodes the compressed / encoded image data read from the first storage unit, and a storage unit in the first storage unit where the image data is recorded A second storage unit in which address data to be specified is stored in a predetermined order; and prior to reading out the image data, a previously stored storage unit in the first storage unit is searched in advance to reproduce a desired image. Control means for storing, in the second storage means, address data specifying the number of storage units required for the processing, counting the amount of image data decompressed and decoded by the decoding means; Of the first storage means
When the number of storage units has been reached, an instruction is issued to switch the storage area to the next storage unit to be read out of the first storage means stored in the second storage means and to read the encoded image data. Data counting means for outputting a switching request signal for performing the switching operation and outputting a control signal for stopping the output operation of the decoding means, and receiving and subsequently reading the switching request signal output from the data amount counting means Address generating means for generating a real address of the storage unit in which image data to be stored is stored and outputting the generated real address to the first storage means; and an output signal of the control means or the address generation means being transmitted to the first storage means. These signals or data are selectively switched so that the image data output or read from the first storage means is input to the decoding means. The control unit stores the address data specifying the required number of each storage unit in the second storage unit, and then the image data should be read first among these storage units. An image reproducing apparatus for outputting address data specifying a storage unit to an address generating means. 4. The image reproducing apparatus according to claim 3, wherein
The switching unit outputs an output signal of the address generation unit to the first storage unit, or selects a signal path so that image data read from the first storage unit is input to the decoding unit. First signal selecting means for selectively switching, and outputting an output signal of the control means to the first storage means, or transferring image data read from the first storage means to the first signal switching means. Second signal selecting means for selectively switching a signal path so as to output the signal path, wherein the control means selects the second signal when searching for the recorded storage unit in the first storage means. The second means is switched to the first signal selecting means after the means is switched to the control means and the address data specifying the required number of each storage unit is stored in the second memory means. 2 signal selection Switching the stages, the data amount counting unit switches to the address generation unit before the control unit outputs address data specifying the storage unit from which the image data is to be read first to the address generation unit, and controls The first signal selecting means is switched so that the means is switched to the decoding means when the means outputs the address data, and is switched to the address generating means when the decoding amount of the image data reaches one storage unit. An image reproducing apparatus characterized by controlling.