JPH0732481B2 - Teletext receiver circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a teletext receiving circuit, and more particularly, to time division in a vertical blanking period of a video signal received from a multiplexed television signal of a coded transmission system. The present invention relates to a teletext receiving circuit configured to display teletext contents on a display unit by extracting multiplexed teletext signals and performing serial / parallel conversion processing, error correction processing, decoding processing, display processing, and the like. .

<Technical Background and Prior Art> In a character broadcasting system based on a coded transmission method that codes and transmits characters and figures, which have recently been put into practical use, the character broadcasting signal is a vertical line of a television video signal. Time-division multiplexing is performed in the form of digital data in a data packet format having a unit length of data superimposed in the 1-horizontal scanning period using the blanking period. In other words, the signal for one teletext program is 1
-One packet at a time during the vertical blanking period is almost continuously superimposed on the vertical blanking period. Therefore, it is necessary to capture all the teletext signals superimposed in the 1-vertical blanking period before the teletext signals superimposed in the next vertical blanking period arrive.

On the other hand, as shown in FIG. 5, in the future, a maximum of 12 programs (12 packets of 10H to 21H) can be superimposed on the teletext signal during the 1-vertical blanking period.

In addition, in FIG. 5, only 16H is described as the multiple teletext signal, but as described above, 10H to 21H
Is a period in which multiplexing is possible, and the multiple teletext signal may be multiplexed in a plurality of periods.

By the way, when a data memory capable of storing data of a plurality of teletext programs is not provided like the conventional teletext receiving circuit, only the program selected by the receiver needs to be fetched. There was no problem because there was no problem in time because there was no problem as long as one data packet could be fetched during the blanking period, but a data memory capable of storing the data of a plurality of teletext programs was provided, and the data memory When storing and accumulating the latest data in, especially when a large number of data packets are superposed in the 1-vertical blanking period, the processing of fetching the large number of data packets is performed in the next vertical blanking period. Must be completed before the arrival of the data packet superimposed on
CPU acquisition processing time becomes a big problem.

That is, in the teletext receiving circuit of the conventional configuration by a simple means of sequentially fetching the data in the order in which they are transmitted by using one buffer RAM which has only the capacity of 1-vertical blanking period data, FIG. As shown in the figure, error correction processing is performed while performing operations such as primary capture processing of superimposed data within the 1-V period, data transfer to buffer RAM after error correction processing, error check, confirmation of reservation status and selected program. CPU processing to store the data in the later buffer RAM in the data memory must be performed. Ie buffer RAM
Is 1-the amount of data for the vertical blanking period, the data required for processing the previous data before the arrival of data for the next vertical blanking period is a large amount of data. Must be stored in memory.

Note that FIG. 6 shows the CPU based on the V-sync signal generated on the receiver side based on the equivalent pulse shown in FIG.
This shows the processing of. Further, the error correction unit improves the correction capability by performing the error correction processing a plurality of times, but the error correction processing time increases if the error correction processing is performed a plurality of times. Moreover, if the number of superposed H of data packets is large, the error correction processing time is correspondingly increased. Therefore, the worse the reception state is, and the larger the number of overlapping H of data packets is, the longer the error correction processing time is, and the shorter the time t at which the CPU can take in the processing is. In addition, the fetch processing time of the CPU becomes longer as the number of superposed H of data packets increases, so that there is a limit to the number of superposed H of data packets that can be simultaneously taken.

<Objects of the Invention> The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to store data of a plurality of teletext programs so that a plurality of teletext programs can be stored and accumulated. While providing a large-capacity data memory that can be used to store the latest data in the data memory, and while ensuring sufficient error correction processing time,
The purpose is to provide a teletext receiving circuit of a coded transmission method that does not cause a problem in the CPU processing time.

<Structure of the Invention> In order to achieve such an object, the teletext receiving circuit according to the present invention has a basic construction as described at the beginning, and is capable of storing data of a plurality of teletext programs. In addition to providing a large-capacity data memory, in order to store the latest data in the data memory, the data output from the error correction unit is stored in a plurality of buffer memories by time division in units of 1-vertical blanking period. By so doing, the CPU is configured so as to be able to increase the CPU uptake processing time while ensuring a sufficient error correction processing time.

<Example> Hereinafter, a specific example of the present invention will be described with reference to the drawings (Figs. 1 to 4).

FIG. 1 is a schematic block circuit configuration diagram of a main part of a teletext receiving circuit according to the present embodiment. In the figure, 1 is an antenna, 2 is a teletext signal sampling unit, 3 is serial-parallel conversion and error correction unit, 4 is a buffer memory having a plurality of buffer RAMs, 5 is a CPU, 6 is a large-capacity data memory for storing data of a plurality of teletext programs, 7 is a decoding and display processing unit, 8 is a CRT or Shows a display such as a liquid crystal display unit, receives the multiplexed television signal transmitted from the broadcasting station by the antenna 1, and superimposes the characters on the multiplexed television signal during the vertical blanking period of the video signal. The broadcast signal is extracted by the teletext signal extracting unit 2, and the extracted data is subjected to error correction processing in packet units by the serial-parallel conversion and error correction unit 3 and then the data is buffered. The data is transferred to the memory 4 and the CPU 5 processes the data in the buffer memory 4 after checking for errors. In the case of a system capable of program reservation, the data is stored in the data memory 6 while checking the program reservation status. Store / accumulate in units of
For example, in response to a program selection by the receiver by key input from an operation panel (not shown), the program is transferred to the decoding / display processing unit 7, subjected to decoding processing and display processing, converted into pixel data, and displayed on the display 8. Is configured to.

As described above, in the teletext receiving circuit according to the present invention, the large-capacity data memory 6 is provided so that a plurality of teletext programs can be stored and accumulated, and a plurality of buffer RAMs are provided.
Although it is intended to improve the fetchable processing time of the CPU 5 by providing the buffer memory 4 provided with the
The operation of the case where two M's are provided will be described with reference to the detailed block circuit configuration diagram of the main part shown in FIG. 2, the buffer RAM switching timing chart of FIG. 3 and the operation explanatory diagram of FIG. . Note that FIG. 2 is a conceptual one, and positive logic and negative logic are not considered.

That is, as shown in FIGS. 2 and 3, the serial-parallel conversion and error correction unit 3 receives the V-synchronization signal, the H-synchronization signal, the serial data, the operation clock, etc., and performs the serial-parallel conversion processing and the error correction. After performing the correction process, the error-corrected data and the specified address on the buffer RAMs 4I and 4II, which will be described later, are output, and the error correction process of all the data superimposed in the 1-vertical blanking period. Error-completion signal indicating that the process has finished and the buffer RAM4I, 4II
Outputs a bus control signal for switching the access destination of the serial-parallel conversion and error correction unit 3 and the CPU 5. The two buffer RAMs 4I and 4II have an address bus and a data bus from the CPU 5 and a serial / parallel conversion and error correction unit 3
The multiplexers 4i and 4ii for switching the address bus and the data bus from the above are connected one by one respectively. The CPU 5 receives the error correction processing end signal and starts the acquisition processing. The address bus and data bus from the CPU 5 are the above-mentioned two multiplexers 4i and 4ii.
Are connected to the respective buffer RAMs 4I, 4II via
In addition, via the address decoder 9, each buffer RAM4
It controls the chip select pins of I and 4II.

The V-synchronization signal and the error correction processing end signal are signals having waveforms as shown in (a) and (b) of FIG. 3, respectively. The error correction processing end signal is a signal for starting the fetch processing with respect to the CPU 5, and the select signal of the multiplexer 4i which changes at the trailing edge of the error correction processing end signal via the flip-flop 10 {third
(C) in the figure is created and its multiplexer
The select signal of 4i is inverted by the inverting element 11 to generate the select signal of the multiplexer 4ii {(d) in FIG. 3}, and the serial-parallel conversion and error correction unit 3 is provided for each of the two buffer RAMs 4I and 4II. The period for receiving the signal from the CPU and the period for receiving the signal from the CPU5 are alternately shifted in time. Therefore, the two buffer RAMs 4I and 4II operate with the timings shifted by 1-vertical blanking erase period and the 2-vertical blanking period, respectively.

On the other hand, the serial-parallel conversion and error correction unit 3 outputs a bus control signal {(e) in FIG. 3} to each of the two buffer RAMs 4I and 4II. ，
And the buffer RAMs sent from the serial / parallel conversion and error correction unit 3 to both the buffer RAMs 4I and 4II via the AND elements 12 and 13.
The timings of control signals for read / write are controlled respectively. Further, the select switching signals of the multiplexers 4i, 4ii produced by the flip-flop 10 switch the control signals for reading / writing the buffer RAMs 4I, 4II output from the CPU 5.

As described above, the host for accessing the respective buffer RAMs 4I and 4II is the buffer RA shown in (f) in FIG.
The M4I select signal is switched like the select signal of the buffer RAM4II shown in (g) of FIG.
It is increasing the time that can be spent on the U5 capture process.

That is, as shown in FIG. 4, CP in the case of the present invention
The available processing time T of U5 is extended until the end of the error correction processing of the next field, which is significantly larger than the available processing time t of the CPU in the conventional case shown in FIG. 6 described above. Increase to. Moreover, since a sufficient error correction processing time can be secured, the error correction processing can be performed plural times while changing the threshold value, and the error correction capability can be maximized.

Similar to FIG. 6, FIG. 4 also shows the processing of the CPU based on the V-synchronization signal generated based on the equivalent pulse on the receiver side. "Primary Superimposition Data Acquisition Processing" and "Error Correction Processing"
Are the same, and in the present invention, it indicates that the CPU available processing time is extended from t in FIG. 6 to T in FIG.

Although only the timing of the acquisition processing operation of the CPU 5 is entered in FIG. 3, the CPU 5 performs the decoding processing and the display processing of the selected program for the remaining time after the acquisition processing is completed. Further, in order to speed up the processing, it is possible to provide a plurality of CPUs, one for the fetch processing and the other one for the decoding processing and the display.

In the above embodiment, in order to simplify the explanation,
Although the case where the two buffer RAMs 4I and 4II are provided as the buffer memory 4 is shown, it will be apparent that the CPU take-in processable time T can be further extended by providing more buffer RAMs. .

<Effects of the Invention> As is apparent from the above detailed description, according to the teletext receiving circuit of the coded transmission system according to the present invention, large-capacity data capable of storing data of a plurality of teletext programs. Along with the provision of a memory, the data output from the error correction section is switched in a time-division manner and stored in multiple buffer memories in order to store the latest data in that data memory, thereby ensuring sufficient error correction processing time. However, since it is configured to increase the CPU uptake processing time, it is of course possible to store and store a plurality of teletext programs and to store the latest data in the data memory. -When a large number of data packets are superimposed within the vertical blanking interval, the data is sequentially transmitted in the order in which they are transmitted as in the conventional case. The data output from the error correction unit is extended by means of time-divisionally switching and storing in a plurality of buffer memories in a unit of 1-vertical blanking period, not by a simple means of taking in one buffer memory. It becomes possible to process multiple data packets at the same time within the processing time of the CPU.
Even if a large number of data packets are superposed and transmitted within the 1-vertical blanking period, the CP
An excellent effect that all the data packets can be processed with a sufficient margin without causing a problem in the U acquisition processing time is exhibited.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 4 show a specific embodiment of a teletext receiving circuit according to the present invention. FIG. 1 is a schematic block circuit configuration diagram of essential parts, and FIG. FIG. 4 is a detailed block circuit configuration diagram of a main part thereof, FIG. 3 is a timing chart of signals of respective parts, and FIG. Also, FIGS. 5 and 6 are for explaining the technical background of the present invention and the problems of the prior art,
FIG. 5 is a diagram for explaining the state of the multiplexed television video signal, and FIG. 6 is a diagram for explaining the operation of the conventional teletext receiving circuit. 2 ... Teletext signal sampling unit, 3 ... Serial / parallel conversion and error correction unit, 4 (4I, 4II) ... Buffer memory (RAM), 5 ... CPU, 6 ... Large-capacity data memory, 7 ... Decoding and display processing unit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 7/083 7/087 7/088

Claims (1)

[Claims] 1. A serial-parallel conversion process, an error correction process, which extracts a time-division multiplexed teletext signal from a received multiplexed television signal of a coded transmission system during a vertical blanking period of the video signal. By performing decoding processing, display processing, etc., it is possible to store the data of a plurality of teletext programs in the teletext receiving circuit of the coded transmission system configured to display the teletext contents on the display unit. A large-capacity data memory, an error correction unit that performs error correction processing on a teletext signal extracted from a video signal, and error-corrected data output from the error correction unit are stored, and the data is stored in the data memory. A plurality of buffer memories for outputting to the buffer memory, and the error-corrected data output from the error correction unit to the buffer memory in time division by 1-vertical blanking period unit. A teletext receiving circuit characterized by comprising a CPU for switching and storing with, and.