JP3118911B2 - Control signal multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal multiplexer for multiplexing a control signal with a synchronization signal.

[0002]

2. Description of the Related Art In a television monitoring system,
2. Description of the Related Art Conventionally, the direction control, zoom control, focus control, and the like of a television camera are performed by remote control to increase the monitoring capability. By the way, in order to remotely control a television camera, it is necessary to send a control signal to the television camera. To simplify the configuration, it has been conventionally required to multiplex the control signal with a synchronization signal for driving the television camera. Is being done.

FIG. 4 is a block diagram showing an example of a conventional control signal multiplexing apparatus of this type, which includes a CPU 11, a ROM 12, a RAM 13, a panel input / output unit 15, a buffer memory 17 and a CPU 11 connected to a common bus 16. Decoder 18
, A control panel 14 connected to the panel input / output unit 15, a mixer 19, and a clock generator 20.
It is composed of

The CPU 11 corresponds to the brain of the apparatus, and performs processing according to a program stored in a ROM 12 which is a nonvolatile memory.

[0005] The control panel 14 outputs control commands to the television camera in accordance with the operation of the operator.

The panel input / output unit 15 is an interface between the control panel 14 and the CPU 11.

The RAM 13 is a rewritable memory in which control commands input from the control panel 14 are temporarily stored, and has an area corresponding to a television camera to be controlled.

The control commands stored in the RAM 13 are transferred to and stored in the buffer memory 17.

The decoder 18 decodes an instruction output from the CPU 11.

The mixer 19 superimposes the control signal a read from the buffer memory 17 on the horizontal synchronizing signal b.

The clock generator 20 generates a read signal c synchronized with the horizontal synchronizing signal b.

FIG. 5 is a time chart of FIG. 4. The operation will be described below with reference to the drawings.

To control the direction and zoom of the television camera, the operator operates the control panel 14. When operated by an operator, the control panel 14 outputs an interrupt signal and outputs a control command including information indicating a control content corresponding to the operation and a television camera to be controlled. Also, control panel 1
Reference numeral 4 also outputs an interrupt signal when the operation is completed, and outputs a control command including information indicating that the control has been completed and information indicating the television camera whose control has been completed.

When an interrupt signal is output from the control panel 14, the CPU 11 starts execution of an interrupt processing program stored in the ROM 12, and first, the control command output to the bus 16 via the panel input / output unit 15. Take in. Next, the control command fetched based on the information indicating the TV camera to be controlled contained in the fetched control command is stored in an area of the RAM 13 corresponding to the TV camera.

The CPU 11 performs the following processing as normal processing in addition to the above-described interrupt processing in accordance with a program stored in the ROM 12.

That is, when a predetermined horizontal synchronization period is reached, the CPU 11 outputs a command for sequentially transferring the control commands stored in the area of the RAM 13 corresponding to each television camera to the buffer memory 17. This instruction is decoded by the decoder 18 so that the buffer memory 1
The control command stored in the area corresponding to each television camera in the RAM 13 is latched in the buffer memory 17. Note that the example of FIG. 5 shows that the transfer of the control command is started in the horizontal synchronization period T1, and the transfer is completed in the horizontal synchronization period T6.

The control command latched in the buffer memory 17 is read by a read signal c output from the clock generator 20 in accordance with the horizontal synchronization signal b, and is supplied to the mixer 19 as a control signal a. In the example shown in FIG.
, The read signal c is output.

The mixer 19 superimposes the control signal a read from the buffer memory 17 on the horizontal synchronizing signal b and outputs it as an output signal d.

Each television camera to which the output signal d is supplied performs direction control and the like according to the control signal a when the control signal a superimposed on the horizontal synchronization signal b is for the own television camera.

[0020]

In the above-described conventional control signal multiplexing apparatus, all control commands for each television camera, which is the controlled apparatus, are temporarily stored in the buffer memory 17, and then read out little by little to read out the horizontal synchronizing signal. Because of the superimposition, when the number of TV cameras to be controlled is large or when the control content is large and the number of bits of the control command is large, there is a problem that a large-capacity buffer memory is required.

An object of the present invention is to provide a control signal multiplexing device capable of reducing the capacity of a buffer memory.

[0022]

In order to achieve the above object, the present invention provides a control signal multiplexing apparatus for multiplexing control signals for a plurality of controlled devices into a synchronization signal as shown in the block diagram of FIG. A control panel 1 for outputting a control signal to each of the controlled devices; a storage unit 2 for temporarily storing a control signal for each of the controlled devices output from the control panel 1; Buffer memories 4 and 5, writing means 3 for alternately writing a predetermined number of control signals for each controlled device stored in the storage means 2 to the first and second buffer memories 4 and 5; First and second buffer memories 4 and 5
And a mixer 7 for superimposing the control signal and the synchronization signal read by the reading means 6 alternately.

[0023]

The control signal outputted from the control panel 1 is temporarily stored in the storage means 2. The writing means 3 writes the control signal for each controlled device stored in the storage means 2 to the first and second buffer memories 4 and 5 alternately.

The reading means 6 reads the control signal stored in the second buffer memory 5 when the control signal is written in the first buffer memory 4 by the writing means 3, and the writing means 3 reads the second control signal. Buffer memory 5
When the control signal is written in the first buffer memory 4, the control signal stored in the first buffer memory 4 is read.

The mixer 7 superimposes the control signal read by the reading means 6 on the synchronizing signal and outputs it.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which first and second two buffer memories 17-1 and 17 are provided.
-2, and the first and second buffer memories 17-1, 17-
2 and a changeover switch 21 for selecting one of the first and second buffer memories 17-17 in accordance with the horizontal synchronization signal b.
A clock generator 22 for alternately generating read signals e and f for the signals 1 and 17-2 and a decoder 23 are provided. In FIG. 2, the same reference numerals as those in FIG. 4 denote the same parts.

FIG. 3 is a time chart of the present embodiment.
Hereinafter, the operation of this embodiment will be described with reference to the drawings.

When the control panel 14 is operated to control the direction and zoom of the television camera, or when the operation is completed, an interrupt signal is output from the control panel 14 and the control is performed in the same manner as described above. The command is output.

When an interrupt signal is output, the CPU 11 executes an interrupt processing program in the same manner as described above, and controls the control command output from the control panel 14 on the RAM 13 according to the control command. To be stored.

The CPU 11 performs the following processing as normal processing in addition to the above-described interrupt processing in accordance with a program stored in the ROM 12.

That is, the CPU 11 operates at a predetermined timing (in this embodiment, the start time t of the horizontal synchronization period T9).
When 1) is reached, an instruction to transfer the N control commands stored in the first to Nth areas of the RAM 13 to the first buffer memory 17-1 is output. This instruction is decoded by the decoder 23, and as a result,
The control commands stored in the first to Nth areas are transferred to the first buffer memory 17-1.

Then, at the start time t2 of the next horizontal synchronization period T10, the CPU 11 sets the (N +
1) Outputs an instruction for transferring the control commands stored in the 2nd to 2Nth areas to the second buffer memory 17-2, and outputs an instruction for switching the changeover switch 21 to the A side. . This instruction is decoded by the decoder 23, and as a result, the (N + 1) th
The N control commands stored in the second to second Nth areas are stored in the second buffer memory 17-2, and the changeover switch 21 is switched to the A side.

The start time t2 of the horizontal synchronization period T10
, The clock generator 22 outputs a read signal e for the first buffer memory 17-1. As a result, the N control commands stored in the first buffer memory 17-1 are supplied to the mixer 19 as the control signal g1 via the changeover switch 21 and are superimposed on the horizontal synchronizing signal b.

That is, in the horizontal synchronization period T10, N control commands are read from the first buffer memory 17-1 and stored in the second buffer memory 17-2.
N control commands stored in the (N + 1) -th to (2N) -th areas are written.

Further, at the start time t3 of the next horizontal synchronization period T11, the CPU 11 sets the (2N +
1) Outputs an instruction for transferring the control commands stored in the third to third Nth areas to the first buffer memory 17-1, and outputs an instruction for switching the changeover switch 21 to the B side. . With this, RAM
N control commands stored in the (2N + 1) th to (3N) th areas of the thirteenth buffer memory 1
7-1, and the changeover switch 21 switches to the B side.

The start time t3 of the horizontal synchronization period T11
, The clock generator 22 outputs a read signal f to the second buffer memory 17-2. As a result, the N control commands stored in the second buffer memory 17-2 are supplied to the mixer 19 as the control signal g2 via the switch 21 and are superimposed on the horizontal synchronization signal b.

That is, in the horizontal synchronization period T11, the (2N +) th of the RAM 13 is stored in the first buffer memory 17-1.
1) N control commands stored in the 3rd to 3Nth areas are written, and the second buffer memory 17-
Two to N control commands are read.

Hereinafter, the same operation is performed for all control commands stored in the RAM 13.

As described above, in the present embodiment, the control command stored in the RAM 13 is alternately written into the first and second buffer memories 17-1 and 17-2, and the first and second buffer memories 17-1 and 17-2 are written.
Since the contents of the second buffer memories 17-1 and 17-2 are alternately read out, the N first and second buffer memories 17-1 and 17-2 store N data transferred during one horizontal scanning period. That is, it is only necessary to have a capacity enough to store the control command. Therefore, according to the present embodiment, the capacity of the buffer memory can be reduced.

[0041]

As described above, the present invention provides the first,
Since the second buffer memory is provided so that the control signal written in the other buffer memory is read out while the control signal is written in the other buffer memory, the capacity of the buffer memory is reduced compared to the conventional example. There is an effect that can be reduced in comparison.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a time chart of FIG. 2;

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a time chart of FIG. 4;

[Explanation of symbols]

 1, 14 control panel 2 storage means 3 writing means 4, 17-1 first buffer memory 5, 17-2 second buffer memory 6 reading means 7, 19 mixer 11 CPU 12 ROM 13 RAM 15 Panel input / output unit 16 Bus 17 Buffer memory 18, 23 Decoder 19 Mixer 20, 22 Clock generator 21 Switch

Claims (2)

(57) [Claims] 1. A control signal multiplexing device for multiplexing a control signal for a plurality of controlled devices with a synchronization signal, comprising: a control panel for outputting a control signal for each of the controlled devices; Storage means for temporarily holding a control signal for each of the controlled devices, first and second buffer memories, and a predetermined number of control signals for each of the controlled devices stored in the storage means. Writing means for alternately writing to the second buffer memory; reading means for alternately reading the contents of the first and second buffer memories; and a mixer for superimposing the control signal and the synchronization signal read by the reading means. And a control signal multiplexing device. 2. The control signal multiplexing device according to claim 1, wherein the synchronization signal is a synchronization signal for driving a television camera.