JPH11266426A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller by which an output image is not disturbed in the case of revising a control value of a memory of a write system asynchronously with a reference signal of the write system and a read system. SOLUTION: A delay circuit 100 delays a signal Sd required for read processing of data generated from a memory control value WHSTART of a write system. Thus, a delay discrimination signal SD whose delay time is coincident with a delay time of data read from frame memories 1-3 is obtained. Thus, an output image is not disturbed even when a control value of the memories of the write system in the case of writing data to the frame memories 1-3 in the memory controller that converts a transfer speed of a received digital video signal Din by using the frame memories 1-3 of a capacity of pluralities of frames.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for converting a transfer rate of an input digital signal and outputting the converted signal.

[0002]

2. Description of the Related Art For example, in a memory control device for converting a transfer speed in order to increase the recording density of a video signal, a series of digital video signals are read out at a timing different from an input timing for writing a digital video signal to a frame memory. I have to.

FIG. 7 is a block circuit diagram showing a configuration of a conventional memory control device.

Referring to FIG. 1, reference numerals 1 to 3 denote frame memories for storing input video signals as 16-bit digital data, and reference numeral 4 denotes input digital data Din having a configuration of 8 bits (1 word) per pixel converted to 16-bit data. The first bit width converter 5 is provided with the above frame memories 1 to 3
Read (READ), write (WRIT)
E) A data switch for switching the state.
Is connected to its input terminal A, and a vertical synchronizing signal W-VSYNC pulse of the input video signal (hereinafter, referred to as a W-VSYNC pulse)
W-VSYNC) and a vertical synchronizing signal R-VSYNC pulse (hereinafter, referred to as R-VSYNC) of the output video signal. Reference numeral 6 denotes a second bit width converter for converting 16-bit digital data into 8-bit digital data, and is connected to the output terminal B of the data switch 5.

A write control circuit 7 controls the writing of the frame memories 1 to 3. The W-VSYNC and the horizontal synchronizing signal W of the input video signal are used as synchronizing signals.
-HSYNC pulse (hereinafter, referred to as W-HSYNC) is supplied. Reference numeral 8 denotes a read control circuit for performing read control of the frame memories 1 to 3, to which the R-VSYNC and a horizontal sync signal R-HSYNC pulse (hereinafter, referred to as R-HSYNC) of an output video signal are supplied as sync signals. ing. Reference numeral 9 denotes a microcomputer for setting a write start position in the write control circuit 7.
The microcomputer 9 outputs to the write control circuit 7 a write start position signal WHSTART for setting the data write start position of the frame memories 1 to 3 in the horizontal direction.

Reference numeral 10 denotes an address value (valid data set value) indicated by the signal WHSTART output from the microcomputer 9.
Is an LSB discriminating circuit for discriminating whether the signal WHSTART is an odd number or an even number.
ant bit) is output. Reference numeral 11 denotes a mask circuit connected to the second bit width converter 6. The mask circuit 11 outputs valid data of output video signals output from the frame memories 1 to 3 based on the determination signal Sd. The range is determined and the first one of each line
The pixel data is masked.

Next, an outline of the operation of the conventional memory control device will be described.

FIG. 8 is a conceptual diagram for explaining the writing and reading operations to and from the frame memory. Here, as shown in FIG. 1A, in order to convert the transfer speed of the input video signal converted into digital data, first, one pixel 8
The digital data Din input as bits is converted by the first bit width converter 4 into 16-bit digital data. This is a commonly used technique when storing digital data transmitted at a very high speed in a frame memory. After the 16-bit digital data is input to the data switch 5, the vertical synchronizing signal W-VSYNC and the horizontal synchronizing signal W-H of the input video signal are output.
An N-line video signal constituting a video of one frame is sequentially written to one of the frame memories 1 to 3 on a line-by-line basis on the basis of SYNC (FIG. 2B). Thereafter, as shown in FIG. 3C, the R-VSYNC and the R-HSYNC of the output video signal are used as a reference.
The transfer speed is converted by reading out 16-bit digital data from any of the frame memories 1 to 3 as an output video signal in which one line consists of 8 bits × M pixels.

FIG. 9 is a timing chart for explaining a write start position based on the signal WHSTART.

Here, the switching of the read / write state for the frame memories 1 to 3 is performed by W-VSYN, respectively.
This is performed in synchronization with C and R-VSYNC.
As shown in (a), the digital data Din of one pixel is converted into 16-bit digital data by the first bit width converter 4 and input to the frame memories 1 to 3. The write control circuit 7 controls the writing of video signals to the frame memories 1 to 3 on a line-by-line basis on the basis of W-HSYNC. At this time, the signal WHSTART from the microcomputer 9 determines which pixel of the input video signal is to be written as data to the frame memories 1 to 3 based on W-HSYNC, that is, starts writing to the frame memories 1 to 3. The position is designated for the write control circuit 7.

For example, in order to start writing from the fourth pixel data, the address value of "4" is set as the effective data setting value. When writing is started from the fifth pixel data, the address value of "5" is similarly set. Address value is signal WHSTAR
As T, it is sent from the microcomputer 9 to the write control circuit 7. Then, the write control circuit 7 controls the writing of the digital data converted into 16 bits on a line-by-line basis based on the effective data set value.

The write control circuit 7 has a structure in which 8-bit digital data is converted into 16-bit data in advance and written into the frame memories 1 to 3. Therefore, as shown in FIG.
Even if the address value of the ART is "5", the fourth 8-bit data is actually written.
The 16-bit digital data written in the frame memories 1 to 3 is read line by line by a control signal output from the read control circuit 8 on the basis of R-HSYNC. The read 16-bit digital data is converted by the second bit width converter 6 into 8-bit digital data.

FIG. 10 is a timing chart for explaining a read start position by the mask circuit.

FIG. 1A shows how 16-bit digital data output from the frame memories 1 to 3 is converted into 8-bit data by the second bit width converter 6. In the LSB determination circuit 10, the signal WHS
Whether the read start position is an odd pixel based on TART,
Alternatively, one of the even pixels is determined. When the pixel is determined to be an even pixel, the determination signal Sd is set to “L”, and when the pixel is determined to be an odd pixel, the determination signal Sd is set to “H” and output to the mask circuit 11. In the mask circuit 11, if the determination signal Sd from the LSB determination circuit 10 is "L", the second
The output video signal Dout output as 8-bit data from the bit width converter 6 is output to the subsequent processing circuit without masking. However, if the discrimination signal Sd is "H", 1
Digital data obtained by masking the 8-bit data of the first pixel of the line becomes the output video signal Dout.

For example, as shown in FIG.
When START is “4”, since the input video signal has been written to the frame memories 1 to 3 from the fourth pixel data, unnecessary data is not input to the mask circuit 11. However, if WHSTART is "5",
As shown in FIG. 10C, the fourth 8-bit data written to the frame memories 1 to 3 in 16-bit units is input to the mask circuit 11 as unnecessary data. Accordingly, in this case, the fourth pixel data read from the frame memories 1 to 3 as the head pixel of each line is converted into 8 bits by the second bit width converter 6.
After being converted into digital data of bits, it is necessary to mask the valid data with the mask circuit 11 as data outside the range.

Therefore, in the mask circuit 11, WHSTA
If RT is an even number, the output of the second bit width converter 6 is output as it is to the subsequent processing circuit without masking.
In the case of an odd number, a video signal in which the data of the first pixel of each line is masked is output to the subsequent processing circuit.

Next, the operation of the data switch 5 will be described.

FIG. 11 is a state transition diagram showing an example of the state transition of the frame memory. A data switching operation based on this state transition diagram is programmed in the data switch 5, and the 16-bit digital video signal written to the frame memories 1 to 3 and the 16-bit digital video signal to be read are stored in the state S0. ＳS11 are selected. That is, the input / output terminals M1 to M3 to which the frame memories 1 to 3 are connected, the input terminal A of the digital data, and the input terminal A of the digital data, according to the input timing of the W-VSYNC and the R-VSYNC asynchronously input to the memory control device. The switching state between the data and the output terminal B is switched.

For example, it is assumed that the frame memories 1 to 3 are in the state S0. That is, the frame memory 1 is in the read state (R), the frame memory 2 is in the write state (W),
The frame memory 3 is currently in a read standby state (F: FULL). At this time, when W-VSYNC is input, the frame memories 1 to 3 transit to the state of S2, and as a switching state, the terminal M1 is connected to the terminal B,
Terminal A is connected to terminal M3 (hereinafter, M1 → B,
Described as A → M3. ). Furthermore, next, R-VSYN
If C is input, the state transits from S2 to S11, and the switching state changes from A to M2 and M3 to B. At this time, the frame memory 1 is in the write standby state (E: EMPT
Y).

However, the frame memories 1 to 3 first store S
In the state of 0, R-VSY prior to W-VSYNC
When the NC is input, the frame memories 1 to 3 store S1
1 state. Note that R-VSYNC and W-VS
If the YNCs are simultaneously input, the state transits to the state S5.

Next, the overall operation of the memory control device will be described in more detail.

FIG. 12 is a timing chart showing the state transition of the frame memories 1 to 3. In this timing diagram,
The frame memory 1 operates in a write state (W), the frame memory 2 operates in a read state (R), and the frame memory 3 operates in a read standby state (F).
That is, the operation starts from the state of S4 shown in the state transition diagram of FIG.

For the memory control device in this state S4,
First, when, for example, R-VSYNC is input (timing t1), based on the state transition diagram of FIG.
7 and the state changes from (A → M1, M2 → B) to (A
→ M1, M3 → B). Then, data for one frame, that is, frame data # (-
After the reading of 1) is completed, the apparatus enters the write standby state (E). That is, the supply of the read control signal and the read address output from the read control circuit 8 to the frame memory 2 is stopped, and instead, the read control signal and the read address are sent to the frame memory 3 which has been in the read standby state (F). The read address is supplied, and the frame data # already written in the frame memory 3
(0) is read. On the other hand, the write control signal and the write address are continuously supplied from the write control circuit 7 to the frame memory 1 in the write state (W),
Frame data # (1) is written.

Next, when W-VSYNC is input to the memory controller (timing t2), the state changes from S7 to S10 based on the state transition diagram of FIG.
2, M3 → B). At this point, the frame memory 1 in the write state (W) has already been written with the frame data # (1), and the supply of the write control signal and the write address from the write control circuit 7 is stopped. The memory 1 enters the read standby state (F). Instead, the frame memory 2 in the write standby state (E) becomes the write state (W), the write control signal and the write address are supplied from the write control circuit 7, and the frame data # (2) is written into the frame memory 2. It is. The read control signal and the read address are continuously supplied from the read control circuit 8 to the frame memory 3 in the read state (R), and the frame data # (0) is read.

Thereafter, a series of operations are repeatedly performed in such a cycle, and the frame data # (-1), # (0), and # are stored in the frame memories 1 to 3 as digital video signals.
(1),... Are written and their frame data is read out with a delay of a predetermined timing, so that the transfer speed of the digital video signal can be converted.

[0026]

The conventional memory control device is constructed as described above,
W-VSYNC and W-VSYNC
HSYNC is R-VSYNC as a readout system reference signal.
C and R-HSYNC are used.

However, in the conventional memory control device, the address value (valid data set value) of the write start position signal WHSTART to the frame memory is changed without synchronizing with any of these reference signals. There was an inconvenience like

FIG. 13 is a timing chart for explaining a change in the effective data set value. W which is the control value of the writing system
As shown in FIG. 13A, the address value of the HSTART has been changed by the microcomputer 9 at an arbitrary timing that is asynchronous with both the W-VSYNC and the R-VSYNC. Therefore, at the timing t0 shown in FIG.
When START is switched, the write control is performed by the write control circuit 7 so that the set address value becomes valid from frame data # (2) written at timing t2.

In such a case, if the pixel position specified by the signal WHSTART is changed from an even-numbered pixel to an even-numbered pixel, the mask circuit 11 controls the first one pixel of each line before and after the change. No masking is performed. However, when the designation of the pixel position is changed from the even number to the odd number as shown in FIG. 13, the determination signal Sd changes from "L" to "H" as shown in FIG. Frame data # (-
In contrast to 1), the mask circuit 11 deletes the first pixel of the line after the frame middle position. However, since the frame data # (-1) is the frame data before the setting change is performed, the data of the first pixel is written as valid data.

For example, if the set value of WHSTART is changed from "4" to "5", the writing start position is changed to the fifth data for the data after frame data # (2), and the first one pixel is changed. Must also be made from this data. But,
In the LSB discriminating circuit 10, the discrimination signal Sd becomes "H" at the timing t0 when the change is made, and the leading one pixel is masked from the line in the middle of the frame data # (-1). Similarly, when the set value of WHSTART is changed from an odd number to an even number, pixel data of a frame that should be masked is output to a subsequent processing circuit without being masked.

Therefore, immediately after the setting value is changed by the microcomputer 9, one pixel of each line which must be actually read is missing or an extra pixel is read. A defect occurs in the frame data to be read. For this reason, there has been a problem that a screen output at a changed transfer speed is often disturbed.

The present invention has been made to solve the above-described problems, and the control value of the write system is changed without synchronizing with the reference signal of the write system and the reference signal of the read system. It is another object of the present invention to provide a memory control device that can reliably limit data outside the valid data range of n-word data that is read only by adding a very small amount of hardware.

[0033]

According to a first aspect of the present invention, there is provided a memory controller for converting a transfer rate of an input digital signal and outputting the converted digital signal in n words (n ≧ n). 2) a plurality of frame memories which can be written in a width, write control means for selecting the frame memory and writing only valid data among the digital signals to the selected frame memory, and the frame memory Read control means for reading n-word data written to the memory; set value generation means for generating a set value for setting the valid data to the write control means; and a frame memory based on the set value. Determining means for generating a determination signal indicating a range of valid data of the written n-word data; A delay means for delaying the signal to the write start position of the valid data, and further delaying by a time from when the n-word data is written to the frame memory until it is read, and based on the delayed determination signal, Means for restricting data outside the valid data range of the n-word data read from the frame memory.

The memory control device according to a second aspect of the present invention further comprises conversion means for converting the n-word data read from the frame memory into one-word data, and the limiting means comprises a one-word data output from the conversion means. As for data, data outside the range of valid data is restricted.

The memory control device according to claim 3 further comprises a conversion means for converting a one-word-width digital signal input in units of lines into n-word data, and an output of the conversion means is written into the frame memory. Things.

In the memory control device according to a fourth aspect, the read control means is configured to read n-word data from the frame memory in line units.

In the memory control device according to the fifth aspect, the read control means is configured to read n from the frame memory in units of blocks.
It is configured to read word data.

In the memory control device according to the sixth aspect, the n-word data is 2-word data.

In the memory control device according to the present invention, the input digital signal is a digital video signal.

[0040]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described.

Embodiment 1 FIG. 1 is a block circuit diagram showing a memory control device according to the first embodiment.
1 to 3 are frame memories, 4 is a first bit width converter,
5 is a data switch, and 6 is a second bit width converter. Further, 7 is a write control circuit, 8 is a read control circuit, 9 is a microcomputer, 10 is an LSB determination circuit, and 11 is a mask circuit.

Each block denoted by reference numerals 1 to 11 is
This is the same as that of the conventional example shown in FIG. 7, and the detailed description thereof is omitted. 100 is the LSB determination circuit 10
This is a delay circuit that outputs a new determination signal _SD obtained by delaying the determination signal Sd from the CPU by a predetermined time. This delay circuit 1
00 is supplied with W-VSYNC and R-VSYNC in addition to the discrimination signal Sd.

In the memory control device according to the first embodiment, the input digital data Din of 8 bits (1 word) is supplied to the first bit width converter 4 as in the conventional example.
And converted into 16-bit (two-word) digital data. The 16-bit digital data is input to the terminal A of the data switch 5 and output from the terminals M1 to M3 according to the switching state defined in the state transition diagram shown in FIG.
3 is stored. The write control circuit 7 outputs a write control signal, a write address, and the like to any of the frame memories 1 to 3 according to a set value of a write position of the signal WHSTART input from the microcomputer 9. Thus, the operation of writing the frame data to the frame memories 1 to 3 is controlled.

The frame data written in any of the frame memories 1 to 3 is read out by the read control circuit when the switching state of the data switch 5 changes and each of the frame memories 1 to 3 becomes the read state. In accordance with the read control signal and the read address output from 8, the data is read to the data switch 5 as 16-bit digital data. These 16-bit digital data are once input to the data switch 5 and then output from the terminal B to the second bit width converter 6, where they are converted into 8-bit digital data. And mask circuit 1
The video signal for one frame is read out on a line-by-line basis. The operation of switching the 16-bit digital data by the data switch 5 is the same as that of the conventional example, and the description is omitted here.

Next, the operation of the memory control device according to the first embodiment will be described.

FIG. 2 is a timing chart for explaining the operation of the memory control device. The signal WHSTART is sent from the microcomputer 9 at the timing shown in FIG.
When the setting change is commanded, the writing start position of each line is changed from the frame data # (2) as in the conventional example (FIG. 2 (h)). At the same time,
This signal WHSTART is also input to the LSB determination circuit 10 (FIG. 2D). Here, the LSB of the set pixel value indicated by the signal WHSTART is determined, and a determination signal Sd (FIG. 2 (j)) is formed.
Is input to Here, similarly to the conventional example, the signal W
When the set pixel value of HSTART is an even number, the discrimination signal Sd becomes "L", and when it is an odd number, it is outputted as "H".

When the discrimination signal Sd is input to the delay circuit 100, it is first delayed by two frames with reference to W-VSYNC (FIGS. 2 (k) and (l)). Next, R-V
Delayed by one frame based on SYNC (FIG. 2)
(M)). The discrimination signal _SD delayed in this manner coincides with the timing of R-VSYNC at which the frame data # (2) is read from the frame memory 2. And
As described above, the frame data # (2) is data in which the writing start position has been changed by WHSTART at the time of writing. That is, the discrimination signal _SD has no effect on the frame data before the change of the write start position is performed, and completely matches the timing of the changed frame data.

Now, it is assumed that the set value of WHSTART has been changed from "4" to "5" by the microcomputer 9. Frame data # (1) is written in WHSTART =
This is performed in the state of “4”. And the frame data #
The write operation (2) is performed in the state of WHSTART = "5". Here, WHSTART is input to the LSB determination circuit 10 at the same time as being input to the write control circuit 7. In this LSB determination circuit 10, WHSTA
Determine whether the pixel position set from RT is odd or even,
The determination signal Sd is output to the delay circuit 100. Therefore, when WHSTART changes from "4" to "5", it means that WHSTART has changed from an odd number to an even number, and the determination signal Sd changes from "L" to "H".

When this discrimination signal Sd is input to the delay circuit 100, it becomes the discrimination signal _SD delayed as described above, and is output at the timing of reading out the frame data # (2). That is, this frame data # (2)
Since the data is written after the state of TART = "5", the extra data of the first pixel of each line is deleted as described above (see FIGS. 9 and 10) in the conventional example. There is a need to. Therefore, if the discrimination signal _SD is “H” at the timing of reading the frame data # (2), the mask circuit 11 masks the data of the first pixel of each line in each frame after the frame data # (2). Will be done.

Since each frame data before frame data # (1) is written with WHSTART set to "4", the first 1 of each line is written.
There is no need to delete pixels. In the memory control device of the first embodiment, since the discrimination signal _SD is "L" before the read frame data # (1), the mask circuit 1
It is not masked by 1.

In the above description of the operation, WHSTART has changed from an even number to an odd number. FIG.
FIG. 11 is a timing chart for explaining the operation of the memory control device when HSTART changes from an odd number to an even number.

For example, when WHSTART from the microcomputer 9 changes from "5" to "4", the discrimination signal _SD is output at the timing of reading out the frame data # (2). For each frame data, WHSTART = "5", that is, odd pixels are set, and the first pixel of each line is masked. However, since the data after the frame data # (2) is changed to WHSTART = "4", that is, to the even-numbered pixels, the data of the first pixel of each line is not masked.

As described above, according to the memory control device of the first embodiment, WHSTART is set to W-VS
Even if it is set to be completely asynchronous with YNC and R-VSYNC, the delay discrimination signal _SD considering the delay amount between frames at the time of writing and reading is formed. Even if the write start position of the data is changed, when the read frame data is output to the screen, there is no problem such as disturbance. Therefore, a normal output screen can be formed without any instantaneous disturbance of the output signal whose write start position of the memory has been changed.

In the memory control device according to the first embodiment, when changing the effective area of the screen or the like, the control on the read side can always be kept constant only by controlling the take-out position at the time of writing. . In addition, the setting of the amount of delay between frames at the time of writing and at the time of reading can also be realized by delaying only the LSB of the write address with a simple delay circuit composed of, for example, only one D flip-flop. Become scale.

In addition, the control value on the read side is not changed while data is being read from the frame memory. Therefore, the output screen from the frame memory is not disturbed by the change of the writing start position. Similarly, to prevent burn-in of the monitor, for example,
Even when the display position is moved in pixel units, the output screen is not disturbed even if the control value of the frame memory is changed.

Further, in the first embodiment, processing is performed such that image data input with an 8-bit (1 word) width is converted to a 16-bit width and stored in a frame memory. For example, when an A / D converter that outputs image data in units of two words at the time of sampling is used, it is not necessary to perform 8-bit to 16-bit bit width conversion.

Embodiment 2 FIG. 4 is a block circuit diagram showing a configuration of the memory control device according to the second embodiment of the present invention.

In FIG. 4, reference numerals 1-3, 5, 7-1
The blocks indicated by 0 and 100 are described in the first embodiment.
Are the same as those described above, and detailed description thereof is omitted. Reference numeral 200 denotes a control signal generation circuit that generates a control signal based on the determination signal _SD from the delay circuit 100. The control signal generation circuit 200 includes a determination signal Sd
In addition to the above, W-VSYNC and R-VSYNC are supplied, and, among the 16-bit digital data read from the frame memories 1 to 3, whether the upper 8-bit data and the lower 8-bit data are respectively valid or not. Are generated as the control signals HACT and LACT. In the following, when upper data is valid, HACT =
When “H” is output and the lower data is valid,
It is assumed that LACT = "H" is output.

FIG. 5 is a timing chart for explaining the operation of the memory control device. As shown in FIG. 5A, the data input to the data switch 5 is obtained by subjecting the image data to A / D conversion in units of two pixels (16-bit width). Image data is written in units of two words (two pixels). Therefore,
If the writing start position of each line (specified by the signal WHSTART as in the conventional example and the first embodiment) is an odd pixel, the frame memories 1 to 3
Is written with extra data for the first pixel. 5 together with the digital data read out from the frame memories 1 to 3 in units of two words.
(B) As shown in (c), a control signal indicating whether the image data is valid for the upper data and the lower data of the 16-bit data in units of two pixels is output to the subsequent processing circuit. .

Hereinafter, the operation of the memory control device will be described with reference to the timing chart shown in FIG. 2 as in the first embodiment. At the timing shown in FIG.
When the setting of WHSTART is changed from, the WHSTART of each line is changed from frame data # (2) as in the first embodiment. WHST at the same time
ART is input to the LSB discriminating circuit 10, and WHSTAR
The LSB of T is determined, and the determination signal Sd is output to the delay circuit 1
00 is input. That is, similar to the first embodiment,
If the set value of WHSTART is an even number, the determination signal Sd
Becomes "L", and if it is an odd number, it becomes "H".

The discrimination signal Sd input to the delay circuit 100
Is first delayed by two frames with respect to W-VSYNC. Next, it is delayed by one frame based on R-VSYNC. The discrimination signal _SD delayed in synchronization with R-VSYNC in this way coincides with the timing at which the frame data # (2) is read, as shown in the timing diagram of FIG. This frame data #
(2) is a frame in which the writing start position has been changed by WHSTART during writing. Therefore, the discrimination signal _SD does not affect the data before the change is made, and the timing completely coincides with the changed data.

The discrimination signal S output from the delay circuit 100
_D is input to the control signal generation circuit 200. In the control signal generating circuit 200, as shown in FIG. 5 (b) (c), HACT and L according to the polarity of the discriminating signal S _D
ACT is output. That is, when WHSTART = 1, the upper 8 bits of 16-bit data read in units of two words are recognized as extra data for the first pixel.

As described above, according to the memory control device of the second embodiment, the WHSTART supplied to the frame memories 1 to 3 is changed to the W-VSYNC or the R-VSYNC.
Even if it is changed completely asynchronously with C, since the delay amount between frames at the time of writing and reading is taken into consideration, a normal output screen can be obtained without disturbing the output signal.

Further, when changing the effective area of the screen, it is only necessary to control the take-out position at the time of writing, and the control value on the reading side may be kept constant at all times.
Also, the delay between frames at the time of writing and reading is
For example, this is realized by delaying only the LSB of the write address by a delay circuit composed of only one D flip-flop, and the hardware becomes smaller.

Also, while data is being read from the frame memory, the control value on the reading side does not change. Therefore, by changing the write start position,
The output screen from the frame memory is not disturbed. Similarly, even if the display position is moved in pixel units, for example, in order to prevent burn-in of the monitor, the output screen is not disturbed even if the control value of the frame memory is changed.

In the first and second embodiments, the case where the set value of the signal (WHSTART) for specifying a pixel position is changed has been described. For example, the same effect can be obtained by applying when changing another set value such as a vertical write start value.

In the first and second embodiments, the case where the transfer rate is converted using the frame memories 1 to 3 for three frames has been described. However, the capacity of the frame memory is not necessarily required for three frames, and the same effect can be obtained with a frame memory control device having a capacity of at least two frames.

The data switch 5 in the first and second embodiments uses the state transition diagram shown in FIG. 11 as an example. However, such a state transition is not necessarily required. The same effect can be obtained even if the data switching operation in the switching state is programmed.

In the memory control devices of the first and second embodiments, it is not always necessary to input the digital data constituting the video signal. The same applies to any other memory control device to which the digital data is input. The effect of can be obtained.

In the first and second embodiments, writing and reading of data in and from frame memories 1 to 3 are performed in a two-word width (16 bits). However, the writing and reading are not necessarily performed in units of two words. When writing to and reading from the frame memory in units of n words (n ≧ 2),
The difference between the start position written in the frame memory with n words (n ≧ 2) width and the start position to be read as the original valid data can be determined. Then, the determination signal indicating the determination result is delayed until the timing at which the valid data is read from the frame memory and thereafter converted to one-word data, and at the same timing as the valid data actually read from the frame memory. By supplying the same to the mask circuit, the same effect as in the first and second embodiments can be obtained.

Further, in the first and second embodiments, when the video data in the frame memories 1 to 3 is read, the video data is read out line by line and the valid data is read out from the frame memories 1 to 3 in the line unit. The determination signal Sd is delayed, and the frame memory 1
3 is supplied to the mask circuit 11 at the same timing as the valid data read. However, the memory control device of the present invention is not necessarily limited to the case where the video data is read out line by line.

FIG. 6 is a diagram showing a state in which a video signal for one frame is divided into a plurality of blocks.

As shown in FIG. 6, for example, when video data is read out in units of blocks consisting of 8 pixels in the horizontal direction and 8 lines in the vertical direction, the start position written into the frame memory with a width of n words (n ≧ 2) And the start position to be read as the original valid data are determined. Then, if the determination signal indicating the determination result is delayed until the valid data is read from the frame memory in block units, and supplied to the mask circuit at the same timing as the valid data actually read from the frame memory, the frame is actually The output screen read from the memory is not disturbed.

[0074]

According to the memory control device of the present invention, the determination signal indicating the valid data range of the n-word data written in the frame memory is delayed until the n-word data in the valid data range is read. Therefore, after the image data is written in the frame memory in units of n words, data outside the valid data range of the n word data to be read can be reliably limited.

In the memory control device according to the second aspect of the present invention, the determination signal indicating the valid data range of the n-word data written in the frame memory is delayed until one word data in the valid data range is read. After the image data is written to the frame memory in units of n words, the data outside the valid data range for the image data when the read n-word data is converted into one-word data is reliably limited. be able to.

The memory control device according to the third aspect of the present invention is configured to convert a 1-word-width digital signal input in units of lines into n-word data. After writing to the memory, data outside the valid data range of the n-word data to be read can be reliably limited.

In the memory control device according to the fourth aspect of the present invention, the discrimination signal indicating the range of valid data of the n-word data written in the frame memory is used until the n-word data of the valid data range is read out in line units. Since the delay is configured, after the image data is written to the frame memory in units of n words, data outside the valid data range of the n words read out in units of lines can be reliably limited.

In the memory control device according to the fifth aspect of the present invention, the determination signal indicating the valid data range of the n-word data written in the frame memory is used until the n-word data in the valid data range is read in block units. Since the delay is configured, after the image data is written to the frame memory in units of n words, data outside the valid data range of the n words read out in units of blocks can be reliably limited.

In the memory control device according to the sixth aspect of the present invention, the determination signal formed according to whether the write start position to the frame memory is an odd number or an even number is delayed until two word data in the valid data range is read. Since the image data is written in the frame memory in units of two words, data outside the valid data range of the two-word data to be read can be reliably limited.

In the memory control device according to the seventh aspect of the present invention, by using a digital video signal as an input digital signal, when the horizontal write start position is changed, only the write start address is changed and the read address is changed. Without changing the control operation, it is possible to prevent the output screen from being disturbed by adding only a small amount of hardware.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a memory control device according to a first embodiment;

FIG. 2 is a timing chart for explaining the operation of the first embodiment;

FIG. 3 is a timing chart for explaining the operation of the first embodiment;

FIG. 4 is a block circuit diagram illustrating a memory control device according to a second embodiment;

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

FIG. 6 is a diagram showing a state in which a video signal for one frame is divided into a plurality of blocks.

FIG. 7 is a block circuit diagram showing a conventional memory control device.

FIG. 8 is a conceptual diagram illustrating a write operation to a memory.

FIG. 9 is a timing chart for explaining the operation of the conventional device.

FIG. 10 is a timing chart for explaining the operation of the conventional device.

FIG. 11 is a diagram illustrating an example of a state transition of a frame memory.

FIG. 12 is a timing chart for explaining the operation of the conventional device.

FIG. 13 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

1 to 3 frame memory, 4 first bit width converter, 5 data switcher, 6 second bit width converter, 7 write control circuit, 8 read control circuit, 9 microcomputer, 10 LSB determination circuit, 11
Mask circuit, 100 delay circuit, 200 control signal generation circuit.

Claims (7)

[Claims] 1. A memory control device for converting a transfer rate of an input digital signal and outputting the converted signal, wherein a digital signal input in units of lines is converted into n words (n words).
≧ 2) a plurality of frame memories which can be written in a width, write control means for selecting the frame memories and writing only valid data among the digital signals to the selected frame memories, and the frame Read control means for reading n-word data written in the memory; set value generation means for generating a set value for setting the valid data in the write control means; and the frame memory based on the set value. Discriminating means for generating a discrimination signal indicating the range of the valid data of n word data written into the memory; delaying the discrimination signal to a write start position of the valid data;
Delay means for delaying the time from when the word data is written to when it is read; means for limiting data outside the valid data range of the n-word data read from the frame memory based on the delayed determination signal And a memory control device. 2. The image processing apparatus according to claim 1, further comprising a converting unit configured to convert the n-word data read from the frame memory into one-word data, wherein the limiting unit converts one word data output from the converting unit into valid data. 2. The memory control device according to claim 1, wherein data outside the range is limited. 3. The apparatus according to claim 1, further comprising a converter for converting a one-word-width digital signal input on a line-by-line basis into n-word data, wherein an output of said converter is written to said frame memory. The memory control device according to claim 1 or 2. 4. The memory control device according to claim 1, wherein the read control unit is configured to read n-word data from the frame memory in line units. . 5. The memory control device according to claim 1, wherein the read control unit is configured to read n-word data from the frame memory in block units. . 6. The memory control device according to claim 1, wherein said n-word data is two-word data. 7. The memory control device according to claim 1, wherein said input digital signal is a digital video signal.