JPH05143283A - Data speed converter - Google Patents

Abstract

PURPOSE:To provide a highly reliable data speed converter to prevent the data in a data buffer from being dissipated. CONSTITUTION:While data buffers 1, 2 and 3 can write, a chip selector control circuit 14 switches a switch 16 through a chip selector 4 in the sequence of terminals (a), (b), (c) and (a), and thus, the data inputted from an (A) side are written in the sequence of data buffers 1, 2, 3 and 1. When these data buffers can read, by synchronizing to this, a chip selector control circuit 15 switches a switch 17 through a chip selector 5 in the sequence of terminals (c), (a), (b) and (c), and thus, from data buffers 3, 1, 2 and 3, the data are read in the sequence and outputted to (B). At this time, the same data buffer is controlled so as not to become simultaneously for writing and for reading, and the speed of input data and output data is converted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rate converter for changing the rate of data transmitted in data communication or the like.

[0002]

2. Description of the Related Art Conventionally, this type of data rate conversion device is
Since it is inside the DSU and the transmission data rate between the terminal side-DSU and the DSU-OCU is different, it is used for converting the transmission data rate. FIG. 4 is a block diagram showing an example of a conventional data rate converter of this type. here,
It is assumed that data is transmitted from [A] to [B] in the figure, and the data rate is changed between [A] and [B]. The read / write selection circuits 9 and 10 set the write enable signal to the high level to the data buffers 1 and 2 as shown in FIG.
Make 2 writable. Chip selector control circuit 13
Is the switch 1 via the write side chip selector circuit 5.
6 is switched in the order of the terminals a, b, a ... And the data buffer for writing is selected at a predetermined interval. Therefore, as shown in FIG. 5B, the write side chip selector circuit 5 selects the write data buffer in the order of the data buffer 1, the data buffer 2, the data buffer 3, the data buffer 1. As a result, the data input from [A] is alternately written into the data buffer 1, the data buffer 2, the data buffer 1, ... As shown in FIG. In the figure, the shaded area indicates the access to the data buffer 1, and the white area indicates the access to the data buffer 2.

On the other hand, read / write selection circuits 9, 10
5 periodically sets the read enable signal to the high level as shown in FIG. 5C to put the data buffers 1 and 2 in a readable state. Along with this, the chip selector control circuit 1
4 switches the switch 17 in the order of terminals b, a, b ... Through the read side chip selector circuit 8, and FIG.
As shown in (D), the read data buffer is selected in the order of data buffer 2, data buffer 1, data buffer 2 ... Therefore, as shown in FIG. 2F, the data is read from these data buffers in the order of data buffer 2, data buffer 1, data buffer 2, ... B] side.

Here, the data for each data buffer is written in the address portion generated from the corresponding address generation circuit in accordance with the write clock WCLK.
Further, the reading of data from each data buffer is performed by reading the data of the address part generated from the corresponding address generating circuit according to the read clock RCLK. That is, the address generating circuit 6 corresponds to the data buffer 1 and the address generating circuit 7 corresponds to the data buffer 2, and each address generating circuit supplies the write / read address to the corresponding data buffer. Moreover, the above-mentioned write clock WCLK
Since the speed of the read clock RCLK is set to be different, the speed of data when input from [A] is different from the speed of data output from the switch 17 to the [B] side. Data speed conversion is performed.

By the way, in the conventional device shown in FIG. 4, when different data buffers are assigned for reading and writing as shown in FIG. 6, no problem occurs, but data is stored in the same data buffer. If writing and reading are simultaneously assigned, the data in the data buffer may be lost before being read. FIG. 5 described above is a time chart for explaining the data speed conversion operation of the device shown in FIG. 4 when the read speed is faster than the write speed. For example, when the write enable signal output from the write / read selection circuits 9 and 10 goes to a high level as shown in FIG. 5A, the chip selector control circuit 13 causes the write data buffer shown in FIG. The data buffer 1 is selected as shown. Therefore, as shown in FIG. 5E, the data on the [A] side is written in the data buffer 1 from the time when the write enable signal becomes high level.

Thereafter, as shown in FIG. 5C, the write / read selection circuits 9 and 10 output the read enable signal, and at the same time, the chip selector control circuit 14 operates by the chip selector circuit 8 as shown in FIG. 5D. When the data buffer 2 is selected for reading, data is read from the data buffer 2 as shown in FIG.
This data is output to the [B] side via the switch 17. Next, when the chip selector control circuit 13 switches the data buffer for writing to the data buffer 2 by the chip selector circuit 5, as shown in FIG. 5B, [A]
The input data from the side is sent through the switch 16 as shown in FIG.
It is written in the data buffer 2 as shown in FIG. When the read signal output from the write / read selection circuit 9 becomes low level as shown in FIG. 5C, FIG.
Reading of data from the data buffer 2 is stopped as shown in FIG. Next, at the same time when the read enable signal of the write / read selection circuit 9 becomes high level as shown in FIG. 5 (C), the chip selector control circuit 14 causes the chip selector 8 to show the data buffer on the data read side as shown in FIG. 5 (D). When switching to the data buffer 1 as described above, reading of data from the data buffer 1 is started as shown in FIG. 5 (F), and the read data is output to the [B] side via the switch 17.

Next, the chip selector control circuit 13 causes the chip selector circuit 5 to change the write data buffer to the data buffer 1 as shown in FIG. As a result, the input data from the [A] side is written in the data buffer 1 via the switch 16 as shown in FIG. At this time, since data is also read from the data buffer 1 as shown in FIG. 5 (F), writing and reading of data to and from the data buffer 1 are simultaneously performed during the period indicated by B in the figure. become. like this,
The periods in which reading and writing are performed simultaneously for one data buffer are in (b), (c), and (d) of FIGS. 5E and 5F. In such a period, data in the data buffer 1 or the data buffer 2 is Before the data is read, new data may be written by overwriting, the data to be read may be lost, and the newly written data may be read.

[0008]

As described above, the two data buffers are alternately switched for data writing and data reading, and the data writing speed and the data reading speed are different. Therefore, in the conventional data rate conversion device that converts the data rate, the same data buffer may be used for reading and writing data at the same time. If new data is written by overwriting before reading the existing data, the previously written data will be lost and the newly written data will be read instead. I was afraid.

In view of the above, the present invention eliminates the above-mentioned drawbacks and prevents the same data buffer from being simultaneously used for data writing and data reading at any timing, and the data in the data buffer is lost. It is an object of the present invention to provide a highly reliable data rate conversion device that prevents the occurrence of such a problem.

[0010]

According to the present invention, by writing input data to a memory and then reading and outputting the data, the writing speed and the reading speed of the data are different from each other. In a data speed conversion device that converts the speed of input data and output data, 3
A plurality of memories, a write control means for sequentially writing the input data to these memories in a predetermined order, and a memory in which data writing operation is not performed among these memories are selected in order. Read control means for reading data from the stored memory.

[0011]

In the data rate conversion apparatus of the present invention, the write control means writes a plurality of memories of three or more, and the input data in these memories in order in a predetermined order. The read control means sequentially selects the memory in which the data writing operation is not performed among these memories and reads the data from the selected memory.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data rate converter of the present invention. 1, 2 and 3 are data buffers for reading and writing data for converting the transmission speed, 4 is a write side chip selector for switching the switch 16 to select a data buffer for writing, and 5 is a switch for reading by switching the switch 17. Read side chip selectors for selecting the data buffers 6, 7, 8 are data buffers 1,
Address generation circuits for generating read / write addresses for 2, 3 and 9, 9, 10 and 11 for read / write selection circuits for outputting read permission signals / write permission signals to the data buffers 1, 2, 3 and 14 for the chip selector 4 A chip selector control circuit for controlling one of the data buffers 1, 2, and 3 for data writing, and 15 for controlling the chip selector 5 to control one of the data buffers 1, 2, and 3. It is a chip selector control circuit that performs control to select one for data reading.

Next, the operation of this embodiment will be described.
It is assumed that the data input from [A] is subjected to speed conversion by this device and output to the [B] side. The read / write selection circuits 9, 10 and 11 set the write enable signal to the data buffers 1, 2 and 3 to the high level as shown in FIG. The chip selector control circuit 14 is the chip selector 4
2 to switch the terminals 16 in the order of the terminals a, b, c, a ... As the data buffer for writing, as shown in FIG. 2B, the data buffer 1, the data buffer 2, the data buffer 3, the data buffer 1 ... Select in order. As a result, the data input from [A] is sequentially written in the data buffer 1, the data buffer 2, the data buffer 3, the data buffer 1, ... As shown in FIG. The shaded area in FIG. 2 indicates access to the data buffer 1, the white area indicates access to the data buffer 2, and the black area indicates access to the data buffer 3.

On the other hand, read / write selection circuits 9 and 1
As shown in FIG. 2C, 0 and 11 periodically set the read enable signal to the high level to make the data buffers 1, 2, and 3 periodically ready for reading. At the same time, the chip selector control circuit 15 switches the switch 17 in the order of the terminals c, a, b, c, ... Via the read side chip selector 5 to form the read data buffer as shown in FIG. The data buffer 3, the data buffer 1, the data buffer 2, ... Are selected in this order. Therefore, as shown in FIG. 2F, the data is read from the data buffer in the order of the data buffer 3, the data buffer 1, the data buffer 2, the data buffer 3, ... And the read data is passed through the switch 17. Is output to the [B] side.

Here, the writing of data to each data buffer is performed at the address generated by the corresponding address generating circuit in accordance with the write clock WCLK. Data is read from each data buffer by reading the data of the address generated from the corresponding address generation circuit according to the read clock RCLK. That is, the address generation circuit 7 corresponds to the data buffer 1, the address generation circuit 7 corresponds to the data buffer 2, and the address generation circuit 6 corresponds to the data buffer 3. The write / read address is supplied to the corresponding data buffer. Moreover, the above-mentioned write clock WCLK
Since the speed of the read clock RCLK is set to be different, the speed of data when input from [A] is different from the speed of data output from the switch 17 to the [B] side. Data speed conversion is performed.

According to this embodiment, (E) and (F) of FIG.
As shown in, the data buffer in which the data is written and the data buffer in which the data is read are never the same at the same time, so new data is overwritten before reading the data from the data buffer. In principle, there is no possibility that the data to be read will be lost and the data rate conversion can be reliably performed without loss of data.

FIG. 3 is a block diagram showing another embodiment of the present invention. In this example, one data buffer 20 is used, and three memory areas 2 are set in this data buffer.
It is divided into 1, 22, and 23. Moreover, since the respective memory areas 21, 22 and 23 are controlled so that data is read / written independently, they correspond to the data buffers 1, 2 and 3 of the previous embodiment. The read / write selection circuit 11 gives a write enable signal to the data buffer 20 to make this data buffer writable. The address control circuit 16 controls the address generation circuit 6 to generate write addresses, for example, in order from the start address of the memory area 21, and then in the order of the memory area 22, the memory area 23, the memory area 21 ... The write address is supplied to the data buffer 20. Therefore, the data input from [A] is the memory area 21, the memory area 22,
The memory area 23, the memory area 21, ... Are sequentially written in accordance with the write clock WCLK.

On the other hand, the read / write selection circuit 12 makes the data buffer 20 readable at a predetermined interval by giving a read enable signal to the data buffer 20 at a predetermined interval. Along with this, the address control circuit 17 controls the address generation circuit 7 to supply the read address to the data buffer 20 while the read enable signal is output from the read / write selection circuit 12. For example, the address generating circuit 7 is arranged so that the memory area 21, the memory area 22, and the memory area 2 are sequentially arranged from the head address of the memory area 23.
It is assumed that the read addresses of 3 ... Are generated in synchronization with the address enable signal. As a result, the data in the memory area 23 is read in accordance with the read clock RCLK, then the data in the memory area 21, the data in the memory area 22, the data in the memory area 23, and so on. B] side.

In this embodiment, since there are three memory areas for reading and writing data independently, it is possible to prevent one memory area from being used for reading and writing data at the same time, and the same effect as the previous embodiment. There is. Moreover, since only one data buffer is required in this example, the number of constituent parts can be reduced and the apparatus can be made inexpensive as compared with the previous example.

[0020]

As described above, according to the data rate conversion apparatus of the present invention, the same data buffer is prevented from being simultaneously used for data writing and data reading at any timing, and It is possible to improve the reliability of the device by preventing the loss of data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data rate conversion device of the present invention.

FIG. 2 is a time chart explaining the operation of the apparatus shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional data rate conversion device.

5 is a time chart explaining the apparatus shown in FIG.

6 is a diagram showing a usage order of data buffers of the device shown in FIG. 4;

[Explanation of symbols]

 1, 2, 3 ... Data buffers 4, 5 ... Chip selectors 6, 7, 8 ... Address generation circuits 9, 10, 11 ... Read / write selection circuits 14, 15 ... Chip selector control circuits 16, 17 ... Switches

Claims (2)

[Claims] 1. The speed of the input data and the speed of the output data are set by making the speed of writing the data different from the speed of reading the data when the data is read and output after the input data is written in the memory. In a data rate conversion device for converting data, three or more memories, write control means for sequentially writing the input data in these memories in a predetermined order, and data write operation in these memories are performed. And a read control unit for reading data from the selected memories in order. 2. The data rate converter according to claim 1, wherein a plurality of storage areas formed by partitioning one memory are used instead of the plurality of memories in which the data is written and read. ..