JPS58215183A - Character broadcasting receiver - Google Patents

Abstract

PURPOSE:To operate a CPU at a high speed, by operating a character pattern and color data for one line within one horizontal scanning period from a display memory to one line buffer at a high speed with time division to hold a cycle still to be read in synchronization with a display clock. CONSTITUTION:A display memory 13 which stores a character graphic and color information, central processing unit 21 which uses in common the memory 13 by a cycle still method, transfer timing generation means 40, buffers 45 and 46 for speed conversion which are inputted with information read out of the memory 13 by the means 40, and a display timing generation means 9, which transfers the information to a display from the said buffers by reading out the information with a different speed from a transfer input speed to the said buffers, are provided. A time for writing the character graphic information to the buffer 45 is differed from a time for writing the color information to the buffer 46, and the character graphic information out of the buffer 45 and the color information out of the buffer 46 are simultaneously read out as a display data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a teletext receiver capable of receiving teletext using a television receiver.

Information signals such as figures and characters are multiplexed and transmitted within the vertical blanking period of the television signal, thereby making it possible to add broadcast services such as Nice and weather forecasts to regular television broadcasts. A new form of broadcasting,
A so-called teletext system has been proposed.

For example, text broadcasting is described in the 1985 Radio Technology Council Report, Volume 4 (published in May 1988), Chapter 1 [Technical Issues in Television Broadcasting].

According to this report, the teletext signal is time-divisionally transmitted within the vertical blanking period of the television signal. In addition, as stated in page 28 + 5.1.1 Compatibility of the above report, the portion where teletext multiplexing is possible within the vertical blanking period is necessary for synchronization of the television signal. Expansion is possible from the 10th H to the 21st H (in the next field, @27xH to the 284th H) excluding the above part. Furthermore, when using a current television receiver, the locations where teletext multiplexing is possible are from the 16th H to the 21st H (the next field is the 279th H to the 281st H), but the 17th H
, 18th H1, 19th H, and 21st H are already used for the KVIT signal, so in reality, 2 of the 1st +SH and 2nd oH
Teletext broadcasting is only transmitted during the H period. Therefore, the central processing unit (hereinafter referred to as CPU and abbreviated as "f") only had to process for 2H. However, if teletext signals are sent during all 12H periods from 10th to 21st) in the future, y
Considering a', the processing power of the above CPU is insufficient, and 12
An Aro CPU with a processing capacity of H is required. There is a method to increase the operating speed as a means of increasing the processing capacity of the CPU, but the conventional cycle steal display system has the disadvantage that the operating speed cannot be increased as will be described later.

By the way, a conventional teletext receiver has a configuration as shown in FIG.

In Fig. 1, 1 is a tuner for receiving television signals, 2 is an IF circuit, 5 is an Eirin signal detection circuit, and 4
The video amplification/color reproduction circuit 5 is a cathode ray tube, which is the same as that used in an ordinary television receiver. Reference numeral 10 denotes a character signal extraction circuit for extracting a character signal multiplexed on a television signal; 11 a program code for determining whether the program code added to the character signal matches the selected program code inputted from the control circuit 12; This is a discrimination circuit, and if there is a match, the pattern data of the character signal is written into the display memory 13. 14 is a synchronization separation circuit, 15 is an address counter circuit for reading out the contents of the display memory 13 in synchronization with the beam scanning of the cathode ray tube 5, and 16 is for parallel/serial switching of the data in the display memory 13 and for color processing. 17 is a display mode discrimination circuit that discriminates a display mode code added to a character signal; 18 is a display gate setting circuit that sets a display gate signal according to the display mode; , 19 is a signal switching circuit that switches between a television image and a teletext screen using a display gate signal. The display mode discrimination circuit No. 17 discriminates these display mode codes added to the 5-character signal.

Decide whether to display the TV M7 screen, full fixed display of teletext, or super display where the TV M7 screen and teletext screen are mixed. The display gate setting circuit 18 controls the gate range in which the signal of the signal switching circuit 19 is switched in accordance with the display mode determined by the display mode determining circuit 17.

In the signal switching circuit 19, the television video signal from the television video amplification circuit 4 and the character information stored in the display memory 13 are read out by the address counter circuit 15, and are combined by the signal synthesis circuit 16. A character signal and a character signal are input, and by switching between them, the television display and the character signal are displayed permanently.

The character signals are super-displayed on the TV screen.

FIG. 2 is a detailed block diagram of a display circuit composed of the control circuit 121, display memory 13, and address counter 15 shown in FIG. 1, which is realized by the cycle-steal display method of the prior art.

In this figure, 21 is a CPU, 22 is a clock generation circuit 23 that generates a clock signal for the CPU 21, and a clock generation circuit 23 is a data input circuit.
(, AM-24 is a program ROM, 25 is a clock signal path for supplying a clock signal generated from the clock generation circuit 22, 26 is a data bus, 27 is an address bus, and 29 is a synchronization signal of a TV screen signal. Display timing pulse generation circuit that generates address signals for display and display,
32 is an address switching circuit which switches between the address bus 27 and the display timing pulse signal path 50 from the display timing pulse generation circuit 29 by a clock signal supplied from the clock/generation circuit 22 to the clock signal path 25; 33 is an address switching circuit; bus 27 and a color display timing pulse signal path 36 from an address converter 31 that converts the address signal from the display timing pulse generation circuit 29 into a color address signal via a clock signal path 25 from the clock generation circuit 22. 54 is a pattern memory circuit (hereinafter referred to as pattern RAM) that stores character and graphic information in a relative positional relationship with the display screen;
, 65 is a color memory (hereinafter referred to as color RAM) for storing color information of characters and figures, 37 is a pattern RAM 5
38 is a color data latch circuit which temporarily holds the color information from AM35.

The outputs of the parallel-to-serial conversion circuit 57 and the latch circuit 58 are sent to the signal synthesis circuit 16, respectively.

Here, the CPU 21 and the address counter 15 share the display memory 15 in a time-sharing manner using a well-known method known as a cycle steal display method. The cycle steal display method is described, for example, in Japanese Patent Laid-Open No. 53-55491. A feature of this system is that characters and graphics can be displayed stably without requiring any special processing for the CPU 21 to access the pattern RAM 14 and color ILAM 35. That is, period 4 T, period, L (low) during which the level of the clock signal generated by the clock generation circuit 22 is H (〕1 A).
When the period T1 is called the period T1, the data signal from the CPU 21 is the clock signal T1.

Focusing on the fact that it is given and received only during the T1 period, C
TJ force 5-R with PU 21 and butter yRAM s4
Address switching circuit with AM55! 12 and 53, and the display address signal from the display timing noise generation circuit 29 is connected to the care address switching circuit 2 and 53.
In this method, the information is supplied to the pattern TtAM 34 and the color RAM 15 via Y, and the character/graphic information and color information stored therein are read out. As mentioned above, the cycle steal display method allows the display memory 13 to be used efficiently in a time-sharing manner.

However, this cycle steal display method has a drawback in that the operating speed of the CPU 21 is determined by the speed of the address signal from the display timing generating circuit 29. For example, if the frequency of the display pixel is '%' 5.7+MHz, 1! The display memory 13 will be operated at yt output and 5.73 MHz÷8=7115KH2. In this case, the operating speed of the CPU 21 is also the display address signal speed K. <L,
This results in a low speed of 716KHz. If the maximum operating speed of the CPU 21 is set to 1.5 MI (z), only 50% of the capacity of the CPU 21 is used, which is a great waste, and the cycle steal display method using the conventional technology mentioned above is faster than this. to CPU2
Since it is not possible to increase the speed of 1, it has the disadvantage that it is difficult to process a large amount of data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a teletext receiving apparatus using the Yaykl steel display system, which eliminates the drawbacks of the prior art described above and allows the CPU to operate at high speed completely independent of the speed of the display clock.

In order to achieve this objective, the present invention provides a 1-line buffer τ that stores 1 line of character patterns and color data, and stores 1 line of character patterns and color data from the display memory in a time-sharing manner within 1 horizontal scanning period. The configuration is such that high-speed transfer to the above-mentioned 1-line buffer, reading from the above-mentioned 1-line buffer is performed in synchronization with the display clock, and the CPU is operated at high speed by holding the cycle steal. It is characterized by the following.

An embodiment of the present invention will be described below with reference to FIG. Third
The figure is a block diagram showing one embodiment of the present invention. In FIG. 3, circuits that perform the same functions as those in FIG. 2 showing the conventional example are designated by the same numbers.

In FIG. 3, 40 is a clock 41? from the clock generation circuit 22? Transfer timing generation circuit for input -42
is the display It which is the output of the transfer timing generation circuit 4o.
, A switching circuit 43 which switches between the pattern StX selection of AM13 and the address signal for display and the address signal for direct translation of the blank part of AM13 (1 for display, which is the output of the address conversion circuit 31) Display RAM
13 address bus 27 from the CPU 21 as an address signal and a switching circuit 4 as a display address signal.
An address signal path 44 is connected to the output of 2 in a time-division manner by a switching circuit 62; A switching circuit 45 is a pattern data buffer for temporarily storing pattern data, 46 is a color data buffer for temporarily storing color data, and 47 is a pattern data buffer 45 and a color data buffer τ 46. A display timing signal 48 is used to read data at the data display speed that is specified, and four reset words 48 are used to synchronize the display timing signal 47 and the transfer timing generation circuit 40.

The twinkle steel disc brake system shown in FIG. 3 will be explained with reference to FIG. 4. In the conventional technology, one machine cycle period is 1.4AS from the display speed of 716KH2.
It had been decided. The cycle steal display method of the present invention allows you to display memo IJL57 regardless of the display speed of 716KH2! In order to read the display data from + and , the speed of the CPU 21 becomes usable at, for example, t5M)lz. Therefore, in this case, one machine cycle period is 66
7 ns, of which 353.5 ns is used for display reading from the display memory 1!1, and 333.5 ns is used for reading and writing from the MPU. This C
The speed of PU21 is remarkable considering the recent state of device development.

It is now possible to process larger amounts of data.

Next, the operation of the block diagram in FIG. 3 will be explained.

The explanation will be made using the timing chart of FIG. 5 together with this diagram. Since the CPU 21 uses the display RAM 13 in the cycle-steal display method, it can read and read data from the display R and AM 13 without any problem.Therefore, here, the display data can be read out using this cycle-steal display method. Explain the matter.

In the present invention, a buffer for speed conversion is provided, and the Sanno read transfer speed read from the display memory 16 is converted into the actual display transfer speed -\ and displayed. First.

This buff for speed conversion will be explained below.

FIG. 6 is a block diagram showing an example of a speed converting buffer knife. In this figure, 51 and 52 are switching circuits that switch every Z scan period, 53 and 54 are speed conversion buffers T for pattern data, and 55 and 56 are empty parts.
The speed conversion buffer τ, 57.58 is always switched to the opposite speed conversion buffer 777 in response to the switching of 51.52 by a switching circuit. For example, memo 171 for displaying pattern data and color data respectively! Read from l and put 1 into speed conversion back 〒54, 56. At this time, the switching circuits are switched to the 51, 521154, and 56 sides. While the speed conversion packs 〒54 and 56 are loading display data, the speed conversion pack T on the opposite side is loaded.
55. 55 visits the display data written one horizontal period ago at the display speed. Accordingly, the switching circuit 5
7.58 has been switched to the 53.55 side. In the next horizontal period, speed conversion buffers 55 and 55 are used for writing, and speed conversion buffers 54 and 56 are used for reading. speed conversion baku7
Each of screens 53 to 56 requires a capacity sufficient to store display data for a horizontal period.

Above σ) - It is possible to perform speed conversion by switching the two systems for each horizontal period. Figure 7 shows the speed conversion. This is a waveform diagram for explaining the operation of the sofa. be.

As shown in FIG. 5, the display timing generating circuit 9 outputs a reset signal 48 every horizontal scanning period in a predetermined time relationship with the horizontal synchronizing signal in order to synchronize the display timing and the transfer timing. Transfer timing generation circuit 4D
It is reset by the beam sector signal 48 and outputs an address signal necessary for reading out the most important pattern data for one horizontal scanning period. This will be explained using the signal format described on page 22 of the 1985 Radio Technology Council Report No. 4IIWI.

According to this signal format, the pattern data required to display one horizontal scanning period is 31 bytes, so 61 types of address signals are required. An address signal for reading this pattern data is shown in (B). After pattern data reading is completed, the address conversion circuit 61 converts the address signal for pattern data reading into an address signal for color data reading, and in addition to the pattern data reading address signal, 31 is used as a color data reading address signal. The seed address will be output. This waveform diagram is shown in FIG.

(E) is a readout completion signal from the display memory 13, and the display data is read out during the period of (El LOW). As a result, the pattern data and color data are time-divided as shown in (F). Then, the display data read out to the same signal path is read out 51 bytes at a time by the switching circuit 44, and the pattern data is transferred to the pattern data buffer τ45, and the color data is transferred to the color data buffer τ46 by the control signal CD. ) is switched and transferred under the control of CG) is a signal to identify which one of the two buffer systems is being read or one is being read, and it goes H (high) every horizontal period.
, L (low) are exchanged.

This signal controls switching between the transfer buffer τ of 53.55g111 and the transfer buffer 54.56 in FIG. - During the horizontal period, pattern data and color data are written into the transfer buffer by 31 bytes each.

Therefore, 63.57IQ÷(31-+-11)=1.02
One byte must be transferred in 4 μs.

Correspondingly, the CPU 21 must also be operated at 97 sKHz. The written pattern data and color data are read out in parallel during the next horizontal scanning period.

The address signal for this readout is shown in FIG. 5()I) and is switched every 1.4/Is. The address signal has a certain time relationship with the horizontal synchronization signal, so display must be done correctly. FIG. 5(I) is display data that is output after an access time delay from the address signal (1). As described above, in the present invention, it is possible to convert display data from a display memory into a correct time relationship. Therefore, it is possible to realize a cycle steal display system that operates at a high speed regardless of the display speed.

Furthermore, although the above explanation was given for the case where the pattern data is 51 bytes, the present invention can of course be implemented in the case where the pattern data is 51 bytes, depending on the circuit digital configuration. 1 byte transfer time of buffer T 45.46 is 63.5fiS÷(32-1-42
)=0.992 pis (101 MHz) or less. Accordingly, CPU21 is 1.01M1l
Just move it on the z-axis.

According to the present invention, it is possible to use it at a speed that is independent of the CPUY display speed. Therefore, it is suitable for competent data processing.

Also, pattern data and color data are read and extracted in a time-sharing manner, so pattern data) LAM and color data)
(It has the advantage that it can be shared as the same memory as AM. Therefore, there is no need for a separate RAM system, which simplifies the circuit. Furthermore, the address signal path and data signal path can be shared, and only half the wiring is required. This has the effect of giving rise to advantages.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional teletext receiver, Fig. 2 is a block diagram showing details of the main parts in Fig. 1, and Fig. 3 is a main part Y of an embodiment of the present invention. -Block diagram, Figure 4 is a waveform diagram for explaining the principle of the cycle steal method, Figures 5 (A) to (I) are waveform diagrams necessary to explain the circuit operation of Figure 3, and Figure 6 is a waveform diagram for explaining the principle of the cycle steal method. FIG. 7 is a block diagram showing an example of a speed converting back knife, and FIG. 7 is a waveform diagram necessary for explaining the operation of the speed converting banoff T shown in FIG. 40... Transfer timing generation circuit 4 Tochrono signal path 42... Switching circuit 43... Address signal 44... Switching circuit 45... Pattern data back 46... Color data back 47... Display timing signal 48. ... Reset signal agent Patent attorney Susuki 1) Interest Figure 1 + 2 Figure 2 '4' 3 Figure

Claims (1)

[Scope of Claims] 1. A display memory that stores character and graphic information and color information, a central processing unit that shares the display memory using a cycle steal method, and transfer timing generation means; A speed converting buffer to which information read from the display memory is transferred and input, and the information is read out at a speed different from the transfer input speed from the buffer to the buffer T and transferred to the display device. 1. A teletext receiver, characterized in that the teletext receiver comprises: a display timing generating means, which enables the operation speed of the central processing unit to be faster than the display speed of the display device. 2. In the teletext receiver as set forth in claim 1, the speed conversion buffer is composed of seven first buffers for temporarily storing character and graphic information and a second buffer for temporarily storing color information. The character and graphic information is written from the time at which the character and graphic information is written on the first buff page and the color information from the 20th page (t differs from the time at which the character and graphic information is written on the nof page, and the first puff is used as display data). , a teletext receiver characterized in that when color information t is read out from the second buffer 〒, they are read out simultaneously.