JP2002271751A - Display control method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control method and device that decreases number of times of access to a display memory by writing still image data subjected to change to a memory storing display data only when the still image data of a succeeding frame are subjected to change. SOLUTION: Still image data stored in a display memory are compared with still image data of a succeeding frame to discriminate whether or not they are coincident (521), when the discrimination indicates noncoincidence, the display memory stores the still image data of the succeeding frame (522). When the discrimination denotes coincidence, moving image data in the display memory are updated (525).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control method and apparatus capable of combining and displaying a moving image and a still image.

[0002]

2. Description of the Related Art In recent years, the television broadcasting system has been changed from a conventional analog system to a digital system.
Digitalization has also been realized in satellite broadcasting in Japan.

[0003] An advantage of such digital television broadcasting is that it is possible to provide an integrated broadcasting service to which various data broadcasts are added in addition to video and audio broadcasting. Services that add data broadcasting are divided into those that provide multimedia services by adding data information to television programs, and those that provide independent services separate from television programs. For example, there are viewer participation type programs, home shopping, various information services, and weather forecasts and news that can be viewed at any time. Such a data broadcast is mainly composed of still images, and the generation of such broadcast data can use an accelerator technology used for drawing control by a computer. By using a graphic controller with this accelerator technology, processes such as line drawing, rectangle drawing, and data movement in rectangular units are executed by simple commands issued from the main controller, and the results are automatically generated. This is reflected in the display memory, and the load on the main controller is greatly reduced.

[0004]

In such a conventional digital satellite broadcast receiving apparatus, when displaying video information from a video decoding unit for decoding a received television signal and image data from the above-described graphic controller, The input of the video information, the image data from the graphic controller, and the output of the display data to the display device are performed at asynchronous timing. Fig. 24 shows the situation.
(A) to (C) show the timing charts.

FIG. 24A shows output timings of video information (moving images) from the video decoding unit. These output timings are a synchronization signal (vertical synchronization signal (MVSYNC) and a horizontal synchronization signal (MSYNC).
HSYNC)) and a data enable (MENABLE) signal indicating that video information is being output. FIG. 24B shows the output timing of image data (still image) from the graphic controller.
These are synchronization signals (vertical synchronization signal (SVSYNC),
A horizontal synchronization signal (SHSYNC)) and a data enable (SENABLE) indicating that image data is being output.
E) Output together with the signal. FIG. 24C shows the output timing of the display data to the display device. The VSYNC signal as the vertical synchronization signal and the H signal as the horizontal synchronization signal are output.
R, G, and B data are output in synchronization with the SYNC signal.

Since the output timings of these data are generated at different timings, these video information and still picture data are stored in different areas (moving picture / still picture switching plane (moving picture / still picture switching information is stored), moving picture plane, The access to the memory stored in the still image plane is defined as the period of one horizontal scanning period excluding the time required to read the moving image / still image switching information from the moving image / still image switching plane. The time for writing (moving image data) to the moving image plane, the time for writing image data (still image data) to the still image plane, and the display data from the moving image plane and the still image plane for displaying. Must be divided by the time required to read the data.

Here, the display device has a resolution of 720 lines in the vertical direction and 1280 pixels in the horizontal direction, and a horizontal synchronization frequency of 4 lines.
Considering the case of 5 KHz, the period of the HSYNC signal is about 22 μsec. The time required to read the moving image / still image switching information from the moving image / still image switching plane, the time required to write to the moving image plane, the time required to write to the still image plane, the moving image plane and the still image plane, The ratio of the time required to read the display data from is that the moving image / still image switching information is 1-bit data, and that the moving image data and the still image data are Y, CB, and CR (4: 2: 2). If the memory is accessed in units of two pixels,
"1: 32: 32: 32". This means that access to that memory must occur in less than about 11 ns. To achieve this, use a high-speed memory such as a DDR (Double Data Rate) type memory device that transfers data at high speed using both edges of a clock signal, or increase the number of memories. Therefore, it is necessary to take measures such as increasing the amount of data that can be transferred at one time.

The present invention has been made in view of the above-mentioned conventional example, and when the still image data of a frame changes next, the changed still image data is written to a memory storing display data. It is another object of the present invention to provide a display control method and a display control method capable of reducing the number of accesses to the memory.

Another object of the present invention is to reduce the number of accesses to the display memory by updating only the changed line or the pixel data when the still image data of the next frame changes. An object of the present invention is to provide a display control method and an apparatus therefor.

[0010]

In order to achieve the above object, a display control device according to the present invention has the following arrangement.
That is, a display control device capable of synthesizing and displaying a moving image and a still image, a storage unit for storing moving image data and a still image data in different areas, and Access means for reading and updating image data; display means for displaying an image on a display device based on the data accessed by the access means; still image data stored in the storage means; Determining means for comparing the still image data with the still image data to determine whether or not they match, and when the determining means determines that they do not match, the access means stores the still image data of the next frame in the storage. Means to store the moving image data by the access means when it is determined that they match. Characterized in that it has control means for the.

In order to achieve the above object, a display control method according to the present invention includes the following steps. That is, the present invention relates to a display control method for combining and displaying a moving image and a still image. And a display step of displaying an image on a display device based on the data accessed in the access step, and comparing the still image data stored in the memory with the still image data of the next frame. A determination step of determining whether or not they match, and if it is determined in the determination step that they do not match, the still image data of the next frame is stored in the memory in the access step, and the determination is performed. And controlling the moving image data to be updated in the accessing step when it is determined that they match. You.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an entire configuration of a digital satellite broadcast receiving apparatus according to an embodiment of the present invention.

In FIG. 1, a broadcast wave received by a receiving antenna 101 is restored by a demodulation section 102 to a digital signal before modulation processing. The restored digital signal is checked by the error correction unit 103 for data loss or data corruption. If any data abnormality has occurred, the data is restored to correct data. The signal checked by the error correction unit 103 is supplied to the demultiplexing unit 104, where the signal is separated into video, audio, and broadcast data of various data including program information and program configuration information. The audio information among the broadcast materials separated by the demultiplexing unit 104 is decoded into an audio signal before being encoded by the audio decoding unit 105, and is connected to the outside based on the audio signal. An audible sound is reproduced by the speaker 125. The video information is converted into video information before the video information is encoded by the video decoding unit 106. The video information is sent to the video signal synthesis processing unit 108, and is synthesized with the image data output from the graphic controller 114, and then connected to the display unit of the digital satellite broadcast receiving apparatus according to this embodiment or connected to the outside. It is output to the displayed display device 126 and is displayed and reproduced.

Various data information sent as a data broadcast is converted by the data decoding unit 107 into data information before being encoded and passed to the CPU 111. C
The PU 111 issues a command to the graphic controller 114 to generate image data according to the data information from the data decoding unit 107. The graphic controller 114 has an accelerator function, performs processes such as line drawing, rectangle drawing, and data movement in units of rectangles in accordance with commands issued from the CPU 111, and develops the results in the RAM 115. The image data generated by the graphic controller 114 is temporarily stored in the video signal synthesis processing unit 108 together with the video information output from the video decoding unit 106 by the RA.
After being stored in the M109 and subjected to the synthesizing process, it is output to a display unit of the digital satellite broadcast receiving device or a display device 126 connected to the outside to be displayed and reproduced.

A CPU 111 is a main controller for controlling the entire digital satellite broadcast receiving apparatus according to the present embodiment, and is a graphic controller for generating image data such as an electronic program guide from various data information transmitted as data broadcast. It issues instructions to the controller 114,
The information from various input / output devices connected via the O controller 117 is generated as image data, the various input / output devices are controlled via the I / O controller 117, and the video signal synthesis processing unit 108 To set the moving image / still image switching information. The video signal synthesis processing unit 108, the graphic controller 114, or the I / O controller 117 is connected to the CPU 111 via a CPU bus 116 that transmits a control signal and the like of the CPU 111.
Also, a ROM 112 storing a program to be executed by the CPU 111 and a RAM 1 used as a work area
13 is also connected to the CPU 111 via the CPU bus 116.

Reference numeral 110 denotes a clock generator, which is a video signal synthesis processing unit 108 and a graphic controller 114.
As the pixel clock (pixel clock) for
A CLK signal and an SCLK signal as a system clock for the CPU 111 are generated. 117 is I / O
The controller, modem 118 and hard disk (HD
D) 119 is connected and these are controlled. Also I
The / O controller 117 includes an IEEE1394 high-speed serial digital interface, through which various AV (Audio-Visual) devices 120 such as digital video devices and audio devices are connected. Further, an infrared light receiving section 121 for receiving infrared light from a remote controller 122 operated by a user and extracting data included in the infrared light, and a card slot for connecting an IC card 124 containing user authentication information. 12
3 are connected, and control these devices according to instructions from the CPU 111.

FIG. 2 is a block diagram showing a configuration of the graphic controller 114 according to the present embodiment.

In FIG. 2, commands and control information from the CPU 111 are transmitted to the graphic controller 1 via the CPU bus 116 in the form of register set data.
14. Also, register get data by which the CPU 111 can know the state of the graphic controller 114 is transferred from the graphic controller 114 to the CPU 111. Commands and control information issued by the CPU 111 are set in each register of the bus interface unit 1141. The graphic controller 114 is provided with a data manipulator 1142 and a graphics engine 1143 that perform an accelerator function.
1 sets data on the circle and its center and radius in the register of the bus interface unit 1141 and instructs the graphics engine 11 to draw the circle.
43 generates display data of the circle, and the data manipulator 1142 operates the memory interface unit 1
This data is written to the RAM 115 via the 144. The memory interface unit 1144 writes and reads image data to and from the RAM 115 according to the RAM address specified by the data manipulator 1142, and performs refresh driving of the RAM 115. The synchronization control unit 1145 is a block that generates a timing for outputting the image data stored in the RAM 115 to the outside, and according to the timing information set by the CPU 111, a vertical synchronization signal (SVSYNC) and a horizontal synchronization signal input from the outside. (SHSYNC),
Image data is output in accordance with the timing of the data enable signal (SENABLE) and the pixel clock (PCLK). Further, the synchronization control unit 1145 communicates with the RAM 1 via the memory interface unit 1144.
15, the image data is read out and stored in the FIFO 1146. The image data thus stored in the FIFO 1146 is processed in the order in which the image data is stored in the video signal synthesis processing unit 108.
Sent to

FIG. 3 is a block diagram showing a configuration of the video signal synthesis processing unit 108 according to the embodiment of the present invention.

The video information from the video decoding unit 106 is temporarily converted to a display size specified by the CPU 111 by the resolution conversion
1088. The image data from the graphic controller 114 and the moving image / still image switching information set from the CPU 111 via the CPU bus 116 are stored in FIFO 1089 and FIFO 1090, respectively.
Once stored. FIFO1088, FIFO108
9. Data stored in each of the FIFOs 1090 is stored in the RAM 109 via the memory control unit 1082. The RAM 109 stores a moving image plane 1097 for storing video information from the video decoding unit 106, a still image plane 1098 for storing image data from the graphic controller 114, and moving image / still image switching information set by the CPU 111. It is assumed that the video / still image switching plane 1099 is separately managed. Further, the video information from the video decoding unit 106 and the image data from the graphic controller 114 are obtained by converting one pixel data into Y, CB, CR (4: 2:
It is assumed that 16 bits are set in 2), and the 16 bits are sent as 32-bit data in units of two pixels. CPU 11
The moving image / still image switching information set by 1 is 1-bit data. When "1", it indicates the output of the video information from the video decoding unit 106, and when "0", the image from the graphic controller 114 is Indicates the output of the data,
It is set from the CPU 111 in units of 32 bits.

Control of writing and reading of data to and from the RAM 109 is performed by a memory control unit 1082.
When data is written to the RAM 109, data is written in units of 32 bits, and when data is read from the RAM 109, data is written in units of 64 bits. It is assumed that the video information from the video decoding unit 106 and the image data from the graphic controller 114 are read at the same coordinate position in 32-bit units.

The timing controller 1087 generates a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC as timing signals to be displayed on the display device 126 in synchronization with the input PCLK signal, and also generates a line buffer 1091 and a switching mechanism. An ENABLE signal indicating a data output timing is output to 1084. Further, the VS generated by the timing control unit 1087
The YNC signal and the HSYNC signal are also input to the memory control unit 1082, and the memory control unit 1082 reads and writes data from and to the RAM 109 based on these synchronization signals.

Video signal synthesis processing section 1 according to the present embodiment
At 08, a vertical synchronization signal (VSYNC) and a horizontal synchronization signal (HSYNC) as timing signals for displaying on the display device 126 are transmitted to the graphic controller 114.
Are also output as a vertical synchronizing signal (SVSYNC) and a horizontal synchronizing signal (SHSYNC) as a synchronizing signal to the digital camera. Further, an ENABLE signal output from the timing control unit 1087 and indicating a timing of outputting data to the line buffer 1091 and the switching mechanism unit 1084 is also output as a data enable (SENABLE) signal to the graphic controller 114. As a result, the timing at which image data is output from the graphic controller 114 is the same as the timing at which display data is output from the video signal synthesis processing unit 108 to the display device 125.

FIGS. 4A and 4B are timing charts for explaining operation timings in the video signal synthesis processing unit 108 according to the present embodiment. FIG. A diagram for explaining output timing,
FIG. 4B is a timing chart for explaining the output timing of the image data from the graphic controller 114.

In the present embodiment, as shown in FIG. 4A, image data from the graphic controller 114 is output only when an enable (SENABLE) signal is output. That is, the graphic controller 1
14 outputs image data of the same area as the effective display area of the display device 125. Therefore, the image data output from the graphic controller 114 and the display data output from the video signal synthesis processing unit 108 in the horizontal direction And the data amount in the vertical direction is the same.

Returning again to FIG. 3, the comparator 1092 reads out the data from the line buffer 1091 and
Moving picture plane 109 of RAM 109 output to 84
7 and the still image plane 10 of the RAM 109
98, the still image plane 1098
And the image data output from the graphic controller 114 are compared. Thus, it is determined whether the image data stored in the still image plane 1098 of the RAM 109 and the image data newly output from the graphic controller 114 are the same or have changed.

FIG. 5 is a diagram for explaining how the comparator 1092 compares the image data from the still image plane 1098 with the image data output from the graphic controller 114.

When the memory control unit 1082 detects that the HSYNC signal has changed, it first reads one line of moving image / still image switching information from the moving image / still image switching plane 1099 of the RAM 109 (501), and switches it to the switching information. The data is sent to the storage unit 1083 and stored. Next, FIFO
From 1088, the video information from the video decoding unit 106 is read and written to the video plane 1097 (500). After that, the moving picture plane 1097 and the still picture plane 1098
From the display device 1 at the timing of the next HSYNC signal.
The display data to be output to 26 is read and stored in the line buffer 1091. Thus, the line buffer 1091
The display data stored in the timing control unit 1087
(502). Moving image / still image switching plane 1099 in advance
Based on the moving image / still image switching information stored in the switching information storage unit 1083, the switching mechanism unit 1084 determines whether the video information from the video decoding unit 106 or the image data from the graphic controller 114. Either is selected and the format conversion unit 1085
Output to The format conversion unit 1085 converts display data in units of two pixels into data of one pixel and converts 16-bit data of Y, CB, and CR (4: 2: 2) into 8-bit data of R, G, and B each. Convert to image data.
After that, the image data is digital-to-analog converted by the D / A converter 1086 and output to the display device 126.

Further, image data is output from the graphic controller 114 at the same timing as when the display data stored in the line buffer 1091 is read out to the switching mechanism 1084 (503). Therefore, the comparator 1092 compares the image data output from the line buffer 1091 at the same timing with the image data output from the graphic controller 114, and determines whether or not the data match. The result of the match / mismatch determination in the comparator 1092 is stored in the line flag register 1092 of the comparator 1092, which stores a 1-bit determination result in line units.
1 is reflected.

FIG. 6 is a diagram for explaining how the result of the match / mismatch determination is reflected in the line flag register 10921 according to the present embodiment.

In FIG. 6, a display screen 30 composed of data broadcast information is composed mainly of still image data such as characters and figures. In this display screen 30, reference numeral 20 denotes a photographic image. Here, the “region” item 510 in the news column is selected by the viewer's operation of the remote controller 122 (FIG. 1), and its frame is displayed in color. As described above, when the item 510 of “region” is colored, the comparator 1092 detects that the display data of the corresponding line has changed, and the corresponding line (line 300) of the built-in line flag register 10921 is changed.
To 339) are set to “1” indicating that there has been a change.

When detecting that the VSYNC signal has changed, the memory control unit 1082 determines whether or not “1” is set in the line flag register 10921 of the comparator 1092. If there is a line that is set to “1” even for one bit, the next VSY is set.
Until the NC signal changes, the writing to the RAM 109 is not the video information stored in the FIFO 1088, but the image data stored in the FIFO 1089.

FIG. 7 shows a line flag register 10921.
FIG. 11 is a diagram for describing processing by a memory control unit 1082 that selectively writes video information stored in a FIFO 1088 or image data stored in a FIFO 1089 in accordance with the state of FIG.

FIG. 8 is a flowchart showing the flow of display processing in one vertical scanning period in the memory control unit 1082.

In FIG. 7, the VSYNC signal (520)
, The detection result of the still image plane information to be displayed, ie, 1
Line buffer 1 at the timing of the previous frame
A comparison result between the image data from the image controller 091 and the image data from the graphic controller 114 is detected based on the value of the line flag register 10921. As a result, if it is determined that the still image plane information has changed, the still image data sent from the graphic controller 114 and stored in the FIFO 1089 is written to the still image plane 1098 at 522. In this case,
In this one vertical scanning period, the comparator 1092 does not detect whether the still image plane information of the next frame has changed. This is because when the still image plane information is continuously changed, the updating of the moving image plane information is not performed continuously, which hinders the display of the moving image. , The next moving image is surely displayed.

Next, at the timing of the VSYNC signal (523), since no change in the still picture plane information in the previous frame has been detected, at 525, the moving picture plane information stored in the FIFO 1088 is transferred to the moving picture plane 1097 of the RAM 109. Is written to. In parallel, 52
At 4, the comparator 1092 detects whether there is a change in the still image plane information to be displayed next.

If there is no change in the still picture plane information, the moving picture plane information is updated (528) and 527 within the cycle of the next VSYNC signal (526).
As shown by, the comparator 1092 detects whether there is a change in the still image plane information to be displayed next. If it is detected at 524 that the still image plane information has been changed, the still image plane information is updated at 528 and the comparator 1092 at 527 is updated.
, The process of detecting whether there is a change in the still image plane information to be displayed next is omitted.

Next, control processing in the memory control unit 1082 will be described with reference to the flowchart in FIG.

First, when a change in the VSYNC signal is detected in step S101, the process proceeds to step S102, where the comparator 1
It is determined whether or not “1” is set in the line flag register 10921 at 092. If “1” is not set, the process proceeds to step S103, and the RAM 10
The moving image / still image switching information for one line is read from the nine moving image / still image switching plane 1099. Next, in step S104, the video information stored in the FIFO 1088 is read, and the moving image plane 10 of the RAM 109 is read.
Write 97. Then, the process proceeds to step S105, where RA
Moving picture plane 1097 and still picture plane 1 of M109
From 098, display data to be output to the display device 126 at the timing of each HSYNC signal is read, output to the line buffer 1091 and displayed. This process is repeated until the image display of this frame is completed.

If it is determined in step S102 that "1" is set in the line flag register 10921 of the comparator 1092, the flow advances to step S107, and the moving image / still image for one line from the moving image / still image switching plane 1099 of the RAM 109 is processed. Read image switching information. Next, step S
In step 108, the still image information stored in the FIFO 1089 is read and the still image plane 10
Write to 98. Then, the process proceeds to step S109, where RA
Moving picture plane 1097 and still picture plane 1 of M109
From 098, display data to be output to the display device 126 at the timing of each HSYNC signal is read, output to the line buffer 1091 and displayed. This process is repeated until the image display of this frame is completed. Note that the information of the line flag register 10921 is determined when the VSYNC signal changes, that is, when the frame is switched.
It is assumed that it is cleared to “0” by being read by the memory control unit 1082.

FIG. 9 shows a comparator 109 according to this embodiment.
6 is a flowchart for explaining the processing in FIG.

This process is started by the VSYNC signal. First, at step S110, it is checked whether or not the still picture information has been changed in the previous frame. If the still picture information has been changed, the comparator 1092 within the next vertical synchronizing period. No comparison is made.

On the other hand, if the still image information has not been changed in the previous frame in step S110, the process proceeds to step S110.
In step 111, the data from the line buffer 1091 and the graphic controller 1
Compare with data from 14. And step S11
At 2, it is determined whether they match. If they match, the process proceeds to step S114. If they do not match, the process proceeds to step S113 to set the flag information of the non-matching line to "1". And step S11
In step 4, it is checked whether the checking of the line data for all the scanning lines in the frame has been completed. If the checking has not been completed, the process returns to step S111, and the above-described processing is repeated.

As described above, according to the first embodiment, whether or not the image data output from the graphic controller 114 has changed is detected on a line-by-line basis. Decoding unit 10
The image data (still image) output from the graphic controller 114 is written in the RAM 109 instead of the video information (moving image) output from the RAM 6. Thereby, RAM1
As shown in FIG. 5, the access to 09 saves the access time of the display data for one line of the display screen during one horizontal synchronization period.

According to the first embodiment, when the image data (still image data) output from the graphic controller 114 changes, the display based on the video information (moving image data) output from the video decoding unit 106. No update is performed, and only the image data (still image data) output from the graphic controller 114 is updated.
Therefore, when the still image data is frequently updated, the update rate of the video information output from the video decoding unit 106 is reduced by half.

However, if the update rate of one screen is 15 Hz or more, the image can be viewed without any discomfort by the human eye, and the update rate of the video information output from the video decoding unit 106 is 6 Hz.
If the frequency is 0 Hz, even if the image data output from the graphic controller 114 changes continuously, the update rate of the video information output from the video decoding unit 106 can be secured at 30 Hz. It is thought that there are few.

Here, as shown in FIG. 3, a synchronizing signal counter 1093 is provided in the video signal
The number of occurrences of the NC signal is counted by the synchronization signal counter 1093, and when the predetermined number is counted, an OVER signal is issued to the memory control unit 1082. Memory control unit 108
2 is O which is issued from the synchronization signal counter 1093.
When the VER signal is input, the line flag register 10921 of the comparator 1092 is read. As a result, the number of times the update of the video information output from the video decoding unit 106 is skipped is at most the predetermined number or less,
The update rate of the moving image can be further increased.

The display size information processed and output by the resolution conversion processing unit 1081 is stored in the synchronization signal counter 1.
093. Therefore, the synchronization signal counter 10
Reference numeral 93 changes a value for counting the number of occurrences of the VSYNC signal based on the display size information input from the resolution conversion processing unit 1081. Thereby, the video decoding unit 10
6, the update rate of the video information output from the video decoding unit 106 can be changed according to the display size of the video information output from the video decoding unit 6. For example, when the size of the video information to be displayed is small, the update of the video information output from the video decoding unit 106 and the update of the image data output from the graphic controller 114 are performed alternately, and the size of the video information to be displayed is changed. Is larger, the number of updates of the video information output from the video decoder 106 is increased. This enables control to increase the update rate of the video information output from the video decoding unit 106.

[Second Embodiment] In the first embodiment, it is detected that the image data output from the graphic controller 114 has changed, and only when the change is detected, the image data output from the video decoding unit 106 is detected. By writing the image data output from the graphic controller 114 to the RAM 109 instead of the video information
The case where the factors for accessing the RAM 109 are reduced has been described.

On the other hand, in the second embodiment, the RA of the image data output from the graphic controller 114 is
The case where the image data output from the graphic controller 114 is written to the RAM 109 using the blanking period before and after the VSYNC signal without interrupting the writing to the M109 will be described.

Before and after the synchronizing signal output to the display device 126, for example, in a display device such as a CRT that emits light by irradiating a phosphor screen with an electron beam, horizontal scanning is performed from left to right. In such a case, a horizontal retrace period for returning the irradiation of the electron beam to the left end when the scanning reaches the right end is provided. Similarly, in the vertical direction, a vertical blanking period is provided for returning the irradiation of the electron beam to the upper end when the beam scanning reaches the lower end.
In these periods, no display data is output and the display process is not performed, so this is called a blanking period.

In the second embodiment, of the image data output from the graphic controller 114 during the vertical blanking period (V blanking period) which continues over several lines, the image data of the changed line is The case of writing to the RAM 109 will be described. Note that the overall configuration of the device according to the second embodiment is basically the same as the configuration of FIGS. 1 and 3 according to the first embodiment, and a description thereof will be omitted.

FIG. 10 is a block diagram showing a configuration of a graphic controller 114a according to the second embodiment of the present invention. Portions common to the configuration according to the above-described first embodiment are denoted by the same symbols, and description thereof is omitted. I do.

The graphic controller 114a according to the second embodiment outputs image data in synchronization with a synchronization signal (SVSYNC, SHSYNC) and a data enable signal (SENABLE) input from outside. Video signal synthesis processing unit 10 according to
8a (to be described later) is a data enable indicating that image data corresponding to the address information of the RAM 115 specified by the ALINFO signal is output as image data corresponding to the address information specified by the ALINFO signal. It has a function of outputting together with the (RENABLE) signal.

FIGS. 11A and 11B are timing charts for explaining control processing in the graphic controller 114a according to the second embodiment of the present invention. As is apparent from comparison with FIGS. 4A and 4B, in FIG. 11B, it is understood that image data is output together with the data enable (RENABLE) signal even in the vertical blanking period. .

FIG. 11A shows the output timing of display data to the display device 126, and FIG. 11B shows the output timing of image data from the graphic controller 114a according to the second embodiment. I have.

In FIG. 11B, the image data corresponding to the address information of the RAM 115 specified by the ALINFO signal is supplied during the V blanking period.
It is output together with the E signal. That is, the graphic controller 114a operates the ALI at an arbitrary timing.
When the address information is set by the NFO signal, the image data corresponding to the address information specified by the ALINFO signal is transferred to the RAM 11 via the memory interface unit 1144 during the subsequent V blanking period.
5 is read. This image data is stored in FIFO1
After being temporarily stored in the 146, it is output as image data to the video signal synthesis processing unit 108 together with the RENABLE signal.

FIG. 12 is a diagram showing an example of the address information specified by the ALINFO signal.

As shown in FIG. 12, following the start bit (0), the ALINFO signal includes a line designating section (10 bits) indicating the head line of the image data from which the address information is output, and the line designating section (10 bits). The length designation unit (10 bits) for designating the number of lines continuously output from the line designated by the unit, and an end bit (1) indicating the end of the ALINFO signal.
For example, in the example of the display screen shown in FIG.
Since the image data corresponding to 40 lines from the 0th line to the 339th line has been changed, the line designation section includes
"12C" which is a hexadecimal display of the first line "300"
However, "028" which is a hexadecimal display of the number of continuous change lines "40" is set in the length designation portion. The address information composed of these information is P
The video signal is output from the video signal synthesis processing unit 108 in synchronization with the CLK signal.

FIG. 13 is a block diagram showing a configuration of a video signal synthesis processing unit 108a according to Embodiment 2 of the present invention.
Portions common to the configuration according to the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the video signal synthesizing processor 108a according to the second embodiment, the information of the line flag register 10921 of the comparator 1092 is stored in the synchronization signal counter 1093.
The data is read out by the address generation unit 1094 at the timing of the OVER signal output from. If "1" is set in the line flag register 10921, the address information of the corresponding line is output to the graphic controller 114a in the data format shown in FIG. 12 in synchronization with the PCLK signal.

FIG. 14 is a flowchart for explaining processing in the memory control unit 1082a of the video signal synthesis processing unit 108a according to the second embodiment of the present invention.

RAM 10 by memory control unit 1082a
9 is the same as the timing chart shown in FIG. 5 of the first embodiment during a period other than the V blanking.

This processing is first started in step S201 when the memory control unit 1082a detects that the VSYNC signal has changed.
It is determined whether it is a blanking period, and if not, the process proceeds to step S203. Here, one line of moving image / still image switching information is read from the moving image / still image switching plane 1099 of the RAM 109, and the information is stored in the switching information storage unit 1083. Next, the process proceeds to step S204, where the video information (moving image) from the video decoding unit 106 is
The moving image information is read from O1088, and the moving image information is written in the moving image plane 1097. Then, the process proceeds to step S205,
At the timing of each HSYNC signal from the moving picture plane 1097 and the still picture plane 1098, the display device 126
Display data to be output to the line buffer 10
Stored in 91. Thereby, the line buffer 1091
Are transmitted to the display device 126 in synchronization with each horizontal synchronization signal and displayed.

As shown in the flowchart of FIG. 9, image data is output from the graphic controller 114 at the same timing as when the display data stored in the line buffer 1091 is read out to the switching information storage unit 1083. The comparator 1092 makes a comparison in order to check the match / mismatch with the image data from the line buffer 1091 output at the same timing. Then, the result is set in the line flag register 10921 of the comparator 1092.

On the other hand, during the V blanking period of step S202, when it is detected that the HSYNC signal has changed, the process proceeds to step S207, and the video information from the video decoding unit 106 temporarily stored in the FIFO 1088 is transferred to the moving picture plane 1097. Write. However, in this case,
Reading of moving image / still image switching information from the still image switching plane 1099, reading of display data from the moving image plane 1097 and the still image plane 1098, and the graphic controller 114 in the comparator 1092.
Is not compared with the image data output from the line buffer 1091.

In step S208, when the address information is output to the ALINFO signal from the video signal synthesizing processing unit 108a, the graphic controller 114a outputs the image information corresponding to the requested address information together with the RENABLE signal. Memory control unit 1
082a reads out image data (still image) from the graphic controller 114 temporarily stored in the FIFO 1089 while the display data is being read from the moving image plane 1097 and the still image plane 1098, and the information thereof is displayed. Is written to the still image plane 1098 (S209).

FIG. 15 is a timing chart showing the processing timing in this case.

In the figure, the operation timing in the V blanking period is shown. At the timing 531 at which the RENABLE signal is output, the graphic controller 11
Image data for one line output from the RAM 4a is stored in the RAM
It is stored in the corresponding line of the still image plane 1098 (step 530).

As described above, according to the second embodiment, it is detected whether or not the image data output from the graphic controller 114a has changed. If the change has been detected, the vertical data before and after the VSYNC signal is detected. Graphic controller 114 using blanking period
a of one line of image data output from the
9 is written to the corresponding line of the still image plane 1098. As a result, the access to the RAM 109 is performed as shown in FIG.
As shown in (1), the time for accessing one line of display data during one horizontal synchronization period can be saved.

According to the second embodiment, the limited V
During the blanking period, only the image data of the line where the image data has changed is stored in the still image plane 10 of the RAM 109.
If the number of changed lines is large, the RAM 109 is written over a plurality of V blanking periods.
Will be updated.

Therefore, in the video signal synthesizing processing section 108a according to the second embodiment shown in FIG. 13, "1" is set in the address generating section 1094 in the line flag register 10921 read from the comparator 1092. It is also possible to provide a counter for counting the number of operations, and change the processing depending on whether or not the count value counted in the count is equal to or greater than a predetermined value. That is, when the count value is equal to or more than the predetermined value, the same processing as in the first embodiment is performed.

Thus, the graphic controller 1
Even when the number of lines whose display contents have been updated with the image data output from the output terminal 14 exceeds a predetermined value, it is possible to update all the contents of the still image plane 1098 of the RAM 109 in one vertical synchronization period. it can.

[Third Embodiment] In the above-described second embodiment, it is detected that the image data output from the graphic controller 114a has changed in line units, and during the V blanking period, the graphic controller 114a is changed.
In the above description, of the image data output from a, the image data of the line whose content has changed has been written to the RAM 109, thereby reducing the factors for accessing the RAM 109.

Next, in the third embodiment of the present invention, in addition to detecting a change in image data on a line-by-line basis, a change in image data is also detected on a pixel-by-line basis. Then, in addition to the address information of each line, the graphic controller 114a can be designated in the address unit of the changed pixel. Thereby, HS
The image data output from the graphic controller 114a can be written to the RAM 109 using a blanking period before and after the YNC signal.

FIG. 16 is a block diagram showing a configuration of a video signal synthesis processing unit 108b according to Embodiment 3 of the present invention.
Portions common to the configuration according to the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In the video signal synthesizing processing unit 108b according to the third embodiment, the comparator 1092b stores the line flag register 1 indicating the change of the image data in the vertical line unit.
In addition to 0921, a pixel flag register 10922 indicating a change in image data in a horizontal pixel unit is provided. The information of the flag registers 10921 and 10922 is stored in the OV output from the synchronization signal counter 1093.
It is read by the address generation unit 1094 at the timing of the ER signal. If "1" is set in these pieces of information, address information indicating the corresponding line and pixel position is written in the format shown in FIG.
The graphic controller 114 is synchronized with the CLK signal.
Output to a.

FIG. 17 is a diagram showing an example of address information to which information indicating that a change has occurred in a horizontal pixel unit has been added.

In FIG. 17, a line designation section (10 bits) indicating the head line of the image data to be output, and a V length designation for designating the number of lines continuously output from the head line designated by the line designation section Part (10 bits)
In addition to the above, a pixel designation unit (11 bits) indicating the head pixel position of the line, and an H length designation unit designating the number of changed pixels continuously output from the pixel position designated by the pixel designation unit (11 bits).

For example, referring to the example of the display screen shown in FIG. 18, the display contents of 40 lines from 300 lines to 339 lines are changed corresponding to the item “region” 510, and 900 lines in the horizontal direction. The display contents are changed for 360 pixels from pixels to 1259 pixels. In this case, the line designating section stores 16 of the first line “300”.
"12C" which is a hexadecimal display, and "028" which is a hexadecimal display of a continuous line number "40" is stored in the length designation portion. Further, “384” which is a hexadecimal display of the address “900” of the head pixel position is displayed in the pixel designation section, and 1 of the continuous pixel number “360” is displayed in the H length designation section.
“168” which is a hexadecimal display is set.

Further, before and after these pieces of information, a start bit (0) and an end bit (1) indicating the start and end of data are added. An extension bit (0) whose logic is opposite to that of the end bit is added between the V-length designation unit and the pixel designation unit. Thus, on the side receiving the address information, whether the address information ends with only the address information related to the line according to the above-described second embodiment, and further, the horizontal feature which is a feature of the third embodiment, It can be determined whether the address information on the pixel in the direction is also added.

The address information composed of these pieces of information is synchronized with the PCLK signal, and
08b to the graphic controller 114a.

In the video signal synthesizing processing unit 108b according to the third embodiment, the number of pixels that can be written to the RAM 109 during the blanking period before and after the HSYNC signal is set in the address generation unit 1094 in advance. Further, the address generation unit 1094 is provided with a counter that counts how many “1” pixels are set in the pixel flag register 10922 read from the comparator 1092.
The address generation unit 1094 checks whether the number of “1” in the pixel flag register 10922 is within a predetermined value. If so, the address information is added to the address information by adding information about pixels in the horizontal direction. Output information. On the other hand, this pixel flag register 10922
When the number of "1" s set in the address information is larger than a predetermined value, the end bit (1) is added after the V-length designating unit without adding information about pixels in the horizontal direction to the address information. To output address information.

The video signal synthesizing processing unit 108b
When the address information is output as the INFO signal, the graphic controller 114a determines whether or not the information on the horizontal pixels is also added to the address information. When the information about the pixel in the horizontal direction is added, the image data corresponding to the requested address information is stored in the RAM 1 via the memory interface unit 1144 during the blanking period before and after the HSYNC signal.
15 is read. Then, the image data is temporarily stored in the FIFO 1146, and then output as image data together with the RENABLE signal.

On the other hand, when the information about the pixels in the horizontal direction is not added, as described in the second embodiment, it corresponds to the address information requested in units of lines during the V blanking period. The image data is read out from the RAM 115 via the memory interface unit 1144 and temporarily stored in the FIFO 1146.
It is output as image data together with the ABLE signal.

Memory control unit 10 according to the third embodiment
A state in which the RAM 109 is accessed by 82b is shown in a timing chart of FIG. 19, and a flow of processing at that time is shown in a flowchart of FIG.

Here, in one horizontal synchronization period, the RAM 1
In response to the reading of the moving image / still image switching information for one line from the moving image / still image switching plane 1099,
Writing of video information stored in the IFO 1088 to the moving picture plane 1097 and reading of display data from the moving picture plane 1097 and the still picture plane 1098 are performed.
It is assumed that there is enough time for writing to the RAM 109, and the changed image data is written to the RAM 109 using this period.

The RAM 10 by the memory control unit 1082b
9 is accessed by the graphic controller 114a.
When there is no change in the image data output from, the timing chart is the same as the timing chart shown in FIG.

In FIG. 19, when the horizontal synchronizing signal (HSYNC) becomes active at 1900, moving image / still image switching information is read from the moving image / still image switching plane 1099 of the RAM 109 (1901).
The moving image data stored in the IFO 1088 is stored in the RAM 1
09 to the moving picture plane 1097. The line buffer 10 is synchronized with the horizontal synchronization signal (HSYNC).
The reading of the display data from 91 is started (190
5) The display data is output in synchronization with the ENABLE signal (1907). When the ALINFO signal is output from the address generation unit 1094 based on the comparison result of the image data of the previous frame (1908)
In step 1909, the data stored in the RAM 115 is read from the graphic controller 114a in synchronization with the RENABLE signal, and
098 (1903). Then, in 1904, data is read from the moving image plane / still image plane for displaying the next line, and in 1906, the contents of the line buffer 1091 are updated to the display data of the next line.

Next, referring to the flowchart of FIG.
The processing in the memory control unit 1082b will be described.

First, in step S301, when a change in the VSYNC signal is detected, the flow advances to step S302, where HSYNC
When a change in the C signal is detected, one line of moving image / still image switching information is read from the moving image / still image switching plane 1099 to the RAM 109. Next, step S303
Then, the video information stored in the FIFO 1088 is read and written to the moving picture plane 1097. Next, the process proceeds to step S304, where the graphic controller 114
It is determined whether or not the image data is stored in the FIFO 1089 based on the RENABLE signal from the CPU. If it is stored, the process proceeds to step S306,
Image data is read from 089, and the information is written to the still image plane 1098. After step S306 or in step S304, if no image data is stored in the FIFO 1089, the process proceeds to step S305, where the moving image plane 1097 and the still image plane 109
8 and the display device 1 at the timing of the next HSYNC signal.
The display data to be output to 26 is read. Then, the process proceeds to step S307 to check whether the process for one screen has been completed.
The above processing is executed until the display processing for the screen is completed.

In parallel with this processing, the comparator 1092
In b, the comparison between the image data from the line buffer 1091 and the image data from the graphic controller 114a is performed. This process is almost the same as that of FIG. 9 described above. In step S113 of FIG. 9, not only the flag information of the unmatched line is set to “1”, but also the position of the unmatched pixel is determined. This embodiment is different from the above-described embodiment in that the pixel is detected and the position of the pixel flag register 10922 corresponding to the pixel position is set to “1”.

Here, when the number of “1” of the pixel flag register 10922 counted by the address generation unit 1094 is larger than a predetermined value set in advance,
To the graphic controller 114a, address information including information indicating only the unmatched line is output without adding information on the pixel position. Thus, as described in the second embodiment, the graphic controller 114 is utilized by using the V blanking period.
The image data output from a is written into the RAM 109.

Further, when the number of “1” s of the line flag register 10921 counted by the address generation unit 1094 is equal to or more than a predetermined value, as described in the first embodiment, other than during the blanking period. During the valid display data output period, the image data output from the graphic controller 114 is written into the RAM 109 instead of the video information output from the video decoding unit 106.

As described above, according to the third embodiment, a change in image data is detected not only for each line but also for each horizontal pixel in each line, in addition to detecting a change in image data for each line. Is detected and the pixel position is also stored, so that the graphic controller 1
For 14a, the range of the changed image can be specified not only on the line where the image has changed, but also on a pixel-by-pixel basis. Thereby, the transfer time of still image data can be reduced. Furthermore, H
Image data output from the graphic controller 114 can be written to the RAM 109 using a blank time when accessing the RAM 109 during a blanking period before or after a SYNC signal or during one horizontal synchronization period.

[Embodiment 4] In Embodiments 1 to 3 described above, the video signal synthesizing unit detects that the image data output from the graphic controller has changed, and the image data of the changed portion is detected. Only RAM10
9 has been described, the number of factors for accessing the RAM 109 is reduced.

On the other hand, in the fourth embodiment, the graphic controller has information on a portion where the image data has changed compared to the previous frame, so that the video signal synthesizing section can read the information. . Thereby, the video signal synthesis processing unit can know the information of the location where the display content is updated, and can instruct the graphic controller to output only the image data of the location where the display content is updated. The case where the content of the RAM 109 is updated will be described.

FIG. 21 is a block diagram showing a configuration of a graphic controller 114c according to Embodiment 4 of the present invention.

The graphic controller 114c does not output image data sequentially in synchronization with synchronization signals (SVSYNC signal and SHSYNC signal), but outputs address data specified by an ALINFO signal input from the outside. Only when the image data corresponding to the address information is a data enable signal (RENABL)
E signal).

This graphic controller 114c
Generates drawing data using the accelerator function of the graphic controller 114c in accordance with commands and control information set from the CPU 111 via the CPU bus 116. Then, the result is written to the RAM 115 via the memory interface unit 1144. That is, the graphic controller 114c
This means that the position of the data in the display area has been changed.

The graphic controller 114c in the fourth embodiment has a line flag register 1147 that performs the same function as the line flag register 10921 described in the first embodiment.
A memory address for writing image data generated by the data manipulator 1142 into the RAM 115 in accordance with commands and control information set via the CPU bus 116 from the memory interface unit 1144.
Is set to "1" at the position of the line flag register 1147 corresponding to the memory address.

FIG. 22 is a block diagram showing a configuration of a video signal synthesis processing unit 108c according to the fourth embodiment.

The video signal synthesizing section 108c does not have a function of comparing the image data from the still image plane 1098 with the image data output from the graphic controller 114c. Address generation unit 1094
Inputs the information of the line flag register 10921 output from the graphic controller 114c, reads the line flag register information of the graphic controller 114c at the timing of the OVER signal output from the synchronization signal counter 1093, and sets “1”. Judge whether it is. If there is at least one line in which “1” is set, the address information described in the above-described second embodiment is transferred to the AL at an arbitrary timing.
Output to INFO signal.

FIGS. 23A and 23B show Embodiment 4 of the present invention.
23A is a timing chart illustrating operation timings in the video signal synthesis processing unit 108c according to the first embodiment, FIG. 23A is a diagram illustrating output timing of display data to the display device 126, and FIG.
4C is a timing chart illustrating the output timing of the image data from FIG. 4C, showing how the image data corresponding to the address information specified by the ALINFO signal is output together with the RENABLE signal during the V blanking period.

When the address information is set by the ALINFO signal at an arbitrary timing, the graphic controller 114c thereafter sets the AL information in the V blanking period.
The image data corresponding to the address information specified by the INFO signal is output to the output memory interface unit 114.
4 from the RAM 115. Then, after temporarily storing the image data in FIFO 1146, REN
It is output as image data together with the ABLE signal.

In the fourth embodiment, the access to the RAM 109 by the memory control unit 1082 is the same as the operation shown in the flowchart of FIG. 14 of the second embodiment.

It is assumed that the information in the line flag register 1147 of the graphic controller 114c is cleared to "0" by being read by the memory control unit 1082.

As described above, according to the fourth embodiment, it is detected whether or not the image data output from the graphic controller 114c has changed. If the change has been detected, the block before and after the VSYNC signal is detected. Using the ranking period, the graphic controller 114c
Is written into the RAM 109.
As a result, in one horizontal synchronization period, one display screen is displayed.
Access to the RAM 109 for display data for lines can be omitted, and the video signal synthesis processing unit can be simplified.

The present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but it can be applied to a single device (for example, a copying machine, a facsimile machine, etc.). ) May be applied.

Further, an object of the present invention is to supply a storage medium (or a recording medium) in which program codes of software for realizing the functions of the above-described embodiments are recorded to a system or an apparatus, and a computer (or a computer) of the system or the apparatus. This is also achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. When the computer executes the readout program codes, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instructions of the program codes. This also includes a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. , The CPU provided in the function expansion card or the function expansion unit performs part or all of the actual processing,
The case where the function of the above-described embodiment is realized by the processing is also included.

As described above, according to the present embodiment, when an image in which a still image and a moving image are mixed is displayed, only the still image data whose data has changed is written into the memory, thereby achieving one horizontal scanning. It is possible to reduce the number of accesses to the memory occurring during the period. This makes it possible to reduce the cost of the apparatus without requiring a high-speed memory.

[0114]

As described above, according to the present invention, when the still image data of the frame changes next, the changed still image data is written into the memory storing the display data. The number of accesses to the memory can be reduced.

According to the present invention, when the still image data of the next frame changes, the number of accesses to the display memory can be reduced by updating only the changed line or the pixel data. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an entire digital satellite broadcast receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a graphic controller according to Embodiment 1 of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a video signal synthesis processing unit according to Embodiment 1 of the present invention.

FIG. 4 is a timing chart illustrating a state in which image data is output from a graphic controller and a state in which display data is output from a video signal synthesis processing unit according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating R in one horizontal scanning period according to the first embodiment;
6 is a timing chart illustrating access to an AM, a state of a line buffer, and comparison of still image data.

FIG. 6 is a diagram illustrating display data and the contents of a flag register corresponding to a changed portion according to the present embodiment.

FIG. 7 is a timing chart illustrating access from a video signal synthesis processing unit to a memory according to the first embodiment based on a comparison result in a comparator.

FIG. 8 is a flowchart illustrating a process performed by a video signal synthesis processing unit according to the first embodiment.

FIG. 9 is a flowchart illustrating processing in the comparator according to the present embodiment.

FIG. 10 is a block diagram showing a configuration of a graphic controller according to Embodiment 2 of the present invention.

FIG. 11 is a timing chart illustrating a state in which image data is output from a graphic controller and a state in which display data is output from a video signal synthesis processing unit in Embodiment 2 of the present invention.

FIG. 12 is a diagram showing a data configuration of address information according to the second embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a video signal synthesis processing unit according to Embodiment 2.

FIG. 14 is a flowchart illustrating a process performed by a video signal synthesis processing unit according to the second embodiment.

FIG. 15 is a timing chart illustrating access to the RAM during one horizontal scanning period according to the second embodiment.

FIG. 16 is a block diagram illustrating a configuration of a video signal synthesis processing unit according to Embodiment 3 of the present invention.

FIG. 17 is a diagram showing a data configuration of address information according to the third embodiment.

FIG. 18 is a diagram illustrating display data and the contents of a flag register and a pixel flag register according to a changed portion according to the third embodiment.

FIG. 19 is a timing chart illustrating access to a RAM, a state of a line buffer, and comparison of still image data during one horizontal scanning period according to the third embodiment.

FIG. 20 is a flowchart illustrating a process performed by a video signal synthesis processing unit according to the fourth embodiment.

FIG. 21 is a block diagram showing a configuration of a graphic controller according to Embodiment 4 of the present invention.

FIG. 22 is a block diagram illustrating a configuration of a video signal synthesis processing unit according to Embodiment 4.

FIG. 23 is a timing chart illustrating a state in which image data is output from a graphic controller and a state in which display data is output from a video signal synthesis processing unit in Embodiment 4 of the present invention.

FIG. 24 is a timing chart illustrating access of image data to a display memory in a conventional television receiver.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/907 G09G 5/36 520L (72) Inventor Takashi Tsunoda 3- 30-2 Shimomaruko, Ota-ku, Tokyo F term in Canon Inc. (reference) 5C052 AA17 AB04 AC02 CC12 DD04 DD06 5C053 FA06 FA07 FA20 GB15 HA04 HA22 KA01 KA24 LA06 LA07 5C082 AA02 BA02 BA12 BB22 CA55 DA64 EA08 MM02 MM07

Claims (12)

[Claims] 1. A display control device capable of combining and displaying a moving image and a still image, comprising: storage means for storing moving image data and still image data in different areas, respectively; Access means for reading and updating data and still image data, display means for displaying an image on a display device based on the data accessed by the access means, still image data stored in the storage means, Determining means for comparing the still image data of the next frame with the still image data of the next frame to determine whether or not they match; Is stored in the storage means, and when the determination means determines that they match, the moving image data is updated by the access means. And control means for controlling so that,
A display control device comprising: 2. The apparatus according to claim 1, wherein the determination unit compares the still image data of each frame with each other on a line basis to determine whether the still image data of the two frames match. The display control device according to the above. 3. The display control device according to claim 1, wherein the determination unit skips determination processing in a next frame when determining that the two do not match. 4. A comparing means for comparing the still image data of each frame with each other on a line-by-line basis and on a pixel-by-pixel basis on each line; When the determination unit determines that they do not match, the control unit converts the still image data of the next frame by the access unit based on the comparison result held in the holding unit. 2. The display control device according to claim 1, wherein the storage unit stores the image data in units of pixels of a corresponding line. 5. The control means, if it is determined by the determination means that they do not match, in the vertical blanking period for display on the display means, the control means converts the still image data of the next frame by the access means. The display control device according to any one of claims 1 to 4, wherein the display control device is stored in the storage unit. 6. The control means, if it is determined by the determination means that they do not match, in the horizontal blanking period for display on the display means, the access means converts the still image data of the next frame by the access means. The display control device according to any one of claims 1 to 4, wherein the display control device is stored in the storage unit. 7. A display control method for synthesizing and displaying a moving image and a still image, the method comprising accessing a memory storing the moving image data and the still image data in different areas, respectively. An access step of performing reading and updating; a display step of displaying an image on a display device based on the data accessed in the access step; a still image data stored in the memory; and a still image data of a next frame And determining whether or not they match each other, and when it is determined that they do not match in the determining step, the still image data of the next frame is stored in the memory in the accessing step. And controlling the moving image data to be updated in the accessing step when it is determined in the determining step that they match. Display control method according to claim. 8. The method according to claim 7, wherein, in the determining step, the still image data of each frame is compared on a line basis to determine whether the still image data of the two frames match. Display control method described. 9. The display control method according to claim 7, wherein in the determining step, when it is determined that they do not match, the determination process in the next frame is skipped. 10. The comparing step of comparing still image data of each frame with each other on a line basis and on each pixel basis of each line, and a holding step of retaining the comparison results on a line basis and a pixel basis. In the control step, when it is determined that they do not match in the determination step, the still image data of the next frame in the access step is based on the comparison result held in the holding step. 8. The display control method according to claim 7, wherein the memory is stored in the memory in pixel units of a corresponding line. 11. In the control step, if it is determined in the determining step that they do not match, in the vertical blanking period for display in the display step, the still image data of the next frame is accessed in the access step. 11 is stored in the memory.
Display control method described in the section. 12. In the control step, if it is determined in the determining step that they do not match, in the horizontal blanking period for display in the display step, the still image data of the next frame is displayed in the access step. 11 is stored in the memory.
Display control method described in the section.