SU1515400A1 - Device for compressing color signals of tv images - Google Patents

Abstract

The invention relates to a technique for transmitting and storing color images in systems using television displays and video terminals. The purpose of the invention is to increase the compression ratio. The device comprises an A / D converter 1, a reference level setting unit 2, a control unit 6, two comparison units 7, 11, a memory unit 12, a code converter 13. To achieve this goal, a block of 3 elements AND, three registers 4, 5, 10 and two counters 8.9 are entered into the device. When the output of clock and control pulses to the blocks of the device is stopped, it goes from the information reading mode to the channel to the waiting mode for receipt of the frame sync pulse of the next frame. 1 hp f-ly, 2 ill.

Description

sd

ate

(fuel,

315

The invention relates to a technique for transmitting and storing color images in systems using television displays and video terminals and can be used in automated display, data processing and control systems.

The purpose of the invention is to increase the compression ratio.

FIG. 1 shows a structural electrical circuit of the device; in fig. 2 - functional electrical circuit of the control unit.

A device for compressing color signals of television images containing analog-to-digital conversion (lip) 1, block 2 of the installation of the reference background, block 3 of the elements AND, para 4 and second 5 registers, block 6 of the circuit, first block 7 of the comparison, para 8 and the second 9 counters, the third reg istr 10, the second comparison unit 11, the memory block 12 and the code converter 13.

Block 6 (Fig. 2) contains the first trigger 14, the generator 15 clock pulses, the second trigger 16, the first | 17 and the second 18 elements And, the first counter-divider 19, the third element And 20, the first - the fourth line 21 - 24 backset, respectively , the second counter-divider 25, the fifth delay line-26, the first element OR 27, the sixth delay line 28, the third, the counter-divider 29, the second element OR 30, the seventh delay line 31 and the third trigger 32.

The device works as follows.

The input analog signal is fed simultaneously to the inputs of the analog-digital converter 1 and the unit 2 of the reference level setting. In the last stage, a starting pulse is formed, which is fed to the control unit 6, allowing its operation. A parallel code from the output of the A / D converter 1 is fed to the first input of block 3 of elements I, the second input of which receives a control signal from the output of block 6 of control that allows the color code to pass to the information input of the first register 4 when processing the frame and writing instructions to block 12 It also prohibits when reading instructions from memory block 12. Parallel code received on the information input

04

the first register 4 is recorded in it upon arrival at the input of the clock pulse register from the output of the control unit 6. The code from the output of the first register 4 is recorded in the register 5 upon arrival at the input of BTOpoi o of the register 5 of the clock pulse from the output of the control unit 6. Since the clock pulses to the second register 5 arrive with some advance of the clock pulses arriving at the first register 4, the second register 5 records the code corresponding to the previous ry display element, and in the first bbiii register 4 the code corresponding to the last display element . The parallel code from the output of the first register 4 is fed to the input of the first

unit 7 compare 1eni, to the other input of which a parallel code is fed from the output of the second register 5. In the case of a mismatch between the codes on the output of the first unit 7, it is comparable at the time of filing

a clock pulse from the output of control unit 6, a single pulse is generated.

In the initial state, the first pe, gist 4 is reset. By the time the code of the first frame element is written to the first register 4 to the second register 5 from the output of the first register 4, a combination of n zeros is rewritten. When comparing (in the case of a drop in the contents of registers 4 and 5), a single pulse appears at the output of the first comparison unit 7. This signal simultaneously enters the counting input of the second counter 9 and

the zeroing input of the first counter 8. Under the influence of this signal, the second counter 9 changes its state (increases by one), and the first counter 8 is zeroed. Parallel codes from the outputs of the first register 4 (I.) and the first counter 8 (D) are recorded at the address generated by the second counter 9 in the memory unit 12 at the time of receipt of the recording pulse from the output of the control unit 6. In this, the processing of the first display element is completed.

The subsequent code from the output of the A / D converter 1 through block 3 of the elements is And is written to the first register 4 and is compared in block 7 with the previous code rewritten into the second register 5. If the code of the last display element is different from the code of the previous one

51

the display cycle, the processing cycle is similar to that considered. If the codes match, then the output of the first comparison unit 7 sets a potential of zero, with the result that the second counter 9 does not change its state, and the first counter 8 increases its state by one under the action of a pulse from the output of the control unit 6. A new instruction (with a modified one) will be recorded in memory block 12 at the old address.

This algorithm processes all elements of the frame display. After processing the last element of the frame from the output of control unit 6, a write pulse is sent to the input of the third register 10, under the influence of which the maximum address code from the output of the second counter 9 is written to the third register 10. With delay (relative to the signal from the output of control unit 6) The output of block 6 receives a zeroing signal at the second input of the second counter 9 and the third input of the first register A. The second input of the block 3 elements I receives a prohibition signal from the output of control block 6 for the time of reading the information (instructions (I; + D;) from memory block 12. The read resolution information signal from memory block 12 is a pulse arriving at the input of memory block 12 and the second input of code converter 13 from the output of control block 6. This read enable signal is received only after zeroing the second counter 9. Since the second counter 9 is in the zero state, the first (n + p) bit code is read from the memory location with the zero address of the block 12 and is parallel to the first input of the code converter 13. This memory location is used to store the sync code. The output of control unit 6 to the input of converter 13 of the code receives clock pulses providing a sequential shift of information at the third input of converter 13 into (n + p) times the frequency of the read signal fed to the clock input of memory block 12 and the clock input of converter 13 of code.

The first block of comparison 7 compares the zero combination received from the output of the first register 4 and differs from

five

0

4006

from the output of the second register 5, it forms single pulses at its output. These signals are synchronous with the clock pulses from the output of control block 6 to the clock input of the first comparison block 7. The arrival of single pulses from the output of the first comparison unit 7 to the counting input of the second counter 9 provides a sequential search of the memory cells of the memory 12, the information from which is read in the parallel code and fed to the code converter 13. The process of reading information from memory unit 12 and writing it to code converter 13 is ensured by periodically issuing a read enable signal from the output of control unit 6.

By applying clock pulses from the output of the control unit 6 to the input of the code converter 13, sequential transmission of information to the channel is provided. Single pulses from the output of the first comparator unit 7 are also applied to the zero input of the first counter 8, without affecting the reading process. Address codes generated at the output of the second counter 9, in parallel with the arrival at the input of the memory unit 12, arrive at the information input of the third register 10 and the input of the second comparison unit 11.

Due to the absence of a write enable signal at the input of the third register 10, the incoming address codes do not change the maximum address code stored in it. This code comes from the output of the third register 10 to the input of the second comparison unit 11. Upon receipt of the clock pulses from the output of the control unit 6 to the input of the second comparison unit 11, the output of the comparison signal is obtained at the output of the block 11. The maximum address code is compared with the block 12 memory address code.

five

0

five

0

five

0

five

memory, information from which through the converter 13 codes have already entered the channel. This is achieved by the fact that the clock pulses from the output of the control unit 6 to the input of the second comparison unit 11 receive the clock pulses from the output of the control unit 6 to the clock input of the first comparison unit 7. In this way.

the match of the code of the current address with the code of the maximum address will occur after reading from the memory block 12 the last instruction of this code. The result of the coincidence of the current and maximum address codes in the form of a single pulse from the output of the second comparison unit 11 will go to the input of the third register 10, reset it, and simultaneously to the input of the control unit 6. This will stop the output of clock and control pulses to the units of the device. Thus, the device from the information readout mode to the channel enters the waiting mode for the arrival of the frame sync pulse of the next frame.

The control unit 6 operates as follows.

In the initial state, the first 14 and second 16 triggers, the first 19, the second 25, the third 29 counters-dividers, the third trigger 32 are in the zero state. At the moment when the impulse control unit 6 arrives at the output of the reference level setting unit 2, the first trigger 14 switches to the one state. The high level signal from the output of the first trigger 14 is fed to the first input of the first element And 17. Allowing the passage of clock pulses from the generator 15 clock pulses to the output of the first element And 17, from where they arrive at the input of the first counter divider 19. The latter upon receipt (n + p) pulses form at its output a pulse arriving at the input of the third element I 20 and through the first delay line 21 to the output of control unit 6. The first delay line 21 provides the delay necessary to complete the process of writing the codes of the previous and subsequent display elements in the second 5 and first 4 registers. Information is recorded in the first register 4 upon receipt of a signal from the output of the third element I 20 through the fourth delay line 24. The second register 5 receives the recording control signals directly from the output of the third element I 20. During the processing of information entering the input of the proposed device, the presence of signals at the output of the third element I 20 ensures

15

20

25

thirty

35

40

45

50

55

It is supplied by applying to its input a single potential from the output of the second flip-flop 16. This same single potential is fed to the output of the control unit 6. The delay time of the second 22 and third 23 delay lines is longer than the delay time of the first delay line 21. In addition, the delay time of the delay line 23 is longer than the time of the second delay line 22. A second divider counter 25 connected to the output of the third element I 20 divides the input pulse sequence by 2, and then forms a pulse at its output. This pulse is simultaneously fed to the input of the fifth delay line 26, the first input of the first element OR 27, the first input of the second element OR 30 and the first input of the second trigger 16 and is the signal for the end of the image frame cycle. Under the influence of this pulse, the second trigger 16 is switched to a single state. The zero potential from the second output of the second trigger 16 is fed to the output of control unit 6 and to the input of the third element 20, prohibiting the issuing of clock pulses from the outputs of control unit 6. The first element, OR 27, passes a pulse from the output of the second counter-divider 25 to the output of the control block 6 with a delay determined by the delay line 28, ensures that the corresponding blocks are reset at the end of the frame processing cycle. A single potential from the first output of the second trigger 16 permits the issuing of clock pulses from the code of the second element I 18. These pulses go to the output of control unit 6 and to the input of the third counter-divider 29. On receipt of (n + p) clock pulses, the third divider counter 29 at its output it generates a pulse arriving at the second input of the second element OR 30 and at the output of the control unit 6. A single impulse received at the first input of the second element OR 30, from its output will go to the first input of the third trigger 32 and through the seventh delay line 31 to the second input of the same trigger. The third trigger 32 forms a control pulse at the output of control block 6. This impulse provides reading in the channel synch15

rokoda. Subsequently, single pulses arrive at the second input of the second element OR 30, ensuring the operation of the third flip-flop 32 for generating control pulses at the output of the control unit 6. Upon completion of the information read cycle, a single pulse received at the input of control unit 6 will set the first 14 and second 16 triggers to the zero state. In addition, this single impulse goes to the second input of the first element OR 27, ensuring the formation of a zeroing pulse at the output of block 6 of the control unit. Further, the operation of the elements of the control unit 6 is repeated according to the described algorithm.

Claims (2)

1. A device for compressing color images of television images, containing an analog-to-digital converter (ADC) and a unit for mounting foot supports on a level, volume; the input inputs of which are an input device for compressing color signals of television images, a first comparator unit, a memory block , a code converter and a second comparison unit, the output of which is connected to the first input of the control unit, characterized in that, in order to increase the compression ratio, a block of elements I are entered into it, to the first and second inputs of which The output of the LCP and the first output of the control unit are connected, the second, third, fourth, fifth and sixth outputs of which are connected respectively to the clock inputs of the first and second comparison blocks, to the memory input of the memory block, to the combined read inputs of the memory block and the code converter and the clock input of the code converter, to the signal input of which the output of the memory unit is connected, and the output is the output of the device for compressing the color signals of television images, the first register, to the information one, CB and zeroed yuschemu podklyuchvgSh inputs which respectively output the AND block, the seventh and eighth outputs of the control unit, a second register to which the clock and data inputs connected, respectively AOO ° the ninth control unit input: the shadows and the first signal input of the first comparison unit, the first signal input of the memory unit and the output of the first register, the first and second counters and the third register, are connected to the start input, the zeroing input and the information input of which are connected Q deti1 is the output of the control unit, the output of the second comparison unit and the first input of the second comparison unit, the address input of the memory unit and the output of the second counter, to the counting and zeroing inputs of which are connected, respectively, the zero output of the first counter and the output of the first comparison unit to the second control unit output, eleventh output 1-: expensive 0 dinen with the counting input of the first counter, the output of which is connected to the second one. memory input, while the output of the third register is connected to the second input 5 of the comparator unit, the output of the reference level setting unit is connected to the second input of the control unit, the output of the second register is connected to the second signal input of the first unit and compare 0. 2. The device according to claim 1, characterized in that the control unit contains three flip-flops, three AND elements, two OR elements, seven delay lines, three divider counters and a clock pulse generator, whose code is connected to the first input of the first And element, the second input of which is connected to the output of the first trigger, the first input of which is the second input of the control unit, the second input is the first input of the control unit and is connected to the first inputs of the first OR element and the second trigger, to the other input of which the first input is connected the second OR element, the second input of the first OR element, the input of the fifth delay line, the output of which is the fQ tenth output of the control unit, and the output of the second divider counter, the first output of the second trigger is connected to the first input of the second AND element, to the other input of which the output of the first element is And, and the input of the first counter-divider, the output of which is connected to the first input of the third element And and the input of the first delay line, the output of which is 5 five five 11151 with the second output of the control unit, the second output of the second flip-flop is connected to the second output of the third element And is the first output of the control unit, the output of the second element And is the sixth output of the control unit and connected to the input of the third divider counter, the output of which is the third the output of the control unit and connected to the second input of the second OR element, the output of which is connected to the first input of the third flip-flop directly and to the second input through the seventh delay line, and the output of the third flip-flop is O012 the fifth output of the control unit, the output of the third element And is the ninth output of the control unit and is connected to the inputs of the first, second, third and fourth delay lines and the second counter-divider, the output of the first OR element is connected to the input of the sixth delay line, the output of which is the eighth output of the control unit, and the outputs of the second, third, and fourth delay lines are respectively the eleventh, fourth, and seventh outputs of the control unit. g