JPH0292117A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To shorten the corrected result detecting time to meet it even when the number of wirings is a little more by stopping a correcting processing for the data packet and proceeding to a next processing when all '0' are detected even on the way of correcting processing. CONSTITUTION:The corrected result detection to detect whether or not the error correction is normally executed is carried out by seeing the contents of all 82 registers of a syndrome register 16 after the error of respective bits is corrected. Namely, when the error correction is executed correctly for all 272 bits, since the contents are all '0', an all '0' detecting circuit 32 detects whether or not the correcting processing is completed. The all '0' detecting circuit 32 generates the detecting pulse at the time of detecting the all '0', supplies an end signal through an I/O circuit 33 to a CPU 13 and informs that the correction is completed. Thus, the error correcting period can be shortened.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to an error correction circuit used in teletext receivers and the like.

(Prior art) During the horizontal scanning period within the vertical retrace period of a television signal,
A teletext system that superimposes and transmits digital signals has been developed. There are two types of teletext transmission systems: a pattern transmission system and a coded transmission system. In a coded transmission system, an error correction means is used to correct errors in the digital signal.

As an error correction method, for example, there is a method described in the report of the Radio Technology Council, page 4, pages 171 to 190. An error correction circuit using this method will be explained below.

FIG. 3 shows the format of a teletext signal.

One data packet consists of a synchronization section, an information section, and an error correction section. The 16-bit clock line signal (CRI) that constitutes the synchronization section is used to synchronize the phase of the sampling clock for sampling the teletext signal data, and the 8-bit framing code (FC) Byte synchronization is achieved to capture data in units of 8 bits (1 byte). The service m code (Sl/IN) of the information department is a code indicating the 8-bit transmission method, etc., and the packet control code (P
C) is a code indicating continuity of 6-bit data packets. Furthermore, the information section is constituted by a 22-byte data section following the PC. In order to correct errors occurring in this 190-bit information section, an 82-bit error correction section is added after the information section. Check code PO
- By adding the error correction section consisting of P81, it is possible to correct up to 8 bits of code errors that occur in the 272 bits in total of the information section and the error correction section.

FIG. 4 shows a circuit that performs error correction using the above error correction code.

RAM II stores a total of 272 bits of data in the information section and error correction section of one data packet of the received teletext signal, and after the correction operation is completed, the corrected data is stored. Data input/output to RAMII is as follows:
All operations are performed by the CPU 1B and program ROM 12. The uncorrected parallel data in 8-bit units read from the RAM II is converted into serial data D in 1-bit units by the parallel-to-serial conversion shift register 14, and is supplied to the 272-bit shift register. at the same time,
Serial data D is also given to the syndrome register 16. The syndrome register 16 performs syndrome operations on 272-bit data. Depending on the result of the syndrome calculation, the majority circuit 17 determines whether or not to perform correction. Based on this judgment output, the correction circuit 18
The serial data D output from the shift register 15 is corrected. Here, the 272-bit shift register 15 is configured so that the operation result output from the syndrome register 16 is 2
Since it is delayed by 72 bits, it operates as a delay circuit to synchronize the data and the result of this operation. The serial conversion shift register 19 converts the corrected data CD output from the correction circuit 18 into 8-bit parallel data. This parallel data is stored again in RAM II via the CPU 13. Note that the timing generation circuit 20 generates a shift clock 5CLK for the registers 4, 15, 16, and 19 based on the clock CK.

In the above error correction method, 8 out of 272 bits of data
Errors that occur in bits can be detected, but further errors in data cannot be corrected.

Therefore, correction result detection is performed to detect whether the error has been correctly corrected. This can be done by looking at the contents of all 82 registers of the syndrome register 16 after error correction has been performed. That is, if all 272 bits are correctly corrected, their contents will be all "0", and if not, there will be one or more "1". Therefore, the 82-bit syndrome data held in the register 6 is subjected to an OR operation by the OR circuit 21, and the result of the operation is read by the CPU 13 via the I10 circuit 22.

(Problems to be Solved by the Invention) According to the conventional error correction circuit, a syndrome operation for 272 bits is performed, a correction process is performed for the data for 272 bits according to the result, and then the correction is performed successfully. The correction result is detected as to whether or not the error occurred. Here, the correction result is detected by the OR circuit 21 when the contents of the 82-bit register are
Although an OR operation is performed, 82-bit lines are required to be connected between the shift ROM register 16 and the OR circuit 21. However, increasing the number of wires in this way increases the circuit scale when integrated circuits are implemented.

In order to solve this problem, the applicant of the present application has developed a means for reading out the register contents of the syndrome register 6 bit by bit using a clock and performing an OR operation in Japanese Patent Application No. 59-201915. However, when this method is adopted, although the number of wiring lines is reduced, a problem arises in that it takes a long time to finally obtain a correction result.

That is, as shown in FIG. 5, in period (3), syndrome calculation is performed on 272 bits. In period ■, 2
Correction processing is performed bit by bit for 72 bits.

Processing of one bit is performed in synchronization with one cycle of the shift clock generated by the timing generation circuit 20. If the shift clock period is 815 fsc (fsc: color subcarrier 3.579545 MHz, 815 fsc is the period of the character signal transmission bit rate of 175 nsec).
), the time required for ■ is 175 n5ecX
272 = 47.6 μsec, and the same time is required for ■. Therefore, the total time from period ■ to ■ is 952 μS.
It's time for eC.

Next, period (2) requires reading time for 82 bits of the syndrome register. Therefore 175 n5ecX 82= 14.35 μs e
It takes c.

As a result, the total time from period ■ to period ■ is 109
．． It becomes 55 μsec.

When the circuit scale is reduced in this way, there is a problem that the correction result detection time becomes longer, and there is a desire to shorten the time. In particular, in addition to error correction, the CPU in a teletext system is required to perform many data processes such as data acquisition, display memory access, and music data processing. There are circumstances that make it impossible.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction circuit that can shorten the correction result detection time by a commensurate amount even if the number of wiring lines is somewhat large.

[Structure of the Invention] (Means for Solving the Problem) According to the present invention, when correction processing is sequentially performed on each bit of each serial data, the contents of the syndrome register become all "0" when there are no errors. Taking advantage of this, a means is provided to detect all "O's" in the syndrome register, and if all "O's" are detected even during the correction process, the correction process for that pig packet is stopped and the next one is started. This allows you to proceed with the process.

(Function) By using the above means, the shortest correction period, which conventionally required a fixed amount of time, can change the contents of the syndrome register to all “0” by just correcting the first one bit.
Then, the correction process can be completed.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In RAM11,
In one data packet of the received teletext signal, a total of 272 bits of data are stored in the information section and error correction section, and after the correction operation is completed, the corrected data is stored. All data is input to RAMII by the CPU 13 and program ROM 12. Above RAM
The uncorrected parallel data in 8-bit units read from II is converted into serial data D in 1-bit units by parallel-to-serial conversion shift register 4, and is applied to syndrome register 16 via switch 31. The syndrome register 16 performs syndrome operations on 272-bit data. Depending on the result of the syndrome calculation, the majority circuit 17 determines whether or not to perform correction.

Based on this judgment output (correction signal), the correction circuit 18 sequentially corrects the serial data D outputted from the switch 31 bit by bit. That is, the majority circuit 17 divides the syndrome mutators supplied from the syndrome register 16 into 17 predetermined groups, and performs an exclusive OR operation within each group.

If the number of calculation results "1" in the 17 groups is 10 or more, it is determined that there is an error, and the determination output is supplied to the syndrome register 16 and the correction circuit 18. The judgment output is used to correct the serial data D in the correction circuit 18.

Further, this judgment output C is input to the syndrome register 16 when correction processing is performed, and the state of the syndrome register 16 is held. Serial conversion shift register 19
converts the corrected data CD output from the correction circuit 18 into 8-bit parallel data. This parallel data is
It is stored again in RAM II. Note that the timing generation circuit 20 generates a shift clock 5CLK for the registers 14, 16, and 19 based on the clock CK in response to a start pulse from the CPU 13. Further, this timing generation circuit 20 is in charge of the sequence of error correction processing, and outputs read and write timing pulses for the RAM II, atto addresses for the Sarani RAM 11, and control pulses for the switch 31.
This reduces the burden on CPU1B.

If the correction capacity is exceeded, the determination output is, for example, "0", and the data that has passed through the correction circuit 18 is converted into parallel data by the serial/parallel conversion register 19 and stored in RAMII again.

Therefore, correction result detection is performed to detect whether error correction has been performed normally. This can be done by looking at the contents of all 82 registers of the shift 0-m register 16 after each bit has been corrected. That is, if all 272 bits are correctly corrected, the contents will be all "0". As a result, the all "0" detection circuit 32 detects whether or not the correction process has been completed.

The contents of this all “0” detection circuit 32 are as follows:
3, it is added to the second half of the corrected data and the RA
Stored in MII.

According to the embodiment described above, the contents of RAMII are supplied to the syndrome register 16, and a shift ROM operation is performed.
The majority decision circuit 17 obtains a decision output as to whether or not to perform correction, and based on this decision output C, correction is performed bit by bit in the correction circuit. The syndrome register 16 has a shift register 161 and a correction section 162 using an exclusive OR circuit, and output data of the register 161 is supplied to the input of the register 161 through the correction section 162. The judgment output C from the majority circuit 17 is also supplied to the correction section 162, and when the majority judgment circuit 17 judges that there is an error, the judgment signal C becomes "1", and is supplied to the correction section 162 and stored in the register. The output data of 161 is inverted and supplied to the input. If there is no error, the determination signal C becomes 0'', and the output data of the register 161 is supplied to the input without being inverted.

Error correction for teletext broadcasting is based on the majority decision cyclic code (272-190), and when 272 bits of data is passed through the syndrome register 16, if all the data is error-free, after the syndrome calculation period shown in Figure 5 (■) is completed. , the contents of the syndrome register 16 tend to be all "0",
If there is an error in any data, it is corrected during the correction period shown in FIG. 5, and becomes all "0". Therefore, the all "O" detection circuit 32 generates a detection pulse when all "0"s are detected, and supplies an end signal to the CPU 13 via the I10 circuit 33 to notify that the correction has been completed.

Thus, as shown in FIG. 2, the sooner the syndrome data becomes all "0", the shorter the error correction period will be. If all "o"s are not detected, correction processing is performed up to the last bit as in the conventional case, and the contents of the all "0" detection path 32 at that time are added to the end of the output data of the correction circuit 18. , are stored in RAMII via the serial/parallel conversion shift register 19.

As described above, according to the present invention, the correction process can be ended at the same time as the correction of error bits is completed. Therefore, assuming that the first bit at the beginning of the correction period is corrected and there is no data indicating an error in the subsequent bits, the entire correction period will be completed in 48.7 μsec. In the case of teletext broadcasting, error correction is performed up to eight times in one field, so it is possible to reduce the processing time by a maximum of (109,55-48,7)X8, that is, about 487 μsec.

Such an advantage is that the load placed on the pig processing time of the CPU 13 is reduced to that extent, and more time is provided for other processing. In the teletext system, in addition to error correction, processing for capturing incoming pigs, processing for writing and reading image data into display memory,
Much data processing is required, such as music processing (processing to generate music based on music data). When error correction processing takes less time, C
Since the PU 13 has more free space, it becomes possible to shorten the time required to write character image data to the display memory, for example, and it also becomes possible to add other processing functions to enhance the functionality of the receiver.

[Effects of the Invention] As described above, according to the present invention, even if the number of wiring lines is somewhat large, the correction result detection time can be shortened commensurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the operation period of the circuit shown in FIG.
... Majority circuit, 18... Correction circuit, 19... Serial-to-parallel conversion register, 20... Timing generation circuit,
31...Switch, 32...All "0" detection circuit,
33...I10 circuit. The applicant's representative is Takehiko Suzue, a patent attorney. 11...RAM, 12...ROM, 13...CP
U.

Claims (1)

[Claims] A storage means in which data to be corrected is stored, and a syndrome operation is performed on the serial data to be corrected derived by parallel-to-serial conversion of the data in this storage means, a majority vote is obtained from the syndrome data, and each data Syndrome calculation means that sequentially outputs correction signals indicating whether or not bits should be corrected, and whose syndrome is reset depending on the contents of the correction signal to be corrected; , a correction means for correcting the serial data to be corrected bit by bit read from the storage means, and a register content of the syndrome calculation means which is monitored during the correction operation of the correction means and whose contents are all "0". An error correction circuit characterized by comprising means for stopping the correction operation when the error occurs.