JPH11203447A - Decoding device and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decode all encoded signals inputted by simple circuit constitution without increasing the scale of a circuit and complicating control. SOLUTION: An inputted 8-bit encoded signal 100 is converted into a 32-bit signal by a register circuit 1 and stored in a buffer memory 3 through an FIFO 2. When an output request is outputted from a decoder 7, the encoded signal read out from the memory 3 in each 32-bit unit is outputted to the decoder 7 through an FIFO 4 and a selector circuit 5 and decoded by the decoder 7. When the signal 100 is not converted into a 32-bit signal and the residual of the encoded signal stored in the FIFOs 2, 4 and the memory 3 is zero, a residual detection circuit 6 switches the circuit 5 to the side of a terminal B so as to output the encoded signal 100 outputted from the circuit 1 directly to the decoder 7 and decode the signal 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device and method for writing an input coded signal into a buffer memory, reading the coded signal once, and decoding the coded signal with a decoder.

[0002]

2. Description of the Related Art Conventionally, digital signals such as video and audio have been encoded by a method such as MPEG in order to reduce the amount of data. In order to reproduce such an encoded signal, decoding must be performed by a decoding device. For example, there is an "image decoding device" as disclosed in JP-A-8-186822. In this image decoding apparatus, an operation is performed in which bit streams are sequentially stored in a buffer memory, and the stored bit streams are sequentially read and decoded.

Generally, a coded signal input with a certain number of bits is converted into a bit width of a buffer memory, stored in the buffer memory, and then read out from the buffer memory and decoded.

[0004]

As described above, in the conventional decoding apparatus, when the encoded signal is temporarily stored in the buffer memory and then decoded, the encoded signal input with 8 bits is actually used. 16 which is the bit width of the buffer memory.
After conversion into bits or 32 bits, the data is written to the buffer memory, and then read and decoded in the aforementioned units.
However, if the number of bits of the coded signal has a remainder with respect to the bit width of the buffer memory, the coded signal cannot be converted into the above-described predetermined unit. There was a problem that it was not possible.

Therefore, when the number of bits of the coded signal has a remainder with respect to the bit width of the buffer memory, an invalid dummy signal is added to the coded signal so that there is no remainder with respect to the bit width of the buffer memory. After that, the data can be stored in the buffer memory. But in this case,
A flag indicating whether the coded signal stored in the buffer memory is valid or invalid is required, which causes a problem that the circuit scale of the device is increased and control is complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a simple circuit configuration without increasing the circuit scale or complicating the control. An object of the present invention is to provide a decoding device and method capable of decoding all encoded signals.

[0007]

Means for Solving the Problems In order to achieve the above object, a feature of the first invention is that an input coded signal is converted into a predetermined bit unit, and is temporarily stored in a memory. In a decoding device that reads an encoded signal and decodes the encoded signal by a decoder, detecting means for detecting whether or not the input encoded signal has been converted into a predetermined bit unit, Control means for directly outputting to the decoder and decoding the coded signal which has not been converted to the predetermined bit unit without detecting the coded signal which has not been converted to the predetermined bit unit, That is.

According to the first aspect of the invention, when the input coded signal is, for example, 8 bits and only 24 bits are input, it cannot be converted into a predetermined unit of, for example, 32 bits. In such a case, if the 32-bit encoded signal does not remain in the memory or the like, the 24-bit encoded signal is directly sent to the decoder without being stored in the memory to be decoded. As a result, the input coded signals are all decoded.

A feature of the second invention is that the control means adds a dummy signal to a coded signal which has not been converted into a predetermined bit unit, converts the coded signal into a predetermined bit unit, and directly outputs this to the decoder. is there.

A third aspect of the present invention is characterized in that a FIFO circuit for temporarily holding an encoded signal converted into a predetermined bit unit and a FIFO circuit for temporarily holding an encoded signal read from the memory.
O circuit is provided, and when the remaining amount of the coded signal in the FIFO circuit and the memory is all zero and the detecting means detects that the coded signal cannot be converted into a predetermined bit unit The control means is to directly output the coded signal that has not been converted into a predetermined bit unit to the decoder.

According to a fourth aspect of the present invention, there is provided a decoding method for converting an input coded signal into a predetermined bit unit, temporarily storing the coded signal in a memory, reading the coded signal from the memory, and decoding the coded signal. Detecting whether or not the input coded signal has been converted into a predetermined bit unit; and detecting that the input coded signal has not been converted into the predetermined bit unit. And directly outputting to the decoder and decoding the coded signal which has not been converted to the data without storing it in the memory.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first example of the decoding device of the present invention.
FIG. 2 is a block diagram showing an embodiment of the present invention. A register circuit 1 for adjusting the bit width of an 8-bit coded signal 100 to 32 bits is connected to a FIFO (first-in first-out) 2 for temporarily storing a 32-bit coded signal 101, and the coding stored in the FIFO 2 The signal 101 is stored in the buffer memory 3 in units of 32 bits. The encoded signal 101 read from the buffer memory 3 is temporarily stored in the FIFO 4 and then output to the decoder 7 via the selection circuit 5. The selection circuit 5 selects either the output signal of the FIFO 4 or the output signal of the register circuit 1 and outputs the selected signal to the decoder 7. The switching is performed by the FIFO 2, the buffer memory 3, the F
This is performed based on the detection result of the remaining amount detection circuit 6 for detecting the remaining amount of the signal in the IFO 4.

FIG. 2 is a block diagram showing a configuration example of the register circuit 1 shown in FIG. Selection circuits 12, 13, 14, and 15 are provided for selecting an input signal based on the value of a counter circuit 11 that counts up each time a valid flag 200 is input together with the coded signal 100. By multiplexing the encoded signals of the registers 16, 17, 18, and 19 that hold the encoded signals of bits, an encoded signal 101 of 32 bits is generated.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. For example, an encoded signal 100 received from an Internet line is input to the register circuit 1. In step 301, the register circuit 1 holds the input coded signal 100, adjusts its bit width in units of 32 bits, and outputs it to the FIFO 2 when it is determined in step 302 that it has been converted to 32 bits. Hold here. FIFO 2 is buffer memory 3
After the request for writing to the buffer memory 3, the encoded signal 101 is stored until a write permission to the buffer memory 3 is issued.

When a write permission to the buffer memory 3 is issued, the coded signal 101 stored in the FIFO 2 is written to the buffer memory 3 at step 303. When the coded signal 101 is accumulated in the buffer memory 3, reading from the buffer memory 3 is requested, and when permission to read from the buffer memory 3 is issued, the coded signal 101 is read from the buffer memory 3 and stored in the FIFO 4. .

The FIFO 4 takes into account the waiting time from when a read request to the buffer memory 3 is issued to when a read permission is issued, so that the coded signal can be output as soon as an output request from the decoder 7 is received. This is a circuit for reading out the encoded signal 101 from the buffer memory 3 earlier and storing the read-out coded signal 101.

After that, in step 304, the process waits for a request for output of a coded signal from the decoder 7. When the output request is made, the process proceeds to step 305, where the coding stored in the buffer memory 3 is performed. The remaining amount of the signal is determined by the remaining amount detection circuit 6 to determine whether it is zero. If not, the coded signal 101 is read from the FIFO 4 and output to the input terminal A of the selection circuit 5 at step 306.

Normally, the selection circuit 5 selects the input terminal A, and outputs the 32-bit encoded signal 101 input from the input terminal A to the decoder 7. During this time, the remaining amount detection circuit 6 includes the FIFO 2, the buffer memory 3, the FIFO
4 The respective remaining write and read signals are constantly monitored to detect the remaining amount. The remaining amount detection circuit 6 includes a FIFO2,
It is determined that all the remaining amounts of the buffer memory 3 and the FIFO 4 are 0, and the register circuit 1
When receiving the final converted signal that is output when the conversion into the 2-bit coded signal 101 has not been completed, the selection circuit 5 is switched to the input terminal B side.

By the way, the encoded signal 10 in units of 8 bits
If there are only three 0's, for example, and it is determined in step 302 that the coded signal has not been converted in 32-bit units by the register circuit 1, the process proceeds to step 307, in which the output request from the decoder 7 has been made. If not, the process returns to step 301, and if so, the process proceeds to step 308.

In step 308, the remaining amount detecting circuit 6
It is determined whether the remaining amounts of all the coded signals 101 in the FIFO 2, the FIFO 4, and the buffer memory 3 are zero. If not, the process returns to step 301. Switching to the B side, the coded signal 100 not converted to 32 bits is directly output from the register circuit 1 to the decoder 7 for decoding.

At this time, the register circuit 1 adds a dummy signal to the coded signal 100 that has not been converted to 32 bits to make it 32 bits, and directly outputs this to the decoder 7, so that which signal is valid or invalid Is output to the decoder 7.

In the above description, the input coded signal 10
Although 0 is 8 bits and the bit width of the buffer memory 3 is 32 bits, other values may be used as long as the bit width of the buffer memory 3 is larger than the bit width of the coded signal 100.

The selection circuit 5 determines that the remaining amount of the FIFO 2 is zero.
Otherwise, it is sufficient that the input terminal A is selected by the selection signal 300 when the output request from the decoder 7 is received. Further, the selection circuit 5 outputs a coded signal 100 not having 32 bits to the register circuit 1 in which the remaining amounts of the FIFO 2, the buffer memory 3, and the FIFO 4 are all 0.
When there is an output request from the decoder 7 at a certain time,
What is necessary is that the input terminal B is selected by the selection signal 300. Further, the receiving source of the encoded signal 100 is not limited to broadcasting / communication media such as an Internet circuit line.

Next, the operation of the register circuit 1 shown in FIG. 2 will be described. The coded signal 100 is input together with a valid flag 200 indicating whether the input signal is valid. The coded signal 100 is input to the selection circuits 12, 13, 14, and 15, and the valid flag 200 is input to the counter circuit 11. . The counter circuit 11 counts up each time the valid flag 200 is input, and selects the selection signals 51, 52, 53,
54 are sequentially generated, and the selection circuits 12, 13, 14, 1
5 is output.

The selection circuit 12 and the register 16 select the coded signal 100 when the selection signal 51 is valid. When the selection signal 51 is invalid, the previous value held in the register 16 is stored in the register 16. Hold.

Similarly, the selection circuit 13 and the register 17, the selection circuit 14 and the register 18, the selection circuit 15 and the register 1
9 selects the encoded signal 100 when the selection signal 52, the selection signal 53, and the selection signal 54 are valid, and holds the previous value in the register when the selection signals 52, 53, and 54 are invalid. Configure the circuit.

For example, the input order of the coded signal 100 is 1, 2, 3,. . . Then, the 4n-3rd (n =
1, 2, 3...) Are held by the selection circuit 12 and the register 16, and the 4n−2nd input coded signal 100 is held by the selection circuit 13 and the register 17, and 4n The first input coded signal 100 is held by the selection circuit 14 and the register 18, and the 4nth input coded signal 100 is held by the selection circuit 15 and the register 19.

Thereafter, when the signals held in the registers 16, 17, 17, and 19 are multiplexed, an encoded signal 101 converted in units of 32 bits is generated. The above 4n-3, 4n-2, 4n-
1, 4n are mathematical expressions indicating the input order of the coded signal 100 when the coded signal 100 is 8 bits and the bit width of the buffer memory 3 is 32 bits, and is not limited thereto. For example, if the encoded signal 100 is 6 bits and the bit width of the buffer memory 3 is 18 bits, 3n-2,
3n-1, 3n.

Reference numeral 21 denotes a signal generator for generating a converted signal for notifying that the encoded signal 100 cannot be converted into 32 bits from the count value of the counter circuit 11, and this signal is used as the signal generator 6 in FIG. Is output to Reference numeral 22 denotes an encoded signal 1 output from the count value of the counter circuit 1.
It is a flag generator that creates a flag indicating whether the dummy signal of 00 is valid or invalid and outputs it to the decoder 7.

FIG. 4 is a diagram showing a specific signal processing example of the register circuit 1 described above. Input coded signal 1
00 is 8 bits and the bit width of the buffer memory 3 is 32
A pattern in which the number of bits of the input coded signal 100 has a remainder with respect to the bit width of the buffer memory 3 will be described using the case of bits as an example. If the encoded signal 100 is 7
It is assumed that data is input. In the figure, a, b, c, d,
e, f, and g are the values of the input coded signal, and x is an invalid dummy signal.

As shown in FIG. 4A, the valid flag 20
When the values a, b, c, and d of the coded signal are input as shown in FIG. 4B while 0 is “1”, these values are respectively stored in the register 16, the register 17, the register 18, and the register 19. 4 (C), (D), (E), and (F), and when the value d of the encoded signal is stored in the register 4, as shown in FIG. Encoded signal a,
b, c, and d are aligned to the value abcd, and are made into 32 bits.

Next, as shown in FIG.
When the values e, f, and g of 00 are input, these values are similarly stored in the registers 16, 17, and 18 as shown in FIG.
(C), (D), and (E) are stored as shown in FIG.
As shown in (G), the encoded signals e, f, and g have a value of efg and are not converted into 32 bits.

As described above, the input coded signal 100
Is not a multiple of 32, the bit width of the buffer memory 3 has a remainder. However, other values may be used as long as the bit width of the buffer memory 3 is larger than the bit width of the coded signal 100.
For example, the encoded signal 100 may be 4 bits, and the bit width of the buffer memory 3 may be 16 bits. That is, when the number of input bits of the coded signal 100 is not a multiple of the bit width of the buffer memory 3, a remainder is generated with respect to the bit width of the buffer memory 3.

According to the present embodiment, even when the remaining amount of the coded signal held in the buffer memories 3, FIFO2, 4 and the like is zero and the register circuit 1 cannot convert the coded signal 100 into 32 bits, A signal obtained by adding a dummy signal to the coded signal that cannot be converted to 32 bits is directly decoded by the decoder 7.
, And can be decoded. Thereby, even when the number of input bits of the coded signal 100 has a surplus with respect to the bit width of the buffer memory 3, without increasing the circuit scale or complicating the control,
With a simple configuration, all the input coded signals can be decoded by the decoder 7.

FIG. 5 is a block diagram showing a second embodiment of the decoding device of the present invention. However, portions corresponding to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. This example is a configuration example in which the decoder 7 does not request output of an encoded signal to be decoded, and when the number of bits of the input 8-bit encoded signal 100 is not a multiple of the bit width of the buffer memory 3. , 32 bits are not directly added to the coded signal 100 that has not been converted to 32 bits, and are directly output to the decoder 7 as they are.

When the input coded signal 100 is converted into 32 bits, the register circuit 1 writes it into the buffer memory 3 via the FIFO 2. Also in this example, normally, the selection circuit 5 is switched to the terminal A side, and the buffer memories 3 to 3
The encoded signal 101 read in units of 2 bits is
O4, output to the decoder 7 via the selection circuit 5, where it is decoded.

On the other hand, the input coded signal 100 is not converted into 32 bits by the register circuit 1, and the remaining amount detection circuit 6
When it is detected that the remaining amounts of all the signals in the FIFO 2, the buffer memory 3, and the FIFO 4 are zero, the selection circuit 5 outputs the signal to the terminal B
The coded signal 100 that has not been converted into 32 bits from the register circuit 1 is output directly to the decoder 7 via the selection circuit 5 and decoded there.

It is assumed that the 32-bit coded signal 100 directly output from the register circuit 1 to the decoder 7 does not have a dummy signal added thereto, and the decoder 7 outputs the 32-bit coded signal 100 Simply decrypts

This embodiment has the same effect as that of the first embodiment shown in FIG. 1, except that the decoder 7 does not request the output of the coded signal, or the output from the register circuit 1 Since the dummy signal is not added to the coded signal 100 that has not been converted into 32 bits, the configuration can be simplified as compared with the first embodiment.

[0040]

As described above in detail, according to the decoding apparatus and method of the present invention, all codes inputted with a simple circuit configuration can be obtained without increasing the circuit scale or complicating the control. The decoded signal can be decoded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a decoding device of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a register circuit illustrated in FIG. 1;

FIG. 3 is a flowchart showing an operation procedure of the apparatus shown in FIG. 1;

FIG. 4 is a diagram illustrating a specific operation example of the register circuit shown in FIGS. 1 and 2;

FIG. 5 is a block diagram showing a second embodiment of the decoding device of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 register circuit 2, 4 FIFO 3 buffer memory 5, 12 to 15 selection circuit 6 remaining amount detection circuit 7 decoder 11 counter circuit 16 to 19 register 21 signal generation unit 22 flag generator

Claims (4)

[Claims] 1. A decoding device for converting an input coded signal into a predetermined bit unit, temporarily storing the coded signal in a memory, reading the coded signal from the memory, and decoding the coded signal by a decoder. Detecting means for detecting whether or not the coded signal has been converted into a predetermined bit unit; and converting the coded signal into a predetermined bit unit when the detecting means detects that the coded signal has not been converted into the predetermined bit unit. Control means for directly outputting the unencoded coded signal to the decoder without storing the coded signal in the memory, and decoding the decoded signal. 2. The apparatus according to claim 1, wherein said control means adds a dummy signal to the coded signal which has not been converted into a predetermined bit unit, converts the coded signal into a predetermined bit unit, and directly outputs this to the decoder. The decoding device according to any one of the preceding claims. 3. An FIFO circuit for temporarily holding an encoded signal converted in a predetermined bit unit, and an F for temporarily holding an encoded signal read from the memory.
An IFO circuit is provided, and when the remaining amount of the coded signal in the FIFO circuit and the memory is all zero and the detecting means detects that the coded signal cannot be converted into a predetermined bit unit 3. The decoding apparatus according to claim 1, wherein said control means directly outputs an encoded signal which has not been converted into a predetermined bit unit to said decoder. 4. A decoding method for converting an input coded signal into a predetermined bit unit, temporarily storing the coded signal in a memory, reading the coded signal from the memory, and decoding the coded signal. A step of detecting that the signal has not been converted to the predetermined bit unit, and a step of detecting that the input coded signal has not been converted to the predetermined bit unit. And directly decoding the decoded signal without storing it in the memory.