JP3116968B2 - Digital video signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing apparatus suitable for application to a device which receives a digital video signal.

[0002]

2. Description of the Related Art FIG. 3 shows an example of the configuration of a video system. In FIG. 1, reference numeral 10 denotes a digital VTR, and a digital video signal reproduced by the digital VTR 10 is an image processing device 20 for performing special effect processing.
Supplied to The digital video signal output after being subjected to the special effect processing by the image processing device 20 is output to the monitor 30.
, And the image on which the special effect has been applied is displayed.
In this case, the digital VTR 10, the image processing device 20,
The monitor 30 is supplied with a reference synchronization signal Sref, and is configured to operate in synchronization with the reference synchronization signal Sref.

Here, for example, the input stage of the image processing device 20 corrects a jitter in the digital VTR 10 and a delay due to a cable from the digital VTR 10 to the image processing device 20 and outputs a digital video signal synchronized with the reference synchronization signal Sref. A processing device for obtaining is provided.

FIG. 4 shows an example of the configuration of a digital video signal processing device. In FIG. 1, a digital video signal DSV is supplied to a memory 1 as a write signal.

The digital video signal DSV is supplied to a synchronization detection circuit 2. The synchronization detecting circuit 2 detects a synchronization pattern from the digital video signal DSV.

Here, the synchronization pattern of the digital video signal DSV will be described. FIG. 5 shows the data format of a digital video signal of the D-1 (component) system. Each digital video signal is composed of 8-bit luminance data and color difference data.

The digital line is 2200T (T is 13.5 nsec in clock cycle), the digital horizontal blanking is 280T, and the digital active line is 1920T.

A timing reference signal is provided at the beginning and end of each video data block (1928T) of luminance data and color difference data. That is, initially, SAV (St
artof Active Video) and EAV (End of A)
ctive Video) is placed.

Each timing reference signal is composed of a 4-word string "FF 00 00 XY". Each timing reference signal is defined as an 8-bit word. First three
The word "FF 00 00" is a fixed preamble. The fourth word “XY” defines the field status and indicates the timing of vertical and horizontal blanking (see FIG. 6). F defines the field status, which is “0” in the field 1 section and “1” in the field 2 section. V defines the timing of vertical blanking. It becomes "1" in the vertical blanking interval. H defines the timing of horizontal blanking.
It becomes "1" at the start of horizontal blanking.

In the fourth word, P0 to P3 are:
This is a redundant bit, and is used to correct transmission errors in F, V, and H when they occur. These P0
To P3 are generated as shown in FIG.

Returning to FIG. 4, the synchronization detection circuit 2 detects a fixed preamble as a synchronization signal from the digital video signal DSV.
Supplied to The memory controller 3 is also supplied with a reference synchronization signal Sref.

The memory 1 is controlled by the memory controller 3.
Writing and reading are controlled. That is, the data of the digital active line is written into the memory 1 in synchronization with the detection signal output from the synchronization detection circuit 2 and read out in synchronization with the reference synchronization signal Sref.
As a result, the memory 1 corrects the jitter in the digital VTR 10, the delay due to the cable, etc., and outputs a digital video signal DSV 'synchronized with the reference synchronizing signal Sref, which is supplied to the next-stage processing circuit.

[0013]

By the way, in the example of FIG. 4, some noise may be mixed into the digital video signal DSV on the transmission path. When a signal having the same pattern as that of the fixed preamble is generated due to the contamination of noise, the signal is detected by the synchronization detection circuit 2 as a synchronization signal. Therefore, the digital video signal DSV is written into the memory 1 at an incorrect timing, and is output to the output screen. Has a negative effect.

Accordingly, the present invention is intended to reduce the adverse effect on the output screen when a synchronization signal is erroneously detected.

[0015]

According to a first aspect of the present invention, a synchronous pattern is detected from a digital video signal, a digital video signal is written to a memory in synchronization with the synchronization detection signal, and the memory is synchronized with a reference synchronization signal. In a digital video signal processing apparatus for reading out a digital video signal, an error discriminating means for discriminating the presence or absence of an error is provided from an error detection code added in relation to a synchronization pattern position, and the error discriminating means determines that there is an error. At times, the writing of the digital video signal to the memory in synchronism with the synchronization detection signal is prohibited.

According to a second aspect of the present invention, a synchronization pattern is detected from a digital video signal, a digital video signal is written to a memory in synchronization with the synchronization detection signal, and a digital video signal is read from the memory in synchronization with a reference synchronization signal. In the digital video signal processing device, a time difference discriminating means for discriminating a time difference between the synchronization detection signal and the reference synchronization signal is provided, and when the time difference discriminating means determines that the time difference is other than the predetermined value, the digital video signal processing device is synchronized with the synchronization detection signal. This is to prohibit the writing of the digital video signal to the memory.

[0017]

For example, in the digital video signal of the D-1 system, error detection codes P0 to P3 are added to the timing reference signal (see FIG. 6). If the synchronization signal is erroneously detected due to noise, the formal error detection code P0
Since the presence or absence of an error is not determined in P3, it is determined that there is almost an error. Therefore, in the first invention, when the synchronization signal is erroneously detected, the digital video signal is not written in the memory 5, and the digital video signal of the previous line is output from the memory 5. Thus, when a synchronization signal is erroneously detected, adverse effects on the output screen are reduced.

If a synchronization signal is erroneously detected due to noise, the synchronization detection signal Sdet and the reference synchronization signal Sdet are detected.
The time difference of ref changes greatly. Therefore, in the second invention, when the synchronization signal is erroneously detected, the digital video signal is not written into the memory 5, and
Outputs the digital video signal of the previous line.
Thus, when a synchronization signal is erroneously detected, adverse effects on the output screen are reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, a digital video signal DSV
Is supplied as a write signal to the time axis adjusting memory 5 via the delay circuit 4. The delay circuit 4 is for compensating for a delay such as a synchronization detection operation in the synchronization detection circuit 6.

The digital video signal DSV is supplied to a synchronization detection circuit 6. This digital video signal DSV
Are the same as in FIG. 4 (see FIG. 5).

The synchronization detection circuit 6 detects a fixed preamble of the timing reference signal as a synchronization signal, and the synchronization detection signal Sdet is supplied to the time comparison circuit 7 and the memory controller 8. The reference synchronization signal Sref is also supplied to the time comparison circuit 7 and the memory controller 8.

In the time comparison circuit 7, the reference synchronization signal Sref
Is used, the synchronization detection signal Sdet from the synchronization detection circuit 6 is used.
Is measured and stored (see FIG. 2). Once stored, it is not updated unless the same time difference occurs twice in a row. This time comparison circuit 7
Then, the measured time difference is compared with the stored time difference, and when the difference is within a predetermined range, a signal indicating that the time difference is normal is output. Is output.

In this case, the range is set to be larger than, for example, the time variation due to the jitter of the device, so that a signal indicating an abnormality due to the time variation due to the jitter is not output. The output signal D of the time comparison circuit 7
tm is supplied to the memory controller 8.

When the synchronization signal is detected by the synchronization detection circuit 6, the error discriminating section 9 in the synchronization detection circuit 6 generates error detection codes P0 to P3 added to the timing reference signal.
Is used to determine the presence or absence of an error. The error determination signal Der output from the error determination unit 9 is supplied to the memory controller 8.

The writing and reading of the memory 5 are controlled by the memory controller 8. When the output signal Dtm of the time comparison circuit 7 indicates that it is normal and the error determination signal Der output from the error determination unit 9 indicates that there is no error, the memory controller 8 sends the error signal to the memory 5. Is supplied with a write reset pulse WR formed based on the synchronization detection signal Sdet and a write enable signal WE. Therefore, the digital video signal DSV is written to the memory 5 in synchronization with the synchronization detection signal Sdet, and the data in the memory 5 is sequentially updated. Further, a read reset pulse RD formed based on the reference synchronization signal Sref is supplied from the memory controller 8 to the memory 5, and the digital video synchronized with the reference synchronization signal Sref and time-axis corrected from the memory 5 is supplied from the memory 5. Signal DSV 'is output.

On the other hand, if the output signal Dtm of the time comparison circuit 7 indicates that there is an abnormality, or if the error determination signal Der output from the error determination unit 9 indicates that there is an error, the write reset is performed. The pulse WR and the write enable signal WE are masked, they are not supplied from the memory controller 8 to the memory 5, and the data in the memory 5 is not updated. The read reset pulse RD is supplied to the memory 5 as usual. Therefore, at this time, the signal one line before the memory 5 is output as the digital video signal DSV '.

In this example, when noise is mixed on the transmission path and a synchronization signal is erroneously detected, the error discriminating section 9
Since the presence or absence of an error is not determined by the formal error detection codes P0 to P3, it is determined that there is almost an error. Even when it is determined that there is no error, the synchronization detection signal S
The time difference between det and the reference synchronization signal Sref greatly changes.

Therefore, the error discrimination signal Der from the error discrimination section 9 indicates that there is an error, or that the output signal Dtm of the time comparison circuit 7 is abnormal.
As a result, it is prohibited to write the digital video signal DSV into the memory 5 in synchronization with the synchronization detection signal Sdet,
The signal of the previous line is output from the memory 5.

Therefore, even if a synchronization signal is erroneously detected, an erroneous line with a position shift does not occur on the output screen, and the adverse effect on the output screen can be reduced.

[0031]

According to the present invention, when it is determined that there is an error by the error detection code added in relation to the position of the synchronization pattern, or when the time difference between the synchronization detection signal and the reference synchronization signal is other than a predetermined value. In this case, the writing of the digital video signal to the memory in synchronism with the synchronization detection signal is prohibited, and the signal of the previous line is output from the memory. Therefore, even if a synchronization signal is erroneously detected, an erroneous line with a position shift does not occur on the output screen, and adverse effects on the output screen can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a diagram for explaining a time difference measurement in a time comparison circuit.

FIG. 3 is a block diagram illustrating an example of a video system.

FIG. 4 is a block diagram of a digital video signal processing device.

FIG. 5 is a diagram illustrating an example of a data format of a digital video signal.

FIG. 6 is a diagram showing a timing reference signal of a digital video signal.

FIG. 7 is a diagram illustrating generation of codes P0 to P3.

[Explanation of symbols]

 Reference Signs List 4 delay circuit 5 memory 6 synchronization detection circuit 7 time comparison circuit 8 memory controller 9 error discrimination unit 10 digital VTR 20 image processing device 30 monitor

Claims (2)

(57) [Claims] 1. A digital pattern which detects a synchronization pattern from a digital video signal, writes the digital video signal into a memory in synchronization with the synchronization detection signal, and reads the digital video signal from the memory in synchronization with a reference synchronization signal. In the video signal processing device, an error discriminating means for discriminating the presence or absence of an error from the error detection code added in relation to the synchronization pattern position is provided, and when the error discriminating means determines that there is an error,
A digital video signal processing device for inhibiting writing of the digital video signal into the memory in synchronization with the synchronization detection signal. 2. A digital signal detecting a synchronization pattern from a digital video signal, writing the digital video signal into a memory in synchronization with the synchronization detection signal, and reading the digital video signal from the memory in synchronization with a reference synchronization signal. In the video signal processing device, a time difference determining means for determining a time difference between the synchronization detection signal and the reference synchronization signal is provided. When the time difference determination means determines that the time difference is not a predetermined value, the video signal processing device synchronizes with the synchronization detection signal. A digital video signal processing device for prohibiting the writing of the digital video signal into the memory.