KR970078193A - Descrambler with clock compensation - Google Patents

Abstract

In a conventional digital video disk (DVD), when input data is scrambled after a certain sync signal is generated, when data on the disk is read due to scratches on the disk or external noise and current fluctuation, errors are mixed on the data, The locking is sequentially disturbed in the PLL circuit which extracts the clock from the data. Therefore, the number of clocks for the data is different, and therefore, when the error correction is performed by descrambling the data synchronously, There is a disadvantage that an error due to a missing signal or a fluctuation of a reference clock is transmitted and errors are accumulated continuously.

In order to solve this problem, the present invention provides a disk RAM block having a clock compensation function so that an error is not transmitted or accumulated even if an error occurs due to a change in a synchronizing signal input from the outside or a reference clock, The error can be prevented from being accumulated due to the error.

Description

Descrambler with clock compensation

Since this is a trivial issue, I did not include the contents of the text.

FIG. 1 is a configuration diagram of a descrambler system having a clock compensation function for the present invention, FIG. 2 is a detailed configuration diagram of a write control unit in the present invention, and FIG. 3 is a detailed configuration diagram of a read control unit in the present invention.

Claims (3)

A write control unit for generating a control signal for data to be read by writing all necessary data to be input to the memory unit in accordance with the synchronization signal input; And a read control unit configured to output a reference clock of data that is faster than a write clock even if a change in a reference clock of an input PLL occurs, thereby preventing propagation of an error. The apparatus of claim 1, wherein the write control unit comprises: a synchronization signal detection unit for loading a start address according to a synchronization signal input or initializing each control signal to detect a synchronization signal; A timing generator for generating timing signals necessary for each part; An address generator for generating a pre-initialized address for byte descrambling; A control signal generator for generating a control signal to record a necessary amount of data in the memory unit or to read data recorded in the memory unit; And a data output interface unit for controlling a clock of input data to be synchronized with an address and a memory control signal. The apparatus of claim 1, wherein the read control unit comprises: a control signal generator for setting an initial address value or controlling address generation according to a read control signal input to the address generator; An address generating unit for generating an address required for each mode according to a set address initial value; A timing generator for generating a timing signal necessary for each part according to a reference clock; A data output interface unit for outputting data read out from the memory unit in synchronization with a clock; And a synchronization signal generator for generating a synchronization signal at every cycle by calculating a timing. ※ Note: It is disclosed by the contents of the first application.