WO1986007181A1

WO1986007181A1 - Method and apparatus for processing data

Info

Publication number: WO1986007181A1
Application number: PCT/JP1986/000260
Authority: WO
Inventors: Hiroshi Ogawa
Original assignee: Sony Corporation
Priority date: 1985-05-31
Filing date: 1986-05-22
Publication date: 1986-12-04
Also published as: JPS61276176A; AU5908286A

Abstract

A method and an apparatus for processing data, in which a disk having synchronizing signals recorded in front of and at the back of each data block, is reproduced to detect defective portions in the reproduced data, a position of the synchronizing signal at the back of said data block is detected to find a difference between the bit length of said data block and the position of the synchronizing signal at the back thereof, and the order of data arrangement in the reproduced data after the defective portion is deviated by an amount that corresponds to the above-mentioned difference. This helps to prevent the data from being lost in large amounts owing to the cycle slip error.

Description

Description Data processing method and device

The present invention relates to a data processing method and apparatus used for a disc reproducing apparatus on which digital data is recorded.

Background art

2. Description of the Related Art A recording / reproducing apparatus using an optical disc on which digital data is recorded is generally provided with a function of correcting data errors during reproduction. This error correction function can correct data errors due to signal up-and-down noise during a certain period. In the case of a disc used for a computer, etc., one frame of data can be corrected. A synchronization signal is recorded at the head of the tab block, and between the end of the data block and the synchronization signal of the next data block, for example.

A relatively long gap of about 3 bytes is formed. This gap is provided to absorb rotation fluctuations due to disk eccentricity and the like.

The error correction function described above can correct errors within a certain period of time, but it does correct the cycle slipperer generated by continuous dropout noise over a long period of time. Is impossible at all. Cycle slip errors are caused by the fact that the number of clocks extracted during one frame period changes from a specified number due to continuous dropout noise over a long period of time. appear. In other words, if the number of clocks changes, the address indicated by the number of clocks in the RAM to which the reproduced data is written is out of order, and All data after the portion where the defect occurred during the program period becomes invalid.

Disclosure of the invention

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a data processing method and apparatus capable of correcting a cycle slip error based on a signal defect over a long period of time. .

The data processing method and apparatus according to the present invention reproduces a disk on which a signal in which a synchronization signal is provided at both ends of a data block is recorded, detects a defective portion of the reproduced data, and detects the data block. The position of the synchronization signal provided at the back of the block is detected, and the difference signal between the bit length of the data block and the synchronization signal at the back is obtained. The arrangement order of the data is shifted by an amount corresponding to the difference signal. By doing so, it is possible to correct the cycle slip error after the defective portion of the reproduction data, and to reduce the amount of data lost due to the error.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of a data format applicable to the present invention.

FIG. 3 is a timing chart for explaining the operation of FIG.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 2 shows an embodiment of a data format recorded on a disc applicable to the present invention.

In FIG. 2, an a-bit pre-synchronization signal PRD having a predetermined bit pattern is recorded at the beginning of one frame of data, and then n A bit data block is recorded. At the end, a synchronization signal P 0 D is recorded after b bits having a predetermined bit pattern. In other words, a one-frame data block is recorded with its front and rear portions sandwiched between two synchronization signals PRD and P0D. Therefore, a predetermined number (n) of clocks are extracted during playback during the one frame period. The gap g is provided between the post-synchronization signal POD and the pre-synchronization signal PRD of the next data block. Therefore, this disc is suitable for a data processing device such as a computer, and can process data of one frame over a relatively long time.

FIG. 1 shows an embodiment of a reproduced data processing device in a disk reproducing apparatus having the above-mentioned data format.

In this embodiment, a cycle slip error during reproduction is corrected by the following method.

(1) The address counter of the RAM to which the reproduction signal is written is started by the pre-synchronization signal PRD, and the post-synchronization signal P0D is detected. The address when this signal P0D is detected is detected. The difference between the clock and the predetermined number of clocks (eg, n) in one frame period is calculated and stored.

(2) At the same time, a defect of the reproduced signal is detected and its position (address) is detected and stored.

(3) At the time of reading the RAM, normal reading is performed up to the position where the defect obtained in (2) occurs, and after the position where the defect occurs, the difference obtained in (1) is used. Reading is performed while correcting the reading address based on.

According to the above description, one frame of data has a predetermined bit length (the number of clocks), and correct data is distributed to each address of the RAM. The second embodiment of the apparatus for carrying out the above-described data processing method will now be described.

This will be described with reference to FIG.

In FIG. 1, a reproduction signal RF from a big-cap (not shown) is supplied to an input terminal 1. The signal RF is shaped into a waveform by the waveform shaping circuit 2 and then written into the RAM 3 and supplied to the b-bit shift register 4 and the a-bit shift register 5, respectively. The above signal RF is further supplied to a comparator 6 and a differential rectifier circuit 7. The above RAM 3 is written by the write address counter 8.

In FIG. 3, if the signal RF shown in FIG. A has a defective portion having a length of £, the output signal shown in FIG. This signal is a signal obtained by detecting the approximate position of the defect signal. Further, the output of the differential rectifier circuit 7 is supplied to a phase comparator circuit 9, a low-pass filter 10 and a PLL circuit 12 composed of VCOL1. As a result, a clock CK synchronized with the signal RF is obtained from the VC 011, and the clock CK drives the write address counter 8.

If the signal RF is defective, the output signal shown in FIG. 3B is obtained from the low-pass filter 10. By adding this signal to the window comparator 13, a signal obtained by detecting the approximate position of the defective portion can be obtained from the comparator 13.

The detection signal of the defective portion obtained from the comparators 6 and 13 is added to the gate 14. The defective portion may be detected only by the comparator 6 or only the comparator 13, but in this embodiment, the defect is detected. I do it on both sides to make sure I go out.

Next, the output of the a-bit shift register 5 is applied to the matching circuit 15 and compared with the bit pattern of the pre-synchronization signal PRD. The coincidence signal obtained when the two coincide with each other is applied to the protection interpolation circuit 16 and sufficiently protected and interpolated, and then the address counter 8 is cleared. This causes the counter 8 to start counting from 0, and RAM 3 writes the signal RF.

The output of the b-bit shift register 4 is applied to the matching circuit 17 and compared with the bit pattern of the post-synchronization signal P 0 D. The coincidence signal obtained when the two coincide with each other is applied to the protection circuit 18.

The count value of the counter 8 is given to the RAM 3 and also applied to a window generation circuit 19, a defect position detection circuit 20 and a post-synchronization signal position detection circuit 21.

The window generating circuit 19 generates a window signal of a predetermined width centered on the normal position of the post-synchronization signal POD and adds the generated window signal to the protection circuit 18. And the like. The defect position detection circuit 20 detects an address of an approximate position where a defect has occurred based on a detection signal of a defect portion obtained from the OR gate 14, and is constituted by a register. The post-synchronization signal position detection circuit 21 detects the address of the position of the signal P 0 D based on the coincidence signal obtained from the protection circuit 18 and is composed of a register.

The protection circuit 18 protects the coincidence signal obtained from the coincidence circuit 17 and sends the coincidence signal detected by the window signal to the position detection circuit 21. Thus, the position detection circuit 21 detects the address of the position of the signal POD.

In Fig. 3, the signal PRD detected by the matching circuit 15 If the position of the signal POD detected by the coincidence circuit 17 is at the normal position. The signal PRD and the POD have the relationship shown in FIG. On the other hand, when the count value of the counter 8 becomes smaller than the predetermined value n of one frame due to a signal defect, for example, a dropout, the signal POD is set to the normal position as shown in FIG. Is shifted by one α. Further, when the count value is increased from the predetermined value η due to noise, the signal Ρ 0D is shifted by + α as shown in FIG.

The position detection circuit 21 detects the position of the signal Ρ0D as shown in FIGS. 3D, Ε, and F, and sends the count value m of the counter 8 at that time to the subtraction unit 22. Find the difference from the predetermined value n + QT or -or.

The position detection circuit 20 detects the approximate position of the defective portion based on the detection signal from the OR gate 14 and obtains its address.

As described above, the signal R F for one frame is written in the RAM 3. If a cycle slip error or the like occurs at this time, the signal R F is written in a state in which the error has occurred. At this time, the approximate position of the defective portion is stored in the position detection circuit 20, and the shift amount + or -α of the signal POD is stored in the subtracter 22.

When the writing of RAM 3 is completed as described above, the reading is started next. This reading is performed under the control of the system controller 23, and normal error correction is performed by the error correction decoder 24. In this embodiment, a cycle slip error is corrected together with the normal error correction.

The read address counter 25 of the η bit starts counting based on the instruction of the controller 23. The clock oscillator 26 supplies a clock to the counter 25 and the controller 23. The count value of counter 25 is added to 3-state buffer 27 and It is added to the 3-state buffer 29 through the subtracter 28 and further to the subtractor 30. The buffers 27 and 29 constitute the selector switch 31. Either of the buffers 27 or 29 is selected based on the outputs of the eclipse input gate 32 and the OR gate 33. 29 is selectively turned on to pass the counter output.

The pull! : + O or -α obtained by the unit 22 is added to the zero detector 34 and also to the above-mentioned subtraction unit 28, and the value of α is added to the count value of the counter 25. Make corrections. That is, when + α, or is subtracted from the count value, and when it is 1 or., Α is added to the count value. The zero detector 34 compares each bit pattern of α with all zeros, and when “−0”, outputs “1” to the above-mentioned AND gate 32 and OR gate 33.

Further, the address of the position of the defective portion stored in the position detection circuit 20 is added to the subtractor 30 and compared with the count value, and when the count value becomes the above-described defect position. In other words, when the defective portion of the signal RF written to RA # 3 starts to be read, a signal is output from the polarity determination circuit 35 and added to the AND gate 32 and OR gate 33. Is received.

According to the above configuration, when the reading of the counter 25 is started, the buffer 27 first becomes 0 N, and the RAM 3 is read out from the RAM 3 through the buffer 27 as it is. Next, when the read reaches the address corresponding to the defective portion of the signal RF, the buffer 27 becomes 0FF and the buffer 29 becomes ON. As a result, 1 ^ 1 ^ 13 reads out the address of the value obtained by correcting the count value of the counter 25 by + or -or. Therefore, the read one-frame signal is formed into the specified n bits. And are arranged in the correct order. Incidentally, the data corresponding to the correct address of the separately provided RAM may be rearranged in accordance with the detected count value.

According to the above, it is possible to prevent a large amount of data from being lost at one time due to a cycle slip error. Further, the above-described data processing can be performed using a time corresponding to the gap g between the data blocks. In addition, since the signals PRD and POD are provided before and after the 1-frame data block, the change in the number of clocks due to errors can be obtained with high accuracy. In the present embodiment, the position detection circuit 20 detects the defective portion of the signal at the time of writing. Since the C 1 flag appears continuously, it may be used to detect a defective portion.

According to the data processing device of the present invention described above, it is possible to rearrange the data due to the cycle slip error that has occurred after the defective portion of the reproduction signal at a regular position, thereby losing a large amount of data at one time. Can be prevented.

Claims

The scope of the claims .

1. When processing data reproduced from a disc in which a signal provided with a synchronization signal at the front and rear of a data block having a predetermined bit length is recorded,

A first detection signal is obtained by detecting a defect position of the reproduction data, and a second detection signal is obtained by detecting a position of a synchronization signal provided at the rear of the data block.

A signal representing the difference between the bit length of the data block and the second detection signal is obtained.

A data processing method in which the arrangement order of data after the defect position in the reproduced data is shifted by an amount corresponding to the difference signal.

2. A device for processing data reproduced from a disc on which a signal having a synchronization signal provided at a front part and a rear part of a data block having a predetermined bit length is recorded.

Storage means in which the reproduction data is written,

The clock extracted from the reproduced data is counted, and the write address counter of the storage means, which is cleared by a synchronization signal provided at the front of the data block,

First detecting means for detecting a defect position of the reproduced data,

Second detection means for detecting the position of a synchronization signal provided at the rear of the data block;

Means for determining the value of the difference between the bit length of the data tab and the detection signal obtained from the second detection means;

Complementary correction for shifting the sequence of data read out from the storage means after the defect position by an amount corresponding to the difference value. Correct means,

Data processing device comprising:

3. The first detecting means includes a third detecting means for detecting a defective portion of the reproduction data, and a detecting means for obtaining the count value of the write address counter from the third detecting means. 3. The data processing device according to claim 2, comprising: fourth detection means for detecting by a signal.

4. The correction means is means for giving the read address counter of the storage device and the count value of the read address counter to the storage means as they are from the beginning of the data to the defect position. 3. The data processing according to claim 2, further comprising: a means for providing to said storage means a count value obtained by correcting said force value with said difference value after said defect position. apparatus.