JPS61276176A - Data processing method - Google Patents

Abstract

PURPOSE:To decrease the quantity of data which are lost by errors by providing the synchronizing signals at the front and rear parts of a data block having the prescribed bit length and correcting the data arraying order at and after a defective part of the reproduction data in response to the detecting position of the synchronizing signal at the rear part. CONSTITUTION:The front synchronizing signal PRD of (a) bits having a prescribed bit pattern is recorded on a disk at the head part of data equivalent to a frame together with the rear synchronizing signal POD of (b) bits having a prescribed bit pattern recorded at the end part of an n-bit data block. In a reproduction mode an address counter of a RAM to which the reproduction signal is written is started by the signal PRD. Thus the difference is obtained between the address obtained when the signal POD is detected and a prescribed number of clocks obtained in a frame period and then recorded. At the same time, the defect and its position of the reproduction signal are detected and stored. In a read mode of the RAM the reading is carried out in a normal way up to the position where a defect is produced. Then the addresses are corrected by the obtained difference at and after the defective position. Thus the quantity of data lost by errors can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing method used in a playback device for a disc on which digital data is recorded.

[Summary of the invention]

The present invention detects a defective portion of the reproduced data by reproducing a disc on which a signal having a synchronization signal before and after each data block and a gap is formed between each data block is detected, and also detects a defective portion of the reproduced data. Detect the position of the synchronization signal provided at the rear of the block, find the difference between the bit length of the data block and the position of the synchronization signal at the rear, and determine the arrangement order of the data after the defective part of the reproduced data. This is a data processing method in which data is shifted by an amount corresponding to the above-mentioned difference. This can reduce the loss of a large amount of data due to cycle slip errors.

[Conventional technology]

A recording/reproducing apparatus using an optical disk on which digital data is recorded is generally provided with a function for correcting data errors during reproduction. This error correction function can correct errors caused by signal dropouts, noise, etc. within a certain period of time.

In the case of disks used in computers, etc., a synchronization signal is recorded at the beginning of the data block of the frame, and for example, 3 bytes are recorded between the end of the data block and the synchronization signal of the next data block. A relatively long gap is formed. This gap is provided to absorb rotational fluctuations due to disk eccentricity, etc.

[Problem that the invention seeks to solve]

The error correction function described above is completely unable to correct cycle slip errors caused by continuous dropouts, noise, etc. over a relatively long period of time.

A cycle slip error occurs when the number of clocks extracted during an Eframe period changes from a specified number due to continuous dropouts, noise, etc. over a long period of time. That is, when the clock number changes,
The address of the RAM where the reproduced data is written becomes incorrect, and all data after the defective part of the frame period becomes invalid.

[Means for solving problems]

In the present invention, a disc in which a synchronizing signal is provided at each end of a data block and a signal is recorded with a gap formed between each data block is reproduced, and a defective portion of the reproduced data is detected. The position of the synchronization signal provided at the rear of the data block is detected, the difference signal between the bit length of the data block and the synchronization signal at the rear is determined, and the arrangement order of the data after the defective part of the reproduced data is determined. is shifted by an amount corresponding to the difference signal.

[Effect]

Cycle slip errors after the defective portion of reproduced data can be corrected, and the amount of data lost due to errors can be reduced.

〔Example〕

FIG. 2 shows an example of a data format recorded on a disc to which the present invention can be applied.

In the figure, an a-bit pre-synchronization signal PRD having a predetermined bit pattern is recorded at the beginning of l-frame data, and b-bits having a predetermined bit pattern at the end of a 1, n-bit data block. After the synchronization signal POD is recorded. In other words, one frame of data block is preceded and followed by two synchronization signals PRD and POD.
It is recorded in a form sandwiched between. Therefore, a predetermined number (n) of clocks are extracted during reproduction during one frame period. Furthermore, the gap g described above is provided between the post-synchronization signal POD and the pre-synchronization signal PRD of the next data block. Therefore, this disk is suitable for data processing devices such as computers, and can process one frame of data over a relatively long time.

FIG. 1 shows an embodiment of a reproduced data processing apparatus in a disc reproducing apparatus having the above-described data format.

In this embodiment, cycle slip errors during reproduction are corrected by the following method.

(1) Start the address counter of the RAM into which the playback signal is written with the pre-synchronization signal PRD, and
The difference between the address when OD is detected and a predetermined number of clocks (for example, n) in one frame period is determined and stored.

(2) At the same time, the approximate position (address) where the defect in the reproduced signal occurs is detected and stored.

(3) When reading the above RAM, read normally up to the position where the defect occurred obtained in (2) above, and after the above position, the read address is corrected based on the difference obtained in (1) above. while reading.

According to the above, one frame of data has a predetermined bit length (
clock tll), and can allocate correct data to each address of the RAM, thereby making it possible to correct cycle slip errors.

Next, an embodiment of the above method will be described with reference to FIG.

In FIG. 1, an input terminal 1 is supplied with a reproduction signal RF from a pickup (not shown).

This signal RF is waveform-shaped by the waveform shaping circuit 2, and then R
It is written into AM3 and is also supplied to b-bit shift register 4 and a-bit shift register 5, respectively. Further, the signal RF is supplied to a comparator 6 and a differential rectifier circuit 7. Data is written into the RAM 3 by the write address counter 8.

In FIG. 3, if the signal RF shown in FIG. 3A has a defective portion of length l, an output signal shown in FIG. 3C is obtained from the comparator 6. This signal is a signal that detects the approximate position of the defective portion.

Further, the output of the differential rectifier circuit 7 is supplied to a PLL circuit 12 consisting of a phase comparator circuit 9, a low-pass filter 10, and a VCO II. As a result, the signal RF from the above VCoil
A clock GK synchronized with is obtained, and this clock CK
drives the write address counter 8.

If the signal RF has a defect, the output signal shown in FIG. 2B is obtained from the low-pass filter 10. By applying this signal to the window comparator 13, a signal detecting the approximate position of the defective portion can be obtained from the comparator 13.

The defect detection signal obtained from the comparator 6.13 is applied to the OR gate 14. Note that the detection of defective portions may be performed using only the comparator 6 or only the comparator 13, but in this embodiment, detection is performed using both to ensure detection.

Next, the output of the a-bit shift register 5 is output from the matching circuit 1.
5 and compared with the pattern of the previous synchronization signal PRD. A match signal obtained when the two match is applied to the protection interpolation circuit 16 for sufficient protection interpolation, and then sent to the address counter 8. Clear. This causes the counter 8 to start counting from O, and the RAM 3 to receive the signal R.
Write F.

Further, the output of the b focus shift register 4 is output from the matching circuit 1.
7 and compared with the pattern of the post-synchronization signal POD. A one-defeat signal obtained when the two match is applied to the protection circuit 18.

The counter value of the counter 8 is given to the RAM 3, and is also added to the window generation circuit 19, the defect position detection circuit 20, the post-synchronization signal position detection circuit 21, and the like.

The window generating circuit 19 generates a window signal of a predetermined width centered at the normal position of the post-synchronization signal POD and adds it to the protection circuit 18, and is constituted by a ROM or the like. The defect position detection circuit 20 detects the address of the approximate position where the defect occurs based on the defect detection signal obtained from the OR gate 14, and is constituted by a register. Post-synchronization signal position detection circuit 2
Reference numeral 1 detects the address of the position of the signal POD based on the coincidence signal obtained from the protection circuit 18, and is constituted by a register.

The protection circuit 18 protects the coincidence signal obtained from the coincidence circuit 17 and sends the coincidence signal detected by the window signal to the position detection circuit 21. This causes the position detection circuit 21 to detect the address of the position of the signal POD.

In FIG. 3, the signal PRD detected by the minus number circuit 15
On the other hand, if the position of the signal POD detected by the minus number circuit 17 is at the normal position, the signals PRD and POD will have the relationship shown in the figure. On the other hand, due to signal defects,
For example, when the count value of the counter 8 becomes less than the predetermined value n for one frame due to dropout, the signal POD deviates by one α from the normal position as shown in the figure. Furthermore, if the count value increases beyond the predetermined value n due to noise, the signal POD shifts by +α as shown in FIG.

The position detection circuit 21 detects the position of the signal POD as shown in the third diagram, E and F, and outputs the counter 8 at that time.
The count value m is sent to the subtracter 22 to find the difference +α or -α from the predetermined value n.

Further, the position detection circuit 20 detects the position of the defective part based on the detection signal from the or game 1-14 and obtains its address.

As described above, the signal RF for one frame is written into the RAM 3. If a cycle slip error or the like occurs at this time, the signal RF is written in the form in which the error has occurred. At this time, the position of the defective portion is stored in the position detection circuit 20, and the deviation amount ±α of the signal POD is stored in the subtracter 22, respectively.

When writing to the RAM 3 is completed as described above, reading starts next. This reading is performed under the control of the system controller 23, and the error correction decoder 24 performs normal error correction. In addition to this error correction, this embodiment also corrects cycle slip errors.

The n-bit read address counter 25 starts counting based on instructions from the controller 23. A clock oscillator 26 supplies a clock to the counter 25 and controller 23 . The count value of the counter 25 is added to the 3-state buffer 27, and the subtracter 28
The signal is added to the three-state buffer 29 through the subtracter 30. The buffers 27 and 29 constitute a selector switch 31, and either one of the buffers 27 or 29 is selectively turned on based on the outputs of the negative input AND gate 32 and the OR gate 33.
It is configured to allow the counter output to pass through.

+α or -α determined by the subtracter 22 is added to the zero detector 34 and also to the subtracter 28, so that the count value of the counter 25 is corrected by α. That is, when +α, α is subtracted from the count value, and when −α, correction is performed by adding α to the count value. Zero detector 3
4 compares each bit of α with all zeros, and when α=0, outputs “1” to the AND gate 32 and OR gate 33.

Further, the address of the position of the defective part stored in the position detection circuit 20 is added to the subtracter 30 and compared with the count value, and when the count value reaches the defect position, that is, the signal written in the RAM 3 is When the defective RF portion begins to be read out, a signal is output from the polarity determination circuit 35 and applied to the AND gate 32 and the OR gate 33.

According to the above configuration, when reading from the counter 25 is started, the buffer 27 is first turned on, and the count value is read out from the RAM 3 through the buffer 27 as it is. Next, when the readout reaches the address of the defective part of the signal RF, the buffer 27 is turned OFF and the buffer 29 is turned ON.
becomes. As a result, the address of the value obtained by correcting the count value of the counter 25 by +α or -α is read out from the RAM 3.

Therefore, the read l-frame signal is made up of predetermined n bits and data arranged in the correct order is obtained. In addition, according to the corrected count value, another RAM
The data corresponding to the correct address may be rearranged.

According to the above, it is possible to prevent a large amount of data from being lost at once due to a cycle slip error.

Also, the signal PRD before and after the data block of one frame.
, POD, the value of the change in the number of clocks due to an error, ±α, can be determined with high accuracy. In this embodiment, the position detection circuit 20 detects the defective portion of the signal at the time of writing, but when error correction is performed at the time of reading, the defective portion of the signal is detected by the C of the product code.
Since the I flag appears continuously, this may be used to detect a defective portion.

〔Effect of the invention〕

Data due to cycle sleeve errors that occur after the defective part of the repeating signal can be rearranged to the correct position.
This prevents you from losing a large amount of data at once.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment of a data format, and FIG. 3 is a timing chart of FIG. In addition, in the symbols used in the drawings, 3-----------RAM 8-----11-----to write address counter 20---m −〜−−−−−・Defect position detection circuit 21−・−・−−−−−・Post synchronization signal position detection circuit 22・−・−−−−−・−−−−One subtracter 2
5・−・・−・・−1−−−−−Read address counter 2 B−−−−−−−1・−−1−−−Subtractor 3
1.--.--m--.--.Select switch.

Claims (1)

[Claims] Data reproduced from a disc on which synchronization signals are provided at the front and rear of data blocks having a predetermined bit length, and gaps are formed between each data block. Detecting a defective portion of the reproduced data to obtain a first detection signal; detecting the position of a synchronization signal provided at the rear of the data block to obtain a second detection signal; A signal representing the difference between the bit length of the data pro-lag and the second detection signal is obtained, and the arrangement order of data after the defective portion of the reproduced data is shifted by an amount corresponding to the difference signal. How your data is processed.