JPH06216872A - Digital test signal generator - Google Patents

Abstract

PURPOSE:To set and revise optionally a start position J1 of VC data set to a pay-load area of a digital test signal of an STM frame structure in the unit of frames. CONSTITUTION:Revision information of a start position J1 of H1 data, H2 data set to a pointer area in an STM frame structure and VC data in a pay- load area is set in advance to an H1, H2 memory 11 and a trigger memory 12 in the unit of frames. Then each address is sequentially designated by a counter circuit 16 in response to a frame start signal FS input, data stored in each memory are read in terms of the hardware and a signal synthesis circuit 21 sets the data together with VC data of a VC memory 15 in the STM frame structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital test signal generator for generating a digital test signal having an STM frame structure adopted in an international communication network.

[0002]

2. Description of the Related Art CCITT (International Telegraph and Telephone Consultative Committee)
Has set a new synchronous interface standard for freely transmitting data at high speed between countries in the world. As is well known, in this synchronous interface standard, 1 Gb /
In order to synchronously multiplex high-speed signals of s, one frame is transmitted by STM-1 (Synchronous Transpor) as shown in FIG.
It is expressed by a frame structure of 156 Mb / s 270 bytes × 9 lines called t Model Level One). This STM-1 frame is generated by multiplexing three STM-0 frames as shown in FIG.

In the STM-0 frame structure shown in FIG. 11, the actual data to be transmitted is the payload area (accommodation location) from the 4th byte to the 90th byte of each row.
Is set in a standardized unit called VC (Virtual Container). Specifically, in the payload area of STM-0, 87 pieces of VC data are stored in one row, and a total of 783 (= 87 × 9) pieces of VC data can be stored in one frame.

Further, the first to third lines and the fifth to ninth lines out of the nine lines
An SOH area for storing an SOH (section over head) having functions such as frame synchronization and error monitoring is set in the first 3 bytes of each line. In the first 3 bytes of the 4th line, H indicating the absolute address (address) of the start position J1 of 783 VC data set in the payload area
A pointer area for setting 1, H2, H3 data is provided.

H1, H set in this pointer area
As shown in FIG. 12, 2 and H3 data are respectively b1
.About.b8 has an 8-bit structure. B7 of H1 data
Total 1 from the 2nd bit to the last bit b8 of H2 data
The 0 bit indicates the absolute address of the head position J1 of the VC data. These 10 bits are called a PTR (pointer).

The absolute address of the payload area is 0.
The address is the next position of the pointer area as shown in FIG. 11, the final position of the same line is the address 86, and the beginning of the next line is 8
7th address, and the final 782th address is the final position of the third line in the next frame. For example, STM- in FIG.
In frame 0, the absolute address of the start position J1 of the VC data is 88. Therefore, in this case, the 10-bit PTR is a value in which the number 88 is displayed in binary. Further, as shown in FIG. 12, each bit of odd-numbered digits of the PTR is attached with the symbol I, and each bit of even-numbered digits is attached with the symbol D.

Of the H1 data in the pointer area, 4 bits of b1 to b4 are called NDF (new data flag), and the change presence / absence information of the head position J1 designated by the PTR is set. Specifically, [0110] indicates no change (normal) and [1001] indicates change (PNTG: pointer
Change). The next 2 bits (SS) of b5 and b6 in the H1 data indicate the type of standard.

Further, dummy bits which are not used at the present time are set in the H3 data.

When the start position J1 of the VC data in the STM-0 frame is changed in the process of transmitting a large number of data using the STM-1 frame structure in which the STM-0 frame is multiplexed, As mentioned above, NDF
Change is set to (PNTG), and the absolute address of the start position J1 of the change destination is set to PTR.

Further, when it is necessary to set one less VC data than the specified number (783) or one more VC data in only one frame for some reason, FIG. 13 ( a) As shown in (b), the start position J
1 is moved back and forth by 1 pointer (1 address). at the same time,
The pointer area may be extended to the payload area by 1 pointer (the byte next to H3), or 1 pointer (H3) of the pointer area may be changed to the payload area, resulting in a blank area or duplication in the payload area. Is being prevented.

The step of incrementing the head position J1 by +1 is called + PJC (plus pointer justification).
Decreasing the head position J1 by -1 is called -PJC (minus pointer justification).

Therefore, the STM having the above-mentioned function
In order to perform a performance test of a communication device that transmits / receives a digital signal having a -1 frame structure or performs a data multiplexing process and a data demultiplexing process, a digital test having an STM-1 frame structure having the above-described function The signal needs to be applied to the device under test or the transmission line under test.

A digital test signal generator for generating a digital test signal having the STM-1 frame structure is constructed as shown in FIG.

For example, the processor 1 which is a microcomputer sets H for setting the output port 2 in the pointer area.
Set 1 and H2 data. At the same time, the processor 1 sends + PJC, -PJC, PN to the output port 3 as needed.
Set TG. H1, H2 set to output port 2
10 showing the absolute address of the start position J1 of the data
The bit PTR is applied to the head position calculation circuit 5.

+ PJC, -PJC, and PNTG are applied from the output port 3 to the head position calculation circuit 5. Then, when + PJC and -PJC are applied, the head position calculation circuit 5 obtains the actual head position by adding / subtracting the input 10-digit PTR by 1 pointer. Further, when PNTG is applied to the head position calculation circuit 5, the input PTR becomes the actual head position. Then, the calculated actual start position is applied to the address generation circuit 6 in synchronization with the input of the frame start signal.

The address generation circuit 6 starts designating a read address to the VC memory 7 from the time when the number of pointers indicating the start position J1 input from the start time of the payload area determined by the frame start signal FS has elapsed. In this VC memory 7, 783 pieces of VC data to be stored in the payload area are sequentially stored from address 0 to the final address 782. The VC data sequentially read from the VC memory 7 is sent to the next signal synthesizing circuit 4.

The address generating circuit 6 sends to the signal synthesizing circuit 4 a gate signal for distinguishing the SOH area, the pointer area and the payload area. However, + P
When JC is applied, the end timing of the gate signal is extended by one point in the payload area as shown in FIG. 13A, and when -PJC is applied, the end timing of the gate signal is shown in FIG. As shown in (b), the pointer area is extended by one point.

In addition to the VC data from the VC memory 7, a corrected 10-bit real-time pointer value (RP) to be set in the frame is input from the VC memory 7 to the signal synthesis circuit 4. , Output port 2 to N
DF and SS data are applied. Further, SOH data for setting the SOH area is applied to the signal synthesizing circuit 4.

Then, the signal synthesizing circuit 4 synthesizes these signals at a predetermined timing, and STM- shown in FIG.
Outputs a digital test signal of 0 format structure.

The multiplexing circuit 8 multiplexes three STM-0 frame-structured digital test signals thus created and outputs the final STM-1 digital test signal.

[0021]

However, as shown in FIG.
The digital test signal generator shown in (1) still has the following problems to be improved.

In other words, H1..storing data stored in the pointer area in the STM-0 frame structure of FIG. As shown in the figure, the H2 data is set by software from the processor 1 to each output port 2 and 3 using a program. The change information of the start position J1 is also output from the processor 1 to the output port 3
Set to soft.

As is well known, one STM frame has a unit of 8 KHz (125 μs). Therefore, in order to perform the PNTG, + PJC, and -PJC operations on a frame-by-frame basis, the data settings for the output ports 2 and 3 must be changed on a frame-by-frame basis in synchronization with the frame start signal FS of 8 KHz.

However, in the data setting for the output ports 2 and 3 by the processor 1, the settings of PNTG, + PJC and -PJC cannot be changed in synchronization with the frame signal, so that H1 and H of the pointer area are set for each successive frame.
2 Change data, PNTG, + PJC, -PJC
Cannot be specified.

However, in the actual digital signal,
Since various conditions may occur, there arises a problem that it is not possible to create a digital test signal that meets all the conditions for the device to be measured. As a result, there is a problem in that a test apparatus incorporating this digital test signal generator cannot perform a complete performance test on a device to be measured.

The present invention has been made in view of the above circumstances, and sets the start position on a frame-by-frame basis by setting each data set in the pointer area and the start position change information on a memory-by-frame basis in advance. To change
It is an object of the present invention to provide a digital test signal generator capable of combining start position change and start position forward / backward movement and generating a digital test signal that is closer to an actual digital signal.

[0027]

In order to solve the above problems, a digital test signal generator according to the present invention comprises an SOH memory for storing SOH data to be set in an SOH area of an STM frame structure, and a frame structure payload. A VC memory for sequentially storing the VC data to be set in the area from the start address, and H1, H2 indicating the start position of the VC data in the payload area to be set in the pointer area of the frame structure and the change presence / absence information of this start position. Data is stored at each address in frame units H1. H1.H2 memory, a pair of correction information for moving the head position forward and backward by one pointer, and a trigger memory for storing forcible change information of the head position at each address on a frame-by-frame basis. A counter circuit for sequentially designating read addresses of the H2 memory and the trigger memory; Head position calculation for calculating the actual head position based on the correction information and the forced change information output from the trigger memory, for the head position included in the H1 and H2 data read from each address designated by the counter circuit of the H2 memory A circuit, an address generation circuit that sequentially specifies the read address of the VC memory from the start address from the time corresponding to the start position calculated from the start time of the payload area, and each specified by the address generation circuit of the VC memory. V read from address
C data and H1. H1, H2 read from H2 memory
A signal synthesizing circuit for synthesizing the data and the SOH data read from the SOH memory in a predetermined order and outputting as a digital test signal for each frame unit, at least a trigger memory and H1. The H2 memory is provided with a data setting unit that sets each data in advance according to the test purpose.

[0028]

According to the digital test signal generator having the above-described structure, the H1. At each address in the H2 memory, H1 and H indicating the start position of the VC data in the payload area to be set in the pointer area of the frame structure and the change presence / absence information of this start position by the data setting unit in advance.
Two data are stored in frame units. Similarly, at each address in the trigger memory, a pair of correction information for moving the start position forward and backward by one pointer and forced change information for the start position are stored in advance in units of frames by the data setting unit.

Then, in the state where each data is set in each memory on a frame-by-frame basis, the counter circuit sequentially specifies the read address of each memory every time the frame start signal is input. As a result, H1. Each time a frame is started from the H2 memory and the trigger memory, new H1 data, H2 data and trigger information of + PJC, -PJC, PNTG are output.

The head position calculation unit is the H1. The actual start position is calculated based on the start position information included in the H2 memory and the information output from the trigger memory. The address generation circuit starts designating the read address of the VC memory from the position of the real-time pointer value (RP) output from the head position calculation unit. The VC data read from the VC memory is input to the signal synthesis circuit. The signal synthesis circuit
C data and H1. H1, H2 read from H2 memory
The data and the SOH data read from the SOH memory are combined in a predetermined order and output as a digital test signal for each frame.

When the digital test signal having the STM-N frame structure is created, several digital test signals having the STM-0 frame structure created as described above may be multiplexed.

Therefore, the trigger memory and H1.
If the trigger information of H1 data, H2 data and corresponding + PJC, -PJC, PNTG which should be set in each frame is set in the H2 memory for each of a plurality of consecutive frames, automatically in each frame unit. Digital test signals having different contents are continuously obtained.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the schematic arrangement of the digital test signal generator of the embodiment. H1. As shown in FIG. 3, the H2 memory 11 stores 8-bit H1 data and H2 data which are respectively set in the pointer areas of the same frame at addresses 0 to 1, 2, 3 ... .

Similarly, as shown in FIG. 3, the trigger memory 12 stores H1. The PNTG indicating the change of the position of the head position J1 of the VC data designated by the PTR in each frame at the same address as the H2 memory 11 and + PJC and -PJC as a pair of correction information for moving about 1 point are [1]. Alternatively, it is stored as a bit of [0]. In addition, in FIG. 3, data for 9 frames is stored.

H1. H2 memory 11 and trigger memory 1
When each data is input to the man-machine interface device 13 by the operator, each data 2 is set in the order of each address by the data setting unit 14 including a computer or the like.

FIG. 2A is a diagram showing the display contents of the display screen 13a of the man-machine interface device 13. N
PNTG, + PJ for each frame indicated by o
A type (Type) such as C, -PJC, PTR, and a PTR indicating the absolute address of the start position J1 displayed in decimal,
Mask information Mas for confirming the tolerance of CCITT
k and are displayed.

In the type, PNTG, + PJC,
-If PJC is set, the data setting unit 14
Converts these into bits of [1] and sets them in each address of the trigger memory 12. Note that PNTG, + PJC, and -PJC cannot be duplicated at the same address in the trigger memory 12. Type (Type), PT
If R is set, nothing is set in the trigger memory 12.

Next, H1. PNT in H2 memory 11
A digital test signal generated when G, + PJC and -PJC are set as shown in FIG. 3 will be described.

For example, when PNTG is set at address 0, the NDF in the same frame is [1001] indicating the change of the start position J1 (change of the pointer value). And 1
A 0-digit PTR indicates a change destination, for example, [3] [00000
00011] Also, if + PJC is set at the 3rd address, the 10-digit PT in the frame at the 2nd address immediately before is set.
A value obtained by inverting the bit of odd digit I in R [101010100
1] is set to PTR. Then, at the next address 4, 1 is added to the PTR of the frame at address 2 [00000
00100].

Further, when -PJC is set at the 6th address, the 10-digit PT in the frame at the 5th address immediately before is set.
The value obtained by inverting the bit of the even digit D in R [010101000
1] is set to PTR. Then, at the next 7th address, 1 is subtracted from the PTR of the 5th frame [0000000]
011] is set. In this way, PNTG, + PJC,-
If PJC is set, the pointer value is changed in the next frame.

In the mask information Mask, a 4-digit NDF set in b1 to b4 of H1 data and a 10-digit PDF are set.
TR mask information can be set.

The data setting unit 14 translates each data set in the format shown in FIG. 2 which is easy for the operator to understand, and translates each data into each memory 11 in the format shown in FIG.
Write in each address of 12 (address).

Further, the data setting unit 14 is used for the VC memory 1
ST shown in FIG. 11 in each area from 0 to 782 of No. 5
78 to be set in the payload area of the M-0 frame structure
Write 3 VC data. Specifically, as shown in FIG. 2B, the data of the VC start position J1 is written in the 0th address, the data next to the VC start position J1 is written in the 2nd address, and the VC start position is written in the 3rd address. Write the next data after J1. Then, at the final address 782, the VC start position J
Write the data immediately before 1.

The counter circuit 16 has a frequency of 8 kHz (cycle 12) indicating the start of an STM-0 frame input from the outside.
The frame start signal FS of 5 μs) is counted, and the count value is used as a read address for the trigger memory 12 and H1. It is applied to the H2 memory 11.

When the frame start signal FS is input, the timing generation circuit 17 receives this frame start signal FS.
Payload area by measuring the elapsed time from the input time.
Gate signals PAYT, H1G., For setting various data in the SOH area and the pointer area at a predetermined timing. H2
It outputs G, H3G, and H31G.

More specifically, as shown in the time charts of FIGS. 4 and 5, the gate signal PAYT is a gate signal for designating the SOH area and the pointer area in the frame structure of FIG. H2G, H3G
Is the H1 data, H2 data set in the pointer area,
It is a gate signal indicating each setting area of H3 data. Further, as shown in FIG. 13A, the gate signal H31G is a gate signal indicating a setting area of the extension data H31 when the pointer area is extended by 1 byte when + PJC is designated.

H1. The H2 memory 11 has a counter circuit 16
H1 stored at the address (address) specified in
The data and H2 data are sent to the signal synthesis circuit 21. H
1. Of the 16-bit data output from the H2 memory 11, 10-digit data indicating the PTR is input to the head position calculation circuit 18. Similarly, the trigger memory 12 stores the P stored at the address designated by the counter circuit 16.
NTG, + PJC (+ J). Each bit data of -PJC (-J) is sent to the head position calculation circuit 18 and the address generation circuit 19.

The head position calculation circuit 18 sends the input PTR to the address generation circuit 19 as a real-time pointer value (RP) in the next frame cycle only when the PNGT is input.

When + PJC (+ J) is input from the trigger memory 12, the head position calculation circuit 18 increments the current real-time pointer value (RP) by +1. In addition, this real-time pointer value (RP)
Is transmitted to the address generation circuit 19 in synchronization with the next frame start signal FS.

Further, when the -PJC (-J) is input from the trigger memory 12, the head position calculation circuit 18 decrements the current real-time pointer value (RP) by -1.
Furthermore, the real-time pointer value (R
P) is sent to the address generation circuit 19 in synchronization with the next frame start signal FS.

The address generation circuit 19 has further elapsed from the start time of the payload area indicated by the end time of the gate signal H3 sent from the timing generation circuit 17, by the number of the input real-time pointer values (RP). Designation of a read address to the VC memory 7 is started from time. The cycle for designating this address is set to the clock frequency 6.48 MHz (byte clock frequency in the STM-0 frame structure) required to send one piece of VC data supplied from the outside.

Further, the address generating circuit 19 performs a certain process on the gate signal PAYT input from the timing generating circuit 17 by trigger signals of + PJC and -PJC, and designates a write-inhibited area of VC data. The signal SOHG is generated and the counting operation of the write prohibition period address is stopped.

The address generation circuit 19 also sends a gate signal SOHG indicating a VC data write prohibited area to the signal synthesis circuit 21. The gate signal PAY described above
The constant processing of T means that when + PJC is applied, the end timing of the fourth row (pointer area row) in the gate signal SOHG is set to 1 in the payload area as shown in FIG.
Expand by points. When -PJC is applied, the end timing of the same line is shortened by 1 point in the pointer area as shown in FIG.

The VC memory 15 to which the read address is designated by the address generation circuit 19 starts from the designated address 0 to 7
Each VC data stored at the address 82 is sequentially sent to the next signal synthesizing circuit 21.

Further, the SOH memory 20 stores each SOH data to be set in the SOH area shown in FIG.

In the signal synthesis circuit 21, each gate signal SO
HG, H1G. H2G. H3G and H31G are applied. Then, the signal synthesizer 21 outputs the gate signal SO
Each SOH data stored in the SOH memory 20 is sequentially input in synchronization with the HG continuation period. Further, the signal synthesizing circuit 21 is synchronized with H1.
16-bit H1 and H2 data is input from the H2 memory 11.

The signal synthesizing circuit 21 sets the input VC data, SOH data, and H1 and H2 data in the payload area, SOH area, and pointer area of the frame structure shown in FIG. 12 using the gate signals. To do. Then, the signal in which each data is set is output as an 8-bit digital test signal (STM-0).

The multiplexing circuit 22 multiplexes three digital test signals of STM-0 frame structure thus created and outputs them as a final digital test signal of STM-1 frame structure.

The operation of the thus-configured digital test signal generator until the digital test signal having the STM-0 frame structure is created will be described with reference to FIGS.

4 and 5 show the start position J of VC data.
6 is a time chart showing the operation of each unit when 1 is set to the absolute address of [0] in the payload area and is changed to [3]. In this case, the trigger memory 12 and H1. As shown in FIG.
It is assumed that each data is set as shown in.

When the frame start signal FS having the cycle T _F is input, the counter circuit 16 starts counting and outputs the count value [0]. As a result, the trigger memory 1
NDTG of 2 is output and ND of [1001] indicating forced change
The H1 data and H2 data composed of F and the PTR of [0000000011] indicating the changed position {3] are output. At this time point, the head position calculation circuit 18 has calculated the real-time pointer value (RP) to be output in the next frame, so the PTR is [0] in this frame cycle. Therefore, the address generation circuit 19
Since the output of the address is started from the end time of the pointer area in the gate signal SOHG, in the digital test signal output from the signal synthesis circuit 21, the 8-bit area (address 0) next to the pointer area is the start position of the VC data. It is J1.

Then, when the next frame start signal FS is input, the count value of the counter circuit 16 becomes [1 (0
1)], nothing is output from the trigger memory 12, and H1. From the H2 memory 11, normal ND of [0110]
The H1 data and the H2 data composed of the PTR of [0000000011] indicating F and 3 are output. In this frame period, since there is no PNTG from the trigger memory 12, the PTR is not input to the head position calculation circuit 18. Then, as shown in FIG. 5, the head position calculation circuit 18 sends the real-time pointer value (RP) of [3] to the address generation circuit 19.

As a result, the address generating circuit 19 starts outputting the address from the time corresponding to the address [3] of the absolute address. Therefore, in the test signal output from the signal synthesizing circuit 21, 3 from the end position of the pointer area
The area (3rd address) is the start position J1 of the VC data.

Further, when the third frame start signal FS is input, the count value of the counter circuit 16 becomes [2
(10)], the trigger memory 12 and H1. H
2 The same data as the previous frame is output from the memory 1. Even in this frame period, P from the trigger memory 12
Since there is no NTG, the PTR is not input to the head position calculation circuit 18. Therefore, in this frame cycle, the head position calculation circuit 18 has the real-time pointer value (R) of [3].
P) is sent to the address generation circuit 19. Therefore,
The digital test signal output from the signal synthesis circuit 21 in this frame cycle is the same as the digital test signal output in the previous frame cycle.

Next, referring to FIGS. 3 and 6, the start position J1 of the VC data set to the absolute address of [3] in the payload area is changed to the absolute address of [4] + PJC.
The operation of each part in the case of performing is shown. In this case, + PJC is set in the address 3 of the trigger memory 12.

When the frame cycle is started, each memory 1
H1 and H2 data including + PJC at addresses 1 to 12 and PTR in which the odd-numbered I bit of the PTR of the frame period immediately before is inverted are read. Then, in the next frame period, the added PRT of [4] is sent to the address generation circuit 19. As a result, in this frame cycle, the fourth area (address 4) from the end position of the pointer area becomes the start position J1 of the VC data. In this case, since the gate signal SOHG is expanded into the payload area by 1 byte (8 bits), no empty area is generated in the bay load area. In this frame cycle, the PTR in the pointer area is set to data in which the odd digit I bit is inverted.

Further, in the next frame period, P
TR is a value that correctly indicates [4]. Then, the gate signal SOHG also returns to the original correct gate length. That is,
When + PJC is set, the digital test signal to be output is changed to the target digital test signal when two frame cycles have elapsed.

Contrary to this, conversely, referring to FIG. 3 and FIG. 7, the start position J1 of the VC data is set to the absolute address of [4] of the payload area to the absolute address of [3].
The operation of each unit when performing PJC is shown. in this case,
-PJC is set at address 6 of the trigger memory 12.

When the frame cycle is started, each memory 1
The H1 and H2 data including the + PJC at addresses 1, 12 to 6 and the PTR in which the even-numbered D bit of the PTR of the immediately preceding frame period is inverted are read. Then, in the next frame period, the subtracted real-time pointer value (RP) of [3] is sent to the address generation circuit 19.
As a result, in this frame cycle, the third area (3rd address) from the end position of the pointer area becomes the start position J1 of the VC data. In this case, since the gate signal SOHG is shortened by 1 byte (8 bits) to the pointer area, the VC data will not overlap. In this frame cycle, the PTR of the pointer area is an even digit D
The bit-inverted data will be set.

Further, in the next frame period, P
TR is a value that correctly indicates [3]. Then, the gate signal SOHG also returns to the original correct gate length. That is,
When -PJC is set, the digital test signal to be output is changed to the target digital test signal when two frames have passed.

Next, referring to FIG. 8, P is stored in the trigger memory 12.
H1. When NTG and + PJC are continuously set, and when PNTG and -PJC are continuously set. The setting contents of the H1 data and the H2 data of the H2 memory 11 will be described.

PNTG is set at address 0 and + at address 1.
When PJC is set, the H1 data and H2 data at address 0 are the same as in normal operation [1001] shown in FIG.
NDF and PTR indicating [3] are set. The H1 data and H2 data at address 1 are the ND of [0110]
F and the PTR obtained by inverting the odd digit I of the PTR indicating [3]
To set. Then, the NDF of [0110] and the PTR indicating [4] may be set to the H1 data and H2 data at the address 2.

When PNTG is set at the fourth address and -PJC is set at the fifth address, H1 at the fourth address is set.
Data and H2 data are the same as in the normal operation shown in FIG.
001] NDF and PTR indicating [0] are set. The H1 data and H2 data at address 5 are N of [0110].
DF and PT obtained by inverting the even digit D of PTR indicating [0]
Set R. Then, the NDF of [0110] and the PTR indicating [4] may be set to the H1 data and H2 data at the address 2.

Therefore, a continuous combination of PNTG and + PJC and a continuous combination of PNTG and -PJC are possible.

As described above, the H1. H1 and H2 data set in the pointer area and V in the payload area for each frame in the H2 memory 11 and the trigger memory 12
The forced change information of the start position J1 of the C data and the information (+ PJC, -PJC) for moving the setting area by +1 pointer or -1 pointer are set in advance.

Therefore, even with a high-speed digital signal having the STM-N frame structure, the above-described various settings relating to the change of the start position J1 of the VC data can be performed in each frame. Therefore, it is possible to perform the test on the device under test and the transmission line under test with a digital test signal that is closer to the actual digital signal.

Next, as shown in FIG. 9, the operator selects H1.
Consider a case where wrong data is intentionally set in the H2 memory 11. At the underline A at address 2, trigger memory 1
2 has no PNTG set and NDF is [011
However, the value is changed with respect to the PTR at the first address. In the underline B of the address 7, in the frame before the trigger memory 12, -P
Even though JC is set, the PRT does not have the correct value [3], but has another value.

As described above, by intentionally setting erroneous data in each of the memories 11 and 12, it is possible to intentionally set an error in the digital test signal and whether the measurement target device can accurately detect the error. Can be tested.

The display screen 13a shown in FIG.
In the above, at the time when + PJC and -PJC are set, it is possible to perform a confirmation test whether the measurement target device operates normally even with a digital test signal masking a predetermined number of digits of the 10-digit PTR.

As described above, the digital test signal shown in the mask operation of FIG. 2A, which includes an error intentionally falling into the CCITT standard, and the digital test signal shown in FIG. 9, which includes an error largely outside the CCITT standard, are included. Is applied to the same measurement target, the signal detection capability and error detection capability of the measurement target device can be measured.

The present invention is not limited to the above embodiment. In the apparatus of the embodiment, the finally obtained digital test signal is up to the digital test signal of the STM-1 frame structure in which the digital test signal of the STM-0 frame structure is tripled.
STM-4, STM with higher transmission rate than 1 frame structure
It may be a digital test signal with any frame structure STM-N such as -16.

[0083]

As described above, in the digital test signal generator of the present invention, the H1 data and H2 data set in the pointer area in the STM frame structure and the change information of the start position J1 of the VC data in the payload area are set. H1. The H2 memory and the trigger memory are set.

Therefore, even in the computer software method, even if the digital test signal has a high transmission rate that cannot be followed, the start position of the VC data can be easily changed on a frame-by-frame basis or the start position can be changed. The change and the movement of the starting position back and forth can be performed in combination, and a digital test signal that is closer to the actual digital signal can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital test signal generator according to an embodiment of the present invention.

FIG. 2 is a diagram showing a display screen of the apparatus of the embodiment and a storage content of a VC memory.

FIG. 3 is a diagram showing setting contents of each memory and an actual frame state of the apparatus of the embodiment.

FIG. 4 is a time chart showing the operation of the apparatus of the embodiment.

FIG. 5 is a time chart showing the operation of the apparatus of the same embodiment.

FIG. 6 is a time chart showing the operation of the apparatus of the same embodiment.

FIG. 7 is a time chart showing the operation of the apparatus of the same embodiment.

FIG. 8 is a diagram showing setting contents of each memory and an actual frame state of the apparatus of the embodiment.

FIG. 9 is a diagram showing setting contents of each memory and an actual frame state of the apparatus of the same embodiment.

FIG. 10 is a diagram showing a general STM-1 frame structure.

FIG. 11 is a diagram showing a general STM-0 frame structure.

FIG. 12 is a diagram showing a bit structure of a pointer area in the STM-0 frame structure.

FIG. 13 is a diagram showing expansion or contraction of a pointer area in the STM-0 frame structure.

FIG. 14 is a block diagram showing a schematic configuration of a conventional digital test signal generator.

[Explanation of symbols]

11 ... H1. H2 memory, 12 ... Trigger memory, 13 ...
Man-machine interface device, 14 ... Data setting device, 15 ... VC memory, 16 ... Counter circuit, 17 ... Timing generation circuit, 18 ... Head position calculation circuit, 19 ... Address generation circuit, 20 ... SOH memory, 21 ... Signal synthesis circuit , 22 ... Multiplexing circuit.

Claims (1)

[Claims] 1. A digital test signal generator for generating a digital test signal having an STM frame structure, comprising: an SOH memory (20) for storing SOH data to be set in an SOH area of the frame structure; A VC memory (15) for sequentially storing the VC data to be set in the payload area from the start address, the start position of the VC data in the payload area to be set in the pointer area of the frame structure, and whether or not this start position is changed Information H1 and H2 indicating information is stored at each address in the frame unit. An H2 memory (11), a pair of correction information for moving the head position forward and backward by one pointer, and a trigger memory (12) for storing the forcible change information of the head position at each address on a frame-by-frame basis. H1. A counter circuit (16) for sequentially specifying the read addresses of the H2 memory and the trigger memory;
1. The actual head position included in the H1 and H2 data read from each address designated by the counter circuit of the H2 memory is calculated based on the correction information and the forced change information output from the trigger memory. The start position calculation circuit (18) and the VC corresponding to the start position calculated from the start time of the payload area
An address generation circuit (19) for sequentially designating a read address of the memory from the head address, VC data read from each address designated by the address generation circuit of the VC memory, and the H1. H read from H2 memory
1, H2 data and SO read from the SOH memory
A signal synthesizing circuit (21) for synthesizing the H data in a predetermined order and outputting as a digital test signal in each frame unit, at least the trigger memory and the H1. Data setting unit that sets each data in H2 memory in advance according to the test purpose
(14) A digital test signal generator provided with.