SU1660154A1 - Device for pulse recording and driving - Google Patents

Description

The invention relates to a pulse technique and can be used in systems for the formation and processing of information. The purpose of the invention - improving reliability - is achieved by introducing the output bus 20 and the subtractor 2 pulses. The device also contains triggers 1, 3, keys 4 and 5 with memorization of the control signal, pulse counter 6, controlled frequency divider 7, AND 8, bus 9 clock pulses, initial setup bus 10, bus 11 series pulses, bus 12 control, tires 13 results, 14-19 output tires. The introduction of these elements and new functional relationships allows to increase the accuracy of the result of counting the number of pulses in a series. 7 il.

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The invention relates to a pulse

technology and can be used in the systems of formation and processing of information.

The purpose of the invention is to increase reliability.

FIG. 1 shows a functional diagram of the proposed device; in Fig.2 diagram of the key with the memorization of the control signal; FIG. 3 are timing diagrams explaining the operation of a key with memorization of a control signal; figure 4 is a circuit of a pulse subtractor; figure 5 - timing diagrams explaining the operation of the pulse subtractor; 6 and 7 are timing diagrams explaining the operation of the proposed device.

The device for recording and generating pulses contains the first trigger.

1, subtractor 2 pulses, second trigger 3, first 4 and second 5 keys with remembering control signal, pulse counter 6, controlled frequency divider 7 (UDCH), AND element 8, bus 9 clock pulses, initial setup bus 10, bus 11 pulses, bus 12 control, bus 13 result, as well as the first - the seventh output bus 14-20.

The first reset input of the trigger 1 is connected to the bus 10 and the reset input of the subtractor

2, the start input is connected to the bus 14 and the first output of the key 4, the second input of which is connected to the bus 15, the control input is connected to the direct output of the trigger 1, the control input of the key 5 and the bus 16, the information input is connected to the bus 11 and the input of the subtractor 2 whose information input is connected to bus 9, the first output is connected to bus 9, the first output is connected to counting input of counter 6, the reset input of UDCH 7 and bus 20, the second output is connected to information input of key 5, the first output of which is connected to reset input of trigger 3, bus 17 and entrance throw counter 6, bit outputs of which are connected to tires 13, and the output of the second discharge is additionally connected to the trigger start input 3, the inverse output of which is connected to the first input of the element 8, the output of which is connected to bus 18, the second input is connected to the second trigger reset input 1, the bus 19 and the output of the UDCH 7, the counting input of which is connected to the second output of the key 5, the control inputs are connected to the tires 12.

A device for recording and generating pulses operates as follows.

After turning on the device on the chic 10, you must apply a pulse. In this case, the trigger 1 is set to “O” (FIG. 6, 7c), and the subtractor 2 is set to the broadcast mode of the clock pulses fed to the bus 9 (FIG. 6, 76) from the information input to its second output (FIG. 6 , 7g). In accordance with the level "0" acting on the control input of the key 5, the clock pulses pass from its information input to its first output (Fig.6, 7h), are formed on the bus 17 and the trigger 3 and all bits of the counter 6 are set to the reset inputs in "0".

In the initial state, the bus 9 receives the clock pulses, on the bus 10, the tires 11 (FIG. 6, 7a), 13, 14 (FIG. 6, 7d), 15 (FIG. 6.7d), 16, 18-20 ( 6, 7m, l, e, respectively) there are levels "0", on the bus 17 clock pulses are allocated that coincide in duration and time position with the clock pulses on bus 9, on tires 12 a binary code of a certain number is set, the status of bits of the UDH 7 arbitrary.

Suppose you want to count the number of pulses in a series, the pulses of which are unevenly distributed within the series and have different durations, and the maximum time interval between the leading edges of the pulses does not exceed K periods of clock pulses. In this case, the tires 12 set the binary code of the number K.

The first impulse of the series, which enters the bus 11, in accordance with the level "0" acting on the control input of the key 4, passes from the information input of this key to its first output, is formed on the bus 14 and sets trigger 1 to "1". In addition , on the leading edge of the first pulse of the series, the subtractor 2 is transferred to the mode of subtracting one pulse from the sequence of clock pulses generated at its second output. As a result, the first clock pulse, which then arrives at the information input of the subtractor 2 from the bus 9, is allocated at its first output (and is not allocated at its second output), is formed on the bus 20, resets the UDCH 7 to its original state and writes the number 6 into the counter 6 1. The second clock pulse passes from the bus 9 to the second output of the subtractor 2 and further to the second output of the key 5 (FIG. 6, 7i), since the “1” level operates at its control input. In this case, the number 1 is written to the UDCH 7. The third and subsequent clock pulses also pass from the bus 9 to the second output of the key 5, and each of them increments the contents of the UDCH 7,

The second impulse of the series (and each subsequent) enters the bus 11 through inter 1660154

shaft of time not exceeding K periods of clock pulses. In accordance with the level "1" acting on the control input of the key 4, this pulse passes from the information input of the key 4 to its second output and is formed on the bus 15. In addition, on the leading edge of the second pulse of the series, the subtractor 2 is transferred to the subtraction mode of one pulse from the sequence of clock pulses generated at its second output. As a result, the first clock pulse, which then enters the information input of the subtractor 2 from bus 9, is allocated at its first output (and is not allocated at its second output), is generated by bus 20, resets the UDCH 7 to its initial state and increases the number in the counter 6 to 2. When this occurs, the trigger 3 is set to “1”, as a result of which the level “0” is formed at its inverse output (FIG. 6, 7k).

Further operation of the device when the third and subsequent impulses of the series arrive on the bus 11 is similar to the series described for the second impulse, except that the trigger 3 is constantly in the ”1" state.

After the last pulse of the series arrives on bus 11 and the corresponding clock pulse is allocated to bus 20, the UDCH 7 receives the clock inputs from the second output of the key 5. Since the UDCH 7’s division ratio is equal to the number specified at its control inputs (i.e. is equal to K), then the Kth clock pulse passes from the counting input to its output, is formed on bus 19 and goes further to the second reset input of trigger 1. This causes trigger 1 to switch, due to the bus 16 and control inputs of keys

4 and 5 is set to level 0 ". Clock pulses received on bus 9 after switching to" 0 "trigger 1, pass through subtractor 2 to the first output of the key

5 and are formed on the bus 17, setting trigger "3" at "0", all bits of counter 6 and returning the device to its original state. The operation of the device for registering pulses of the series is completed. Reading the result recorded from the counter 6 and indicating the number of pulses in the series received on the bus 11 should be done under the action of the pulse generated on the bus 19, because under the next clock pulse, the counter 6 is reset, and the device returns to the original condition and again ready to register the pulses of the next series,

Thus, when ne bus arrives 11 series of pulses, the pulses of which are unevenly distributed within the series and have different durations, and the maximum time interval between the leading edges of the pulses does not exceed K periods of clock pulses (in FIG. 6 and 7 K = 8) as a result of the device’s cycle of operation, a binary code of the number of pulses in the series was formed on tires 13, the first pulse of the series and the pulse train without the first pulse on tires 14 and 15, respectively; on the bus 16, a pulse enveloping the pulse train; on bus 17, clock cycles impulses without impulses involved in the registration of a series of pulses, the level 18 is kept on bus 18, a pulse is generated on bus 19, indicating the end of the series of pulses and the registration process of pulses contained in it, and on bus 20 a series of clock pulses corresponding to impulses of the registered series.

If the device is prepared for registering a series of pulses and a binary code of a certain number K is set on tires 12, and a single impulse is received on bus 11, the operation of the device in this case is similar to that described for the first impulse of the series. Since after this, for periods of clock pulses, no pulse arrives on the bus 11 (since a single pulse arrived), the (K + 1) -th clock pulse received in this mode on bus 9 is allocated at the output of the UDCH 7 (this clock the pulse relative to the counting input of the UDCH 7 is Km by subtracting one pulse from the subtractor 2), is formed on the bus 19 and goes further to the second reset input of the trigger 1 and through the element AND 8 to the bus 18. This sets the value to "0 "trigger 1. that ensures the subsequent return of the device to the original state.

Thus, when a single pulse arrives on bus 11 on tires 13, a binary code of number 1 is formed, on bus 14 — a pulse that coincides in duration and time position with the pulse on bus 11. On bus 15, the level “0” is saved on the bus 16 a pulse with duration K of periods of clock pulses was formed; on bus 17 — clock pulses; without a (K + 1) -th pulse participating in the process of registering a single pulse; on bus 18 — a pulse indicating that a single pulse arrived on bus 11 , on bus 19 - impulse, indicating End a process operation of the device on the bus 20 - clock pulse sootvetst1660154

incoming single pulse.

Each key with memorization of the control signal, which is part of the proposed device, can be performed, for example, on four OR-NOT elements and an inverter (FIG. 2), a pulse subtractor can be implemented, for example, on an OR element, 0-trigger and key with the memorization of the control signal (figure 4), and the UDCH may include in its composition a key with the memorization of the control signal, the element OR, the counter, the group of two-input elements AND-NOT and the multi-input element I.

The device allows to increase the accuracy of the result of counting the number of pulses in a series due to the separation in time of the pulses on the counting input and on the reset input of the pulse counter, which always ensures reliable recording by the device of the first pulses in the series.

Claims (1)

Claim A device for recording and generating pulses containing the first trigger, the first reset input of which is connected to the initial installation bus, the start input — to the first output bus and to the first output of the first key with a control signal, the second output and information input of which are connected respectively to the second output bus and bus pulse series, the control input is connected to the direct output of the first trigger, with - the third output bus and with the control input of the second key with remembering the control signal, the first output of which is connected to the fourth output bus, with the reset input of the second trigger and the reset input of the pulse counter, the bit outputs of which are connected to the result buses, and the output of the second digit is additionally connected with the trigger input of the horn trigger trigger, the inverse output of which is connected to the first input of the element I, the output of which is connected to the fifth output bus, the second input to the output of the controlled frequency divider, control inputs 5 which are connected to the control bus, clock bus and sixth output bus, characterized in that, in order to increase reliability, a seventh output bus and subtractor of 3 pulses are entered into it, the information input and mode input of which are connected respectively to the clock bus and with the pulse bus, the first output is connected to the counting input of the pulse counter, with the 5th seventh output bus and with the reset input of a controlled frequency divider, the output of which is connected to the second reset input of the first trigger and the sixth you the input bus, the counting input - with the second output 3 of the second key with memorization of the control signal, the information input of which is connected to the second output of the pulse minder, the reset input of which is connected to the intelligent initial setting. 1660154 -1 ι_ι -— I_GP ^ g SPP π_ □ ~ 1_n_g ____ π_π_π π π π η fie.Z fig one -ί ^^^ Ί ^ Ί ^ Ί ^ Ί ^^^ ηηЛ ^ Ί ^^^ ηЛ ^ η ί * ϋΊ_π_π_η L_P_P_P_P (rig 5 l_p_gi 1660154 Λ * e P P l ι -> Well μ ~ ι_π_η_ lll n l._. L.L. HittltgthiT-Lpc 3 SPT pp / and sapp _ LONG. L.PPPP - { to .......— | _ _ Y -> / β ____P_, Well --— ^; 7i 6 /