SU1462474A1 - Binary-decimal counter in 8-4-2-1 code - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for dividing the frequency of pulses into ten and controlling key circuits under conditions of high levels of pickup, interference, short-term variations in the supply voltage. Provides full exclusion of competitions, prohibited and hidden prohibited states. The counter consists of two counting triggers 3 and 17, five two-input elements AND-HE 6, 7,12,23,24, two three-input elements AND-HE 8 and 13, two triggers with separate inputs 9 and 20. The counter forms a direct and inverse binary-decimal codes of the number of pulses arriving at it via the input bus 1. 2 Il. with (L with: o y 4ib U and

Description

1U62A74

The invention relates to a pulse technique and can be used in devices for dividing a pulse frequency into ten and controlling key circuits under conditions of high pickups, interference, and possible short-term variations in the supply voltage.

The purpose of the invention is to expand the scope by eliminating prohibited and hidden prohibited states.

Figure 1 shows the structural scheme of the proposed binary-decimal counter in code 8-4-2-1; in Fig. 2, time diagrams of its operation (the number of the diagram corresponds to the number of the bus on which this signal is present, or, if the signal 20 is not connected to any bus, the number of the diagram corresponds to the number of the element in Figure 1, the output of which is removed this signal)

input element AND NOT 22; a two-input element IS-NOT 23, the output of which is connected to the input of a two-input

g of the element AND-24, the output of which is connected to the bus 25 reverse code of the fourth bit; an inverter 26, the input of which is connected to the output of the element AND-NOT 24, and the output connected to the bus 27

10 direct code of the fourth bit.

Counting1she flip-flops 3 and 17 operate in phase with the falling edge of the pulse fed to the counting input of the corresponding flip-flop. Installation

15 in the counting triggers is provided by applying to the input of the installation in the O zero logic level, and the counting mode is supplied to the input by a single logic level.

The binary-decimal counter in code 8-4-2-1 works as follows. Let, before applying positive pulses to the input bus 1 of a binary-decimal counter in code 8-4, the binary-decimal counter in code 25 2-1 has been made initial setup.

8-4-2g1 contains input bus 1 and bus 2 of the initial installation, which are connected respectively to the input of the counting signals and the installation input to

To do this, it is enough to apply a zero signal to the bus 2 of the initial installation. It is directly applied to the input of the installation in O

first

first

firing single signals at the outputs

elements AND NOT 6, 8 and 13. After this, I1111

go in, install in

trigger

About the first counting trigger 3; the first 30 counting trigger 3 and causes a new counting trigger 3, direct and injection at its direct output (on the bus, the output outputs of which are connected to the four direct codes of the first bit), respectively; and 5 of the direct left level, and on the inverse output and the return code of the first digit; (on the bus 5 of the return code of the first two-input element 6, the input of the 35-bit) of the unit level. Zero second is connected to bus 4, a direct coder on bus 4, a direct code for a first-time form; two-input element AND-NOT 7, the output of which is connected to the input of the three-input element AND-NOT. 8, and the input to the installation input of the unit of the asynchronous RS-flip-flop 9 with separate inputs consisting of the four-input element AND-HE 10 and the two-input element AND-HE 11; the two-input element AND-NO 12., the input of which Thus, the initial installation of the trigger 9 with separate inputs occurs: at the output of the element 10 a single signal is generated, and at the output of the element AND-NOT 11. - a zero signal. After that, a single signal (from the output of the IS-NE element 8) appears at both inputs of the NAND 12 element with single inputs 9, and a zero signal at the first input of the installation at O, (from the initial installation bus 2)

45

pogo connected to the output of the three-input element AND-NOT 13; a second-order reverse code bus 14 connected to the input of the inverter 15, the output of which is connected to the direct-code bus 16 of the second bit; The second counting trigger 17, the direct output of which is connected to the bus 18 of the third direct discharge code, and the inverse output to the bus 19 of the third discharge return code and to the inputs for setting the unit of the asynchronous RS flip-flop with separate inputs 20, consisting of three-input element AND-NOT 21 and two

Ny signals (from the outputs of the elements AND-NOT 10 and 13), which leads to the formation of a zero signal at its output. The signal from the output of the NAND element I2 causes the appearance at the output of the NAND element (and on the bus 14 a second bit reverse code connected to

input element AND NOT 22; a two-input element IS-NOT 23, the output of which is connected to the input of a two-input

element AND-24, the output of which is connected to the bus 25 reverse code of the fourth bit; an inverter 26, the input of which is connected to the output of the element AND-NOT 24, and the output connected to the bus 27

direct code of the fourth bit.

Counting1she flip-flops 3 and 17 operate in phase with the falling edge of the pulse fed to the counting input of the corresponding flip-flop. Installation

in the counting triggers, the zero logic level is supplied to the installation of the O installation, and the counting mode is provided by a single logic level to this input.

The binary-decimal counter in code 8-4-2-1 works as follows. Before giving positive pulses to the input bus 1 of a binary-decimal counter in code 8-4, let it be enough to send a zero signal to bus 2 of the initial installation. It is directly fed to the input of the installation in O

first

the counting trigger 3 causes the zero level on the direct output (on the 4th bus of the direct code of the first bit) and the inverse output (on the 5th bus of the reverse code of the first bit) of the unit level. The zero level on the bus 4 direct code forms

firing single signals at the outputs

elements AND NOT 6, 8 and 13. After this, I1111

go in, install in

trigger

the counting trigger 3 causes the zero level on the direct output (on the 4th bus of the direct code of the first bit) and the inverse output (on the 5th bus of the reverse code of the first bit) of the unit level. The zero level on the bus 4 direct code forms

30 of the counting trigger 3 causes the zero level on the direct output (on the 4th bus of the direct code of the first bit), and on the inverse output (on the bus 5 of the first 35 bit return code) of the unit level. The zero level on the bus 4 direct code forms

40 with separate inputs 9 is a single signal (from the output of the element IS-NE 8), and at its first input of the setting to O there is a zero signal (from the multiple trigger 3 and calling at its direct output 4 the direct code for the first time the left level , and on the inverse (on the tire 5 of the inverse code of the discharge) of a single level the level on the bus 4 is direct

here are 2 initial installs)

Ny signals (from the outputs of the elements AND-NOT 10 and 13), which leads to the formation of a zero signal at its output. The signal from the output of the NAND element I2 causes the appearance at the output of the NAND element (and on the bus 14 a second bit reverse code connected to

3

output element AND-NOT 7) a single level.

The single signal on the bus 14 is inverted by the inverter 15 and on the bus 16 of the direct code of the second bit appears a zero level, also connected to the counting input of the second counting trigger 17 Because the installation signal in O of this trigger is connected to a zero signal from the initial bus 2, on the forward code of the trigger 17 (on the bus 18 of the direct code of the third bit) the zero level appears, and on its inverse output (on the bus 19 of the third digit reverse code) a unit level.

Thus, a single signal appears from the setup input into 1 flip-flop with separate inputs 20 (from the third-order reverse code bus 19), and a zero signal from its first installation input to the 0 (from the initial setup bus 2). This causes an initial setup of the trigger 20 with separate inputs: a single signal is generated at the output of the NE-21 element, and a zero signal at the output of the IS-NOT 22 element. At the same time, on both inputs of the NAND element 23, there are single signals (from the outputs of the NAND elements 6 and 21).

Thus, at the output of the NAND 23 element, a zero signal appears, which, in turn, generates a single signal at the output of the NAND 24 element (and on the bus 25 of the fourth digit return code connected to the output of the NAND element 24). The single signal on the bus 25 is inverted by the inverter 26 and on the bus 27 of the direct code of the fourth bit a zero signal appears.

Thus, during the operation of the Zero signal on the bus 2 of the initial setup, signals are generated at the outputs of all the logic elements of the proposed binary-decimal counter in code 8-4-2-1. Since the initial setup bus is connected only to the inputs of the trigger circuits, the potentials at the outputs of the logic elements of the proposed counter do not change upon completion of the initial setup mode and the formation on bus 2 of the initial setup unit is one. level

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Thus, after the end of the initial setting mode, before applying the counting pulses, the zero level

C appears on all tires of the 4, 16, 18, 27 forward code and the unit level T is on all the tires 5, 14, 19, 25 of the counter return code. This means that the counter is set to state 0000.

After the passage of the first pulse (time t) applied to the input bus 1, the counting trigger 3 is transferred to the unit state 15: at its direct output (bus 4 of the direct code of the first bit) a single signal is generated and at the inverse output ( bus 5 reverse code of the first bit) - zero,

20 After that, on all inputs of the element IS-NE 8 single signals appear and at the output of the element IS-HE 8 a zero level is formed. This signal confirms the unit level at

2b output element AND-NOT 7 and gets to the input of the installation in 1 trigger 9 with separate inputs. Since on all inputs of the installation in O of this trigger there are single signals (from the output of the NE-13 element, from the bus 2 of the initial installation and from the bus 25 of the fourth digit return code), the signal at the input of the installation to 1 causes the flip-flop of the trigger 9 to one 35 The main condition is: at the output of its element NAND 11, a single signal is generated, and at the output of the element NAND 10.

40

45

50

55

A zero signal at the output of the NAND 10 element causes the appearance of a single signal at the output of the NAND 12 element. There are no other changes at the moment t, and the state is 0001 o

At time t, at the end of the second pulse, the counting trigger 3 goes into state O. In this case, a single signal is generated at its inverse output and zero at the forward output. This signal confirms the unit level at the outputs of the elements AND-NOT 6 and 13 and establishes a single signal at the output of the element AND-NE 8. After that, the individual signals, which are, appear at both inputs of the element AND-NE 7. results in the formation of a zero signal at the NAND 7 element.

Thus, a zero signal appears on bus 14 of the second bit reverse code. It is inverted by an inverter 15, and a single signal appears on the bus 1 6 of the direct code of the second bit. There are no other changes in the signals at the outputs of the elements at time t, and in the counter there appears: state 0010,

I After the termination of the third impulse I supplied to the input bus 1 (time t) in the counting trigger 3 records I O

I unit: appears zero; signal at its inverse output (bus

5 reverse code of the first bit) and; a single signal at the direct output i (bus 4 direct code of the first bit); After that, all I inputs of the NAND 13 element have single I signals, resulting in the output I of the I AND 13 element 13 appearing zero I signal . It confirms a single I signal at the output of the element AND-NOT 12 and; enters one of the inputs of the installation in the On trigger 9 with separate: inputs.

 Since all the other inputs of this trigger contain single signals, a single signal is generated at the output of its element i-NOT 10, and a output signal at the output of element i-NOT 11 is zero. All other signals remain at time t. unchanged, and i binary decimal counter in the code: 8-4-2-1 turns out to be in the OOP state.

After the end of the fourth counting pulse, applied to the threshold 1 (time t), zero is written to the counting trigger 3: a single signal appears at its inverse output (bus

5 return code of the first bit) and zero signal at the direct output (bus 4 direct code of the first bit). This signal confirms the single output signals of the NAND elements.

6 and 8, and also establishes a single output signal on the NAND 13 element. After this, single signals, i.e. at the output of the element AND-NOT 12 a zero level is formed. It, in turn, generates a single, single signal at the output of the element AND-NOT 7 (bus 14 of the second bit return code), which is inverted by inverter 15 (bus 16 of the direct code of the second bit Yes),

Thus, at the counting input i of the second counting trigger 17, the trailing edge of the input signal passes.

Since a single signal from the bus 2 of the initial installation is fed to the input of the installation to the On trigger 17, at the time t the counting trigger 17 switches; on his way out

(bus 18 of the forward code of the third section) is set to a single level, and at the inverse output (bus 19 of the reverse code of the third card, yes) is zero. This signal confirms

a single output signal of the element IS-NOT 24 and is fed to the input of the installation in 1 trigger 20 with separate, departures. Since there are single signals on the remaining inputs of this trigger, trigger 20 is switched: a single level appears at the output of its element 22, and NO-21 21 is zero at the output of the 1 element. This level causes

single output signal

element NAND 23. Other signal changes at time t. does not occur, and the binary-decimal counter in the code is set to

0100.

After the passage of the fourth counting pulse, the states of the output signals 3, 7, 8, 9, 12, 13, 15 (which only changed at times

tj and t) .tg) are completely repeated, sos-, then neither before the feeding of the first count pulse. The external signals on this group of elements have not changed either, so the signals change at the moment

The t end of the fifth counting pulse must repeat the changes at time t, after the sixth (tg) there will be the same changes as at time t, j, and after the seventh (ty) the same changes as at time tjo

Thus, at time t, the counter changes to the state 0101, at time t.g - to the state 0110, and at time t- to 0111s. In this case, after

the end I of the transition process of switching the counter at the moment of t-, zero levels must be present on the tires 5, 14, 19 of the return code and on the bus 27 of the direct code, and the unit ones

the levels are on tires 4, 16, 18 of the forward code and on the bus 25 of the return code. In addition, the unit level must be at the outputs of the AND-HE elements 6, 8, 10, 12, 22 and 23 o. The outputs of the AND-HE elements II, 13, 21 are set to zero signal levels,

At the moment tg of the end of the eighth counting pulse, the countable trigger 3 is transferred to the zero state. In this case, at its inverse output (bus 5 of the reverse code of the first bit) a single level is set, and at the direct output (bus 4 of the direct code of the first bit) a zero signal is generated. It confirms the single signals at the outputs of the NAND elements 6 and 8, and also establishes a single signal at the output of the NAND 13 element. After that, on both inputs, the NAND 12 element is set to single levels, and the output of the NAND 12 element a zero level is formed. This signal is caused by the appearance of a single signal at the output of the NAND 7- element (bus 14 of the second bit reverse code). This signal is inverted by the inverter 15, and a zero signal is generated on the bus 16 of the direct code of the second bit.

Thus, at the counting input of the second counting trigger 17, the trailing edge of the counting signal passes (while a single signal from the initial setup bus 2 remains unchanged at the input of the initial installation), which causes the flip of the trigger 17: the third direct bus 18 the bit appears a zero signal, and a single signal is formed on the third bit reverse code bus 19 of the third bit. After that, at both inputs of the NAND element 24 there are no significant signals, as a result of which a zero signal is generated at the output of this element (fourth-digit return code bus 25). It is inverted by an inverter 26, and a single signal appears on the bus 27 of the direct code of the fourth bit. There will be no other signal changes at time tg, and the binary-decimal counter in code 8-4-2-1 is set to state 1000.

After the end of the ninth pulse (time tq), the counting trigger 3 is triggered: a zero signal appears on bus 5 of the first discharge return code, and a single one appears on bus 4 of the direct first discharge code. After that at both entrances

element AND NOT 6, single signals are set. As a result, a zero signal is generated at the output of the AND-HE element 6. It confirms the single output signal of the NAND 23 element and falls on one of the installation inputs to the O flip-flop 20 with separate inputs. Since on the rest

There are single signals in the 10 inputs of this trigger; it is switched: a single signal is generated at the output of the NAND 21 element, and a zero signal is output at the output of the IS-NOT 22 element. Other signal changes at the outputs of logic elements at time t.

20

25

thirty

.g does not occur, and the binary-decimal counter in code 8-4-2-1 is set to state 1001.

At the end of the tenth counting pulse (time t,), the first counting trigger 3 is triggered. At the same time, a single signal is generated at its inverse output (bus 5 of the return code of the first bit), and at the forward output (bus 4 of the direct code of the first bit) - zero signal. It confirms a single signal at the outputs of the elements AND-HE 8 and 13, and also forms a single signal at the output of the element AND-NOT 6. After. After this, unit levels are set at both inputs of the NANDI element 23, and a zero signal appears at the output of the NANDI element 23 35. He, in turn, establishes a single signal at the output of the element AND-NOT 24 (bus 25 reverse code of the fourth bit). The signal on bus 25 is stranded by one is inverted by inverter 26, and on bus

27, a fourth-bit direct code, a zero signal appears. There are no other changes at the moment, and the binary-decimal counter in the code: 45 8-4-2-1 is set to the LLCOo state. At the same time, all the output signals of the logic elements of the binary-decimal counter in the code repeat the corresponding signals after the end of the initial installations before giving the counting signals. Further, the operation of the binary-decimal counter in code 8-4-2-1-occurs in the indicated manner.

Thus, the binary-decimal counter in code 8-4-2-1 sequentially goes to the state from 0000 to 1001 and then again 0000. P50

55

4624748

element AND NOT 6, single signals are set. As a result, a zero signal is generated at the output of the AND-HE element 6. It confirms the single output signal of the NAND 23 element and falls on one of the installation inputs to the O flip-flop 20 with separate inputs. Since on the rest

There are single signals in the 10 inputs of this trigger; it is switched: a single signal is generated at the output of the NAND 21 element, and a zero signal is output at the output of the IS-NOT 22 element. Other signal changes at the outputs of logic elements at time t.

.g does not occur, and the binary-decimal counter in code 8-4-2-1 is set to state 1001.

We show that, apart from these ten states, the circuit implementation of the counter does not allow any other states. In principle, there are six such forbidden states: 1010, 1011, 1100, 1101, 1110, 1111.

We first show the elimination of the emergency states 1 100, 1101, 1110 and 1111.0 In all these states, the 4-bit 18 direct code of the third bit - Yes, a single 4 signal must be present, and a zero signal on the 19-bit reverse code bus.

The zero signal on the bus 19 supplies - to the input of the element AND-NOT 24. Thus, at the output of the element AND-NOT 24 the bus 25 of the fourth return code of the fourth bit is set to a single ignal. It is inverted by an inverter 6, and a zero signal is set on the 27th direct code bus of the fourth bit, i.e. The circuit implementation of the meter excludes simultaneous (in its third and fourth section) single information, and states 1) 00, 1101, and 1111 cannot arise.

We now show the exclusion of the forbidden states 1010 and 1011 „V. of ob.on | nx of these states on the bus 25 of the inverse code of the fourth bit must be present. The zero level of the signal (pa, inverted by inverter 126, creates a single signal on the fourth-bit direct code bus 127. A zero signal on the bus 25 determines single signals at the outputs of the AND-HE elements 8, 10 and 13 "At the same time, both inputs of the AND-NOT element 12 have single signals, which leads to forming a zero signal at its output

The zero signal at the output of the NAND 12 element determines the occurrence of a single signal at the output of the NAND 7 element (the 14-bit return code of the second bit). It is inverted by inverter 15, and a zero signal is generated on bus 16 of the direct code of the second bit, Toe. The circuit implementation of the counter eliminates the simultaneous presence of single information in its fourth and second bits, and states 1010 and 1011 cannot occur.

Thus, the scheme of a binary-decimal counter in code 8-4-2-1 excludes the possibility of any prohibited-. new state

We now show the elimination of hidden forbidden states. These states, in principle, can occur when flip-flops of flip-flops 9 and 20 with separate inputs when exposed to strong interference, if all their inputs have single signals at the moment of exposure to interference. From the analysis of the timing diagrams of the counter (Fig. 2), it can be seen that there can be nine such states: four for trigger 9 with separate inputs and five for trigger 20 with separate inputs

Let us consider these situations in detail. Flip-flop of trigger 9 with separate inputs under the influence of external interference occurs at the moment of time after the initial installation (or at the end of the tenth counting pulse) before the end of the first pulse. At the same time, the output of the NAND 11 element turns out to be a single signal, and on the code of the 5 NANDE element 10 - zero, which leads to the formation of a single signal at the output of the NAND 12 element. At the same time, at both inputs of the NAND element 7, there are single signals that 30 determines the formation at its output (the 14-bit reverse code bus 14) of the zero signal. The zero signal on the bus 14 is inverted by the inverter 15, and a single signal appears on the J6 bus of the direct code of the second bit. Thus, under the influence of interference, the counter transitions from state 0000 to state 0010. on 40 all elements correspond to the state of the counter after the second count pulse

A flip-flop of flip-flop 9 with separate inputs occurs under the influence of external interference at the time point after the end of the second counting pulse before the end of the third one. At the output of the AND-HI element 11, there is a zero signal, and at the output of the IS-10 element - unit. Both inputs of the IS-NO 12 element have single signals, which leads to the formation of a zero signal at its output, which, in turn, 55 changes the output signal of the IS-NE element 7 (bus 14 of the second return code) from zero to single This single signal is inverted by an inverter 15, and on bus 16

 one

a direct bit code appears a zero signal. Thus, under the influence of interference, the counter changes from state 0010 to state 0000. At the same time, the output signals on all elements correspond to the state of the counter after the initial installation.

The flip-flop of flip-flop 9c is separated by separate inputs under the influence of external interference at the instant of time after the end of the fourth pulse before the end of the fifth. At the output of element I-HE 11 there is a single signal, and at the output of element i-NOT 10 - zero, which results a single signal at the output of the element IS-NOT 12. On both: the inputs of the element IS-NOT 7 are single signals, which determines the formation at its output (bus 14 of the second bit return code) a zero signal. The zero signal on the bus 14 is inverted by the inverter 15, and a single signal appears on the bus 16 of the forward Discharge Code 16. Thus, under the influence of interference, the counter changes from state 0100 to the ON state, and the output signals on all elements correspond to the state of the counter after the sixth counting pulse.

The flip-flop 9 is transferred with separate inputs under the influence of external interference at the time point after the end of the sixth pulse before the end of the seventh. At the same time, the output of the AND-NE element 11 is zero, and the output of the AND-NE 10 element is single. At both inputs of the IS-NOT 12 element, zero signals appear, which leads to the formation of a zero signal at its output, which in turn changes the output signal of the AND-NOT 7 element (bus 14 of the return code of the second bit) from zero to single. This single signal is inverted by the inverter 15, and a zero signal appears on the bus 16 of the direct code of the second bit. Thus, under the influence of interference, the counter changes from state 0110 to state 0100, and the output signals on all elements correspond to the state of the counter after the fourth pulse.

25

6247412

Trigger 20 is transferred with separate inputs under the influence of external interference at time 5 after the initial setup (or at the end of the tenth counting pulse) before the end of the first pulse. In this case, a single signal appears at the output of the NAND element 22, and a zero signal at the output of the NAND 21 element leads to the formation of a single signal at the output of the NAND 23A element. At the same time, at both inputs of the NAND element 24 there are single signals 15, which determines the formation at its output (bus 25 of the return code of the fourth bit) of the zero signal. The zero signal on bus 25 is inverted by the inverter 26, and on the bus 20 of 27 forward code of the fourth bit a single signal appears. signal Thus, when an interference occurs, the counter changes from 0000 at 1000. At the same time, the output signals on all elements correspond to the state of the counter after the eighth counting pulse.

The flip-flop 20 is transferred with separate inputs under the influence of external interference 30 at the time point after the end of the first counting pulse before the end of the second pulse. In this case, the output of the NANDA element 22 turns out to be a single signal, and at the output 35 of the element NANDA21 it is zero, which leads to the formation of a single signal at the output of the NANDI element 23, Moreover, at both inputs 24, single signals are detected, which determines the formation at its output (the 25-bit reverse code of the fourth bit) of the zero signal. The zero signal on the busbar 25 is inverted by the inverter 26, and a single signal appears on the bus 27 pr - 45 of the fourth bit code. A zero signal on bus 25 also leads to the formation of a single signal at the output of the NAND element 8 and switching trigger 50 9 with separate inputs. In this case, a zero signal appears at the output of the NAND 11 element, and at the output of the N 10 NOT element, the signal is single. At both inputs of the element AND-NOT 12, single signals appear, which leads to the formation of a zero signal at its output, which confirms a single signal at the output of the element AND-NE 7 o The single signal on the bus 27

13

the direct code of the fourth bit goes to the input of the element AND-NOT 6, which leads to the formation of a zero signal at its output (since a single signal is also present at the second input of this element). The negative signal at the output of the element AND-H 6 leads to the switching of the trigger 20 with separate inputs: at the output: the element AND-HONE 22 turns out to be a zero-I signal, and at the output of the element AND-HE I 21 - a single signal. interference counter move I from state 0001 to state 1001. I At the same time, the output signals on all I elements correspond to the state I of the counter after the impact of the ninth

Impulse counting.

Ii

i There is a flip of trigger 2 {} with separate inputs under the influence of external interference at the moment of time I after the termination of the second pulse; counting before the end of the third impulse: At the same time, the output of the NES-22 element turns out to be a single signal, and the output of the NES-21 element is zero, which leads to the formation of a single level at the output of the IS-NE 23 o At both inputs of the AND-element HE 24 are single signals, which determines the formation of its vk-; de (fourth-i reverse code bus 25) of the zero signal. The zero-left signal on bus 25 is inverted by inverter 26, and a single signal appears on bus 27 of the fourth-digit direct code. A zero signal on bus 25 also leads to switch trigger 9 with separate inputs. In this case, a zero signal appears at the output of the AND-NOT P element, and a single signal at the output of the NAND 10 element. Single inputs appear at both inputs of the NES-12 element, which leads to the formation of a zero signal at its output, which ensures the appearance of a single signal at the output of the 7-NE element (bus, 14 second-order return code). A single signal on the bus 14 is inverted by the inverter 15, and a zero signal appears on the bus 16 of the direct second-bit code. Thus, when the impact of the counter interference goes from state 0010 to state 1000. At the same time, the output signals on all elements correspond to

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the state of the counter after the impact of the eighth counting pulse.

Flip-flop trigger 20 seconds

5 separate inputs under the influence of external interference at the moment of time after the termination of the third counting pulse before the termination of the fourth pulse. At the same time, the output of the element IS-HE 22

10, a single signal appears, and the output of the NAND 21 element is zero, which leads to the formation of a single signal on the code of the NAND 23 element. At both inputs of the NAND 24 element

15, there are single signals, which determines the formation at its output (the 25-bit reverse code of the fourth bit) of the zero signal. A zero signal on bus 25 inverts 20 with an inverter 26, and a single signal appears on bus 27 of the direct code of the fourth bit. A zero signal on bus 25 also results in the formation of a single signal at the output of the IS-NOT 13 element. I-NOT 12 turns out to be single signals, which determines the appearance of a zero signal at its output, which, in turn, ensures the formation of a single signal. At the output of the NE-7 element (second-digit return code bus 14), A single signal bus 14 inverted inverted rtorium 15 and on tire 16

The 35 second-bit direct code appears a zero signal. A single signal on the bus 27 gets to the input element AND IS NOT 6, on the second input of which there is also a single

40 signal (bus 4). This causes the formation of a zero signal at its output. Thus, under the influence of interference, the counter changes from the OOP state to the state 1001. At

45 this output signals on all elements correspond to the state of the counter after the influence of the ninth counting pulse.

Flip-flop trigger 20

with separate entrances under influence -. At the time of the end of the eighth counting pulse before the end of the ninth pulse, the external interference is interrupted. At the same time, a zero signal is output at the output of the NAND-22 element, and a single signal at the output of the NOT-21 element. At both inputs of the element IS-NOT 23, there are single signals that, at 15

leads to the formation of a zero signal at its output, which determines the formation of a single signal at the output of the NE-24 element (bus 25, the fourth digit return code). A single signal on the bus 25 is inverted by an inverter 26, and a zero signal appears on the bus 27 of the direct code of the fourth bit. Thus, under the influence of interference, the counter changes from state 1000 to state 0000. At the same time, the output signals on all elements correspond to the state of the counter after the initial set-up (or the tenth count pulse). Such a failure can be registered and recorded.

Thus, all cases of possible switching under the influence of external interference of one of the triggers with separate inputs 9 or 20 are indicated. However, there are two time intervals when two of these triggers with separate inputs can be transferred at once. Consider these cases

Triggers 9 and 20 are thrown with separate inputs. A single signal on the bus 14 is inverted by inverter 15 ,. and on the bus 16 of the forward code of the second bit, a zero signal appears. This switches the second counting trigger 17, with the result that on the bus 18 of the forward code of the third bit appears a single signal, and on bus 19 of the reverse code the third bit is a zero signal, which, in turn, determines

external interference at the time of the formation of a single signal at

The AI after the initial setup (or at the end of the tenth counting pulse) before the end of the first pulse. At the outputs of the AND-NE elements 11 and 22, there are single signals, and the outputs of the AND-NE elements 10 and 21 are zero. The output signal is zero. The element AND-NOT 10 leads to the formation of a single signal at the output of the element AND-NOT 12 "In this case, both the codes of the element AND-NOT 7 have a single signal, which leads to the formation of a zero signal at its output (bus 14 of the second return code)

The zero signal on the bus 14 is inverted by the inverter 15, and a single signal is formed on the bus 16 of the direct code of the second bit. A zero signal at the output of the NAND 21 element leads to the formation of a single signal at the output of the NAND 23 element. At the same time, both inputs of the NAND 24 element turn out to be single signals, which determines the formation at its output (the 25 reverse code bus bit) zero signal

output of the NE-24 element (fourth bit reverse code bus 25), the Single signal on bus 25 is inverted by inverter 26, and on bus 27

The 35 code of the fourth bit is a zero signal. Thus, under the influence of interference after the transition process, the counter goes from state 0000 to state

40 0100. At the same time, the output signals on all elements correspond to the state of the counter after the fourth counting pulse.

Flip-flops trigger 9

45. and 20 with separate inputs under the influence of external interference at the time point after the end of the second counting pulse before the end of the third counting pulse. At the same time at the outputs

50 elements AND-NOT 10 and 22 are single signals, and at the outputs of elements AND-NOT 11 and 21 are zero signals. A single signal from the output of the element AND-NOT 10 is fed to the input of the element IS-NOT 12. At the same time, at both inputs of the element AND-NO 12 there are single signals, which leads to the formation of a zero signal at its output, which is determined by the left. yu 15

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The zero signal on the bus 25 is inverted by the inverter 26, and a single signal appears on the bus 27 of the direct code of the fourth bit. The zero signal on bus 25 determines the switching of flip-flop 9 with separate inputs, with the result that a zero signal appears at the output of the NAND element 11, and a single signal at the output of the NAND 10 element. In this case, both inputs of the NAND 12 element are provided with single signals, and a zero signal is generated at its output, which determines the occurrence of a single signal at the output of the element that is NAND 7 (second-order return bus 14)

A single signal on bus 14 is inverted by inverter 15 ,. and on the bus 16 of the forward code of the second bit, a zero signal appears. This switches the second counting trigger 17, with the result that on the bus 18 of the forward code of the third bit a single signal appears, and on the bus 19 of the reverse code of the third bit yes - zero signal, which, in turn, determines

forming a single signal on

output of the NE-24 element (fourth bit reverse code bus 25), the Single signal on bus 25 is inverted by inverter 26, and on bus 27

The 35 code of the fourth bit is a zero signal. Thus, under the influence of interference after the transition process, the counter goes from state 0000 to state

40 0100. At the same time, the output signals on all elements correspond to the state of the counter after the fourth counting pulse.

Flip-flops trigger 9

45. and 20 with separate inputs under the influence of external interference at the time point after the end of the second counting pulse before the end of the third counting pulse. At the same time at the outputs

50 elements AND-NOT 10 and 22 are single signals, and at the outputs of elements AND-NOT 11 and 21 are zero signals. A single signal from the output of the element AND-NOT 10 is fed to the input of the element IS-NOT 12. At the same time, both inputs of the element AND-NO 12 are provided with single signals, which leads to the formation of a zero signal at its output, which

17

a single signal on the output of the EL-NE-7 (bus I4 is the reverse code of the second bit). A single signal on the bus 14 is inverted by the inverter 15, and a zero signal appears on the bus 16 of the direct second-bit code.

A zero signal at the output of the element IS-NOT 21 leads to the formation of a single signal at the output of the element: that AND-NOT 23, On both inputs of the element AND-NOT 24 there are single sins, which leads to the appearance of its output 8 (bus 25 of the return code fourth bit) zero signal The zero signal on bus 25 is inverted by inverter 26, and a direct signal on bus 27 of the fourth code is a single signal. When the inverter 15 is switched, a second counting trigger 17 is triggered, resulting in the fourth direct code 18 of the fourth bit unit appears signal, and on bus 19 - zero signal.

A zero signal on bus 19 results in the output of the IS-NO 24 element (bus 25 of the fourth return code) of a single signal. A single signal on the bus 25 is inverted by an inverter 26s and a zero signal appears on the bus 27 of the direct code of the fourth bit. . Thus, under the influence of interference, the counter changes from the state of 0010 to the state 0100. At the same time, the output signals on all elements correspond to the state of the counter after the fourth counting pulse.

Thus, the proposed schemes for a binary-decimal counter in code 8-4-2-1 exclude the possibility of any hidden forbidden state, since its transitions are defined and. appear unambiguously in its output signals. In this case, the meter is completely absent.

Claims (1)

Formulaisob. eteni 50 45 Binary-decimal counter in code 8 - 4 - 2 - I, containing two counting triggers, two asynchronous RS-triggers with separate inputs, two three-input elements AND-NOT, five two-input elements AND-NOT, two inverters, input counting signals of the first 0 2474 18 the counting trigger is connected to the input bus, the installation input to O is connected to the initial installation bus, the inverse output is connected to the first digit return code bus, and the direct output is connected to the first digit straight code bus, to the first input of the second three-input element I- Not with the first input of the second two-input element NAND, the second. the input of which is connected to the direct code bus of the fourth bit and to the output of the second inverter, and the output to the first input of the fourth two-input I-NE element and to the first input of the zero setting of the first asynchronous RS flip-flop, the inverse output of which is connected to the second input of the fourth two-input element AND-NOT, the output of which is connected to the first input of the fifth two-input element AND-NOT, the second input of which is connected to the third-order return code, the inverse output of the second counting trigger and the installation input of the unit n the first- asynchronous RS-flip-flop, a second set input which is connected to the bus-zero initial installation, installation in the entrance in the second- 0 five five 0 0 the first input, the zero input of the second asynchronous RS flip-flop, the inverse output of which is connected to the first input of the third two-input NAND element, the second input of which is connected to the second input of the zero setting of the second asynchronous RS flip-flop, the installation input of which is connected with the output of the second three-input element IS-NOT, the second input of which is connected to the return code bus of the fourth bit, to the output of the fifth two-input element AND-NOT, to the input of the second inverter and to the first input of the first three-in and the third input is connected to the second-order return code bus and to the input of the first inverter, the output of which is connected to the second-rate forward code bus, and to the input of the counting signals of the second counting trigger, whose direct output is connected to the bus third-party direct code, if different 5 by the fact that, in order to expand the scope by eliminating prohibited and hidden forbidden states, the second input of the first three-input element is NOT connected to the bus direct code of the second bit, the third input to the bus of the direct code of the first bit, and the output to the second input of the third two-input element AND-NOT, the code of which is connected to the first input of the first two-input element AND-NOT, the output of which is connected to the second code return code bus, and the second input - with the output of the second three-input NAND element, the second input of which is connected to the third input of the zero set of the second asynchronous short-circuit trigger. f |||.