JPS6317381B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data transmission system, and more particularly to a data transmission system in which information is transmitted using a serial bit transmission signal to which a synchronization code is added. Conventionally, there has been a data transmission system of this type that transmits information in a format as shown in FIG. In Figure 1, 1 is a start code with a unique pattern made up of multiple bits, 2
is data of fixed bit length and contains information to be transmitted from the transmitting device to the receiving device. 3 is a stop code having a similar format to start code 1 and a unique pattern. Start code 1, data 2 and stop code 3
constitutes one transmission unit, a so-called frame. The transmission signal sent from the transmitting device consists of a series of such frames, and the receiving device detects the start code 1 to decode the original information from the data 2, and detects the stop code 3 to decode the original information from the received data 2. Make information useful. In order to detect the start code 1 and stop code 3, the receiving device uses a pattern generation circuit that generates these patterns, the received transmission signal as content, the same number of bits as the pattern, and the bits of the pattern of the pattern generation circuit. A comparison circuit is provided to detect a match between the two. When detecting start code 1 in the initial state, a search for start code 1 is performed by checking the output of the comparator circuit every time one new bit of the transmission signal is received. When detecting stop code 3, start code 1 is used when detecting a fixed length frame whose length is known in advance.
A detection window is opened a predetermined time after the detection of , and it is checked whether a matching signal is output from the comparison circuit. As a result, when a coincidence signal is output, the information received as data 2 is considered valid, and when it is not, there is a possibility that synchronization has occurred, so the information received as data 2 is invalidated, that is, discarded. . Next, the receiving device starts searching for the start code 1 described above from the initial state. In conventional data transmission systems, when a stop code cannot be detected as described above, the system returns to the initial state and searches for a start code. There is a drawback that if the code is detected incorrectly in succession, the incorrect data becomes valid. The present invention was made to eliminate the above-mentioned drawbacks of the conventional system, and the operating state of the receiving device is determined based on the degree of matching of synchronization code patterns and the number of code errors in data bits. There are two states: a first state in which the synchronization code is searched, a second state in which the synchronization code is estimated to be in the synchronization state and a synchronization code detection operation is performed at a predetermined timing, and a synchronization code is detected in the predetermined timing when the synchronization code is determined to be in the synchronization state. performs a detection operation, divides the received data into a third state in which it is valid, sets transition conditions to the upper state so as to make the transition conditions from the first state to the second state the strictest, and By setting the conditions for transition to a lower state so as to keep the retention conditions of The purpose of the present invention is to provide a data transmission method that provides highly reliable data transmission. An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows the format of the transmission signal.
is a 24-bit synchronization code having a unique pattern with sharp autocorrelation, and 5 is data of a fixed number of bits (for example, 144 bits, of which 48 bits are check bits) containing information to be transmitted. FIG. 3 shows a block diagram of a receiving apparatus for receiving a transmission signal having the format shown in FIG. In Figure 3, 6 is a 24-bit shift register that inputs the transmission signal bit-serial, 7 is a pattern generator that generates the same pattern as the synchronization code of the transmission signal, and 8 is an exclusive OR of 24 circuits. a comparison circuit 9 consisting of a gate and detecting a match between each bit of the shift register 6 and the pattern generator 7;
10 is a 24-bit shift register that leads the output signal of comparison circuit 8 to a parallel input, converts it into a serial signal, and outputs it, and 10 is a 5-bit counter that counts the "0" bit output from shift register 9. be. The count result of the counter 10 is sent to a processor (CPU) not shown.
Reference numeral 11 denotes an 8-bit register that latches the data stored in the shift register 6 (containing data 5 of the transmission signal) by means of a strobe. The data in register 11 is sent to the processor. The clocks for operating the shift registers 6 and 9 and the strobe generating circuit for latching the register 11 are not the gist of the present invention and may be well-known ones, so they are not shown. Also,
The processor may also be of the ordinary stored program type. Next, the operation will be explained. The received transmission signal is sampled bit by bit by a clock and input to the shift register 6. shift·
The contents of the register 6 are compared with the pattern of the pattern generator 7 by a comparator circuit 8, and bits that match become "0" and bits that do not match become "1" and are input to a shift register 9. The contents of shift register 9 are sent to counter 10 and the number of "0" bits is counted. The count result S of count 9 is sent to the processor. The processor verifies the data (96 bits) read 8 bits at a time from the register 11 using the check bits (48 bits) added thereto, and counts the number of detected code error bits. Denoting this count result as t, the count results S and t are processed by the processor as described below. FIG. 4 is a state transition diagram illustrating the operating state of the receiving device. The operating state of the receiving device is synchronization code 4.
Initial state ST1 searching for , synchronization code 4
It is estimated that the receiving device is in synchronization, that is, it is assumed that the receiving device is in sync. State ST3
It can be divided into State ST1 is the count number S of the counter 10,
With the preset constant S ₁ (the maximum number of S ₁ is 24),
When S<S ₁ (transition T ₁₁ ), S when in state ST2
<S ₁ or t ₃ <t (transition T ₂₁ ), and when S<S ₁ or t ₁ <t in state ST3 (transition T ₃₁ ). In state ST1, each time the shift register 6 newly inputs one bit of the transmission signal, the contents of the shift register 9 are read into the processor via the counter 10, and the synchronization code 4 is searched. As a result, when S ₁ ≦S, the transition
By _T12 , the state moves to the upper state ST2. In state ST2, S ₁ ≦S and t ₄
<t≦t ₃ (transition T ₂₂ ), when S ₁ ≦S in state ST1 (transition T ₁₂ ), and the state
This occurs when S ₁ ≦S and t ₂ <t≦t ₁ in ST3 (transition T ₃₂ ). In state ST2, it is estimated that the receiving device is in synchronization, so counter 1 is set at the timing when synchronization code 4 should be detected.
Examine the contents of shift register 9 via 0.
As a result, when the count number S becomes S<S ₁ or t ₃ <t (transition T ₂₁ ), the state returns to the lower state ST1, and when S ₁ ≦S and t≦t ₄ (transition
T ₂₃ ) transitions to the highest level, that is, the synchronous state ST3, and the data read from the register 11 becomes valid. In state ST3, S ₁ ≦S and t≦
t ₂ (transition T ₃₃ ) and when S ₁ ≦S and t≦t ₄ in state ST2 (transition T ₂₃ ), the data 5 read into the processor via the register 11 is Assume that the information is valid. At this time, if there is a code error in data 5, correction processing is performed using check bits (48 bits) included in data 5. However, in state ST3
When S ₁ ≦S and t ₂ <t≦t ₁ , it is a lower state.
Return to ST2 (transition T ₃₂ ) and again S < S ₁ or t ₁ < t
When it becomes, it returns to the lowest state ST1 (transition
_T31 ). In state ST3, the contents of the counter 10 are read at the same timing as in state ST2, that is, the synchronization detection window is opened and the contents are examined. The correspondence between transitions T ₁₁ to T ₃₃ and count numbers S and t is shown in a table.

[Table] For example, in state ST3, S ₁ ≦S and t ₂ <
When t≦t ₁ , it is considered that part of data 5 has changed due to temporary noise, so the state
Return to ST2 and wait for detection of the next synchronization code 4. In the detection of the next synchronization code 4, even if the detection window is opened at a predetermined timing, as long as there is no continuous noise, the conditions S ₁ ≦S and t≦t ₄ will be satisfied with sufficient probability. So, transition T ₂₃ causes state ST
3, and the data read into the processor is valid. Such an operation shortens the time required to achieve synchronization compared to the case where synchronization is acquired again from the initial state. As described above, according to the present invention, the operating state of the receiving device is estimated to be the first state in which the synchronization code is searched bit by bit according to the degree of code error in the synchronization code and the data, and is in the synchronization state. The state is divided into a second state in which the synchronization detection window is opened at the timing of , and the conditions for transition to the lower state are set so that the conditions for maintaining the third state are the most relaxed, making it easy to return to and maintain the synchronized state, and shorten the time it takes to reach the synchronized state from the initial state. This has the effect of realizing highly efficient and reliable data transmission.

[Brief explanation of the drawing]

FIG. 1 is a format diagram of a transmission signal in a conventional data transmission system, FIG. 2 is a format diagram of a transmission signal in a data transmission system of the present invention, and FIG.
The figure is a block diagram of a receiving apparatus using the data transmission system of the present invention, and FIG. 4 is a state transition diagram of the receiving apparatus shown in FIG. 3. 6, 9...Shift register, 7...Synchronization pattern generator, 8...Comparison circuit, 10...Counter, 11...Register.

Claims (1)

[Claims] 1. In a data transmission system that continuously transmits a transmission signal consisting of a synchronization code formed from a plurality of bits and having a unique pattern, and data formed from a fixed number of bits and containing the information to be transmitted. , the number S of bits that match the above-mentioned pattern and a plurality of bits corresponding to the above-mentioned synchronization code in the series of transmission signals received by the receiving device, the code of the data detected by the check bit included in the above-mentioned data; The number of error bits t and the constant S ₁ ,
S<S ₁ due to t ₁ to t ₄ (t ₄ < t ₃ < t ₂ < t ₁ )
When S ₁ ≦S and t ₄ <t≦t ₃ , then S<S ₁ or
When t ₃ < t, S ₁ ≦S and t≦t ₂ , then S
<S ₁ or t ₁ <t, the synchronization code is searched for each time a bit of the transmission signal is received.
state, when S ₁ ≦S in the first state, when S ₁ ≦S and t ₄ <t≦t ₃ , S ₁ ≦
If S and t≦t ₂ , then S ₁ ≦S and t ₂ <t≦t ₁ , the pattern is matched with the plurality of bits of the transmission signal corresponding to the synchronization code at a predetermined timing. The second state to be examined and when S ₁ ≦S and t≦t ₄ in the second state and S ₁ ≦S
And when t≦ _t2 , a third state is set in which a match with a plurality of bits of the transmission signal corresponding to the synchronization code is checked at a predetermined timing and the received data is made valid. data transmission method.