JPH09271000A - Data retrieval circuit for teletext - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data retrieval circuit for digital closed caption suitable for one chip without the need for use of a phase locked loop(PLL) and a voltage controlled oscillator(VCO) or the like. SOLUTION: A frequency divider circuit 3 consisting of a counter 3a and a decoder 3b frequency-divides a CPU (CLOCK) to generate a sampling clock (SAMPLE) corresponding to a period of a closed caption signal (CCDD) to give the closed caption signal to a register 4. In this case, in order to prevent deviation between the sampling clock and the closed caption signal, an edge detector 2 detects a transition edge of the closed caption signal to generate an edge detection signal (VEDGE) to reset the counter 3a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for searching character data used for closed caption type character broadcasting for superimposing character information on a television signal.

[0002]

2. Description of the Related Art The closed caption system is a system for transmitting character information by inserting a closed caption signal into a vertical blanking period of a television signal. This closed caption signal is a 503 KHz NRZ signal,
CR that synchronizes the reference clock to capture data
An I (clock run-in) signal, a 3-bit PAC (preamble address code) signal for identifying a transmission character type such as English or Japanese, and a 16-bit data signal indicating actual character data are arranged in this order.

In a data search circuit used for reading a closed caption signal, a sampling clock of 503 KHz is used to synchronize this with a CRI signal, and a 3 + 16 bit PAC signal and a data signal are shifted according to the synchronized sampling clock. It is designed to be taken into the register. A PLL (phase locked loop) or a VCO (voltage controlled oscillator) is usually used for synchronization of the sampling clock at this time.

[0004]

PLLs and VCOs require analog circuits, and external adjustment components such as capacitors and resistors are essential even when they are integrated into LSIs. Therefore, a one-chip microcomputer LSI with limited number of terminals and circuit scale
Not suitable for. Therefore, in the present invention, the PLL
To provide a digital closed caption data search circuit suitable for one-chip integration without using a VCO or the like.

[0005]

Focusing on the fact that the closed caption signal has a relatively low frequency of 503 KHz, it is possible to generate and use a sampling clock by dividing the CPU clock. In this case, if there is an error in the period of the sampling clock and the closed caption signal, the error may be within the practical range that does not affect the sampling.

That is, according to the present invention, in the data search circuit for reading the closed caption signal, the CPU clock is divided by using the dividing circuit to generate the sampling clock corresponding to the cycle of the closed caption signal. It is characterized in that a closed caption signal is taken into a register in accordance with the sampling clock. In this case, in order to prevent the data signal and the sampling clock from deviating from each other, it is preferable to detect the transition edge of the closed caption signal and reset the frequency dividing circuit. Even if the sampling clock that completely matches the cycle of the closed caption signal cannot be obtained by the frequency division by resetting the frequency division circuit for each transition edge, the frequency division circuit counts the CPU clock for each transition edge of the closed caption signal. Since it is possible to newly start the operation and prevent the deviation from being accumulated, the deviation of the sampling clock can always be kept within the practical range. That is, the sampling clock is 1 of the CPU clock for the closed caption signal.
Since it can be generated synchronously within the error range within the clock,
No PLL required.

If the CPU clock having a high frequency is thus divided to generate the sampling clock, the synchronization by the CRI signal is not necessary and therefore the CRI signal is unnecessary, but when the CRI signal is present, it is unnecessary. It is necessary to prevent the data signal from being taken into the register. To do this, from the frequency divider circuit to C
A mask signal may be generated for each pulse of the RI signal, and the register may be cleared by the mask signal.

Further, if the same logic continues in the data signal in the closed caption signal, the frequency divider circuit reset cannot be applied for each transition edge of the closed caption signal. At this time, if there is a deviation between the closed caption signal and the sampling clock, they will be accumulated. Therefore, in order to prevent this, the data length detection signal of the cycle corresponding to one pulse width of the data signal is also divided by the frequency divider circuit. It is more certain to perform the self-resetting of the frequency dividing circuit based on the data length detection signal. That is, according to this, even if the same logic continues in the data signal, the frequency divider circuit can be reset at the data pulse break, so that the deviation of the sampling clock is corrected for each pulse of the data signal, and the deviation is prevented from being accumulated. To be done.

According to the present invention as one mode of the data search circuit having such a function, a counter which is reset at the data pulse break of the closed caption signal and starts counting the CPU clock, and the data pulse according to the output of the counter. Provided is a data search circuit including a decoder that generates a sampling pulse at a timing corresponding to a half width and a register that captures a closed caption signal by the sampling pulse. The counter can be reset for each data pulse by using the above-described method. That is, the counter is reset by detecting the transition edge of the closed caption signal, and the decoder outputs data at the timing corresponding to the data pulse width according to the output of the counter. It suffices to generate a long detection pulse and reset the counter.

[0010]

1 is an explanatory diagram of a closed caption signal. This closed caption signal is inserted in the vertical blanking period of the television signal, and first has a 7-pulse CRI signal and then a 3-bit PAC signal.
The 16-bit data signal including the parity continues. Conventionally, as shown in the figure, CR
The sampling clock is synchronized with the I signal, and the PAC signal and the data signal are fetched with the sampling clock. Normally, the data pulse of the PAC signal and the data signal has a pulse width twice that of the CRI signal.

FIG. 2 is a block diagram showing an embodiment of a data search circuit for such a closed caption signal. The television signal is first input to the level slicer 1 by the CMOS comparator, whereby the closed caption signal (CCDD) is taken out. The extracted closed caption signal is passed through the edge detector 2 to detect the rising and / or falling transition edges of each pulse, and an edge detection signal (VEDGE) is generated. This edge detector 2 has a CPU clock (C
LOCK) is a clock-type edge detection circuit.
The generated edge detection signal is used to reset the frequency dividing circuit 3 and the shift register 4.

The frequency dividing circuit 3 includes a counter 3a that counts with a CPU clock, and a decoder 3b that outputs a sampling clock (SAMPLE), a mask signal (EMASK), and a data length detection signal (FULL) according to the output of the counter 3a. , Are provided. Counter 3a
Is reset by the output of the NOR gate 5 which logically operates the edge detection signal and the data length detection signal. The decoder 3b is configured using RS-FF,
The sampling clock output from now on becomes the shift clock of the shift register 4, and the mask signal is operated by the edge detection signal and the NAND gate 6 to clear the shift register 4.

The shift register 4 has 19 (= 3 + 16)
With a bit configuration, the closed caption signal is shifted in by the application of the sampling clock, stored, and transmitted to the CPU.

The CPU clock is 10 MHz in this example.
Then, by dividing this by 20 by the frequency dividing circuit 3,
Generate a sampling clock of 0 KHz. The pulse width of this sampling clock is set to be as short as necessary, so that the first sampling pulse is generated at the timing corresponding to 1/2 cycle of the closed caption signal after the reset of the frequency dividing circuit 3. That is, each pulse of the sampling clock is designed to occur at approximately the center of the data pulse of the PAC signal and the data signal. The mask signal is generated at the same cycle and timing as the sampling clock, but its pulse width is longer than the pulse of the sampling clock. The data length detection signal is also set to have the same cycle as the sampling clock, but the first data detection pulse is generated at the timing corresponding to one cycle of the closed caption signal from the reset of the frequency dividing circuit 3, and the timing is set to the data It occurs at the transition edge of the signal.

FIG. 3 shows C of the closed caption signal.
Timings of the edge detection signal, the mask signal, the sampling clock, and the data length detection signal in the RI signal period are shown, and FIG. 4 shows the PA of the closed caption signal.
The timing of each signal in the C signal and data signal periods is shown.

In the CRI signal period of FIG. 3, since the pulse width of the CRI signal is 1/2 of the data pulse, the edge detection signal is generated exactly at the generation timing of the sampling clock and the data length detection signal. Since the frequency dividing circuit is reset by this edge detection signal, generation of the sampling clock and the data length detection signal is suppressed. On the other hand, since the mask signal has a long pulse width, the mask signal is once generated immediately before the generation of the edge detection signal and then is suppressed by the edge detection signal. That is, the mask signal is always generated at least every pulse of the CRI signal, and in this example, the edge detection signal is generated at both the rising edge and the falling edge of the closed caption signal. A mask signal is generated at every transition edge of the CRI signal.

The edge detection signal and the mask signal are NAND
Since the signals are input to the clear terminal of the shift register 4 via the gate 6, the signals are temporarily brought to the high level at the same time to perform the clear. Therefore, the fetching of the CRI signal in the register is prevented. Further, in this example, the generation of the sampling clock is also suppressed, so that the register fetching can be prevented more reliably.

In the PAC signal and data signal periods of FIG. 4, since the edge detection signal is generated with the data pulse width, generation of the mask signal, the sampling clock and the data length detection signal is allowed. Since the mask signal and the sampling clock are generated at the above timing and cycle, after the reset by the edge detection signal, the sampling pulse is generated at about the center of the data pulse and applied to the shift register 4. In this case, since the mask signal is NANDed with the edge detection signal by the NAND gate 6, the shift register 4 is not cleared. Therefore, the closed caption signal is taken into the shift register 4 by the sampling pulse.

Here, since the sampling clock is 500 KHz as described above, an error of 0.6% occurs per bit of the data signal, and if the data contains parity of 8 bits, the maximum is 0.6 × 8 = 4. An error of 0.8% can occur. However, since the sampling pulse is generated at a timing corresponding to half the data pulse width and the sampling is performed substantially at the center of the data pulse, there is no problem even if the maximum error occurs. In addition, the frequency division circuit 3 is reset by the edge detection signal at each transition edge of the closed caption signal to prevent error accumulation, and even when data of the same logic continues, the data length is set as follows. Since each data pulse is reset by the detection signal, deviation of the sample timing due to error accumulation is reliably prevented.

That is, as shown in FIG. 4, when data "1" continues for 2 bits in the data signal, since the transition edge of the data signal does not occur, the frequency dividing circuit 3 is not reset by the edge detection signal. Instead, in this case, the data length detection signal is generated from the decoder 3b at exactly one cycle of the data signal, that is, at the data pulse delimiter.
Since the voltage is applied to the counter 3a via the R gate 5, the frequency dividing circuit 3 itself resets itself. That is, if the following data are different data, resetting is performed by the edge detection signal, and if the following data is the same data, self-reset is performed by the data length detection signal at intervals of one data to prevent the accumulation of deviations. . When the edge detection signal is generated in this example, the frequency dividing circuit 3 is reset, so that the data length detection signal is suppressed.

By thus resetting the frequency dividing circuit 3 at each transition edge of the closed caption signal, the counter 3a always starts counting anew at each transition edge. That is, as shown in FIG.
Due to the error within one clock of the U clock, the closed caption signal and the sampling clock are generated in synchronization. Since the CPU clock has a high frequency, one clock is very short. Therefore, if the CPU clocks are synchronized in this range, the sampling timing will not be out of order.

[0022]

According to the present invention, it is possible to provide a digital closed caption data search circuit suitable for one-chip LSI without using a PLL or VCO. In addition, since an analog circuit is not used, even if it is made into one chip, no external parts are required, which is advantageous in terms of assembly workability and cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a closed caption signal.

FIG. 2 is a block diagram of a data search circuit according to the present invention.

FIG. 3 is a waveform diagram showing signal timing in a CRI signal period.

FIG. 4 is a waveform chart showing signal timing in a PAC signal and a data signal period.

FIG. 5 is a transition edge of the closed caption signal and C.
Explanatory drawing about the relationship with PU clock.

[Explanation of symbols]

 3 Frequency divider 3a Counter 3b Decoder 4 Shift register CCDD Closed caption signal VEDGE Edge detection signal CLOCK CPU clock SAMPLE Sampling clock EMASK Mask signal FULL Data length detection signal

Claims (6)

[Claims] 1. A data search circuit for reading a closed caption signal, wherein a CPU is provided using a frequency dividing circuit.
A data search circuit characterized in that a sampling clock corresponding to the cycle of a closed caption signal is generated by dividing the clock, and the closed caption signal is loaded into a register in accordance with the sampling clock. 2. The data search circuit according to claim 1, wherein the frequency dividing circuit is reset by detecting a transition edge of the closed caption signal. 3. The frequency division circuit generates a data length detection signal having a period corresponding to the pulse width of the data signal in the closed caption signal, and the frequency division circuit resets itself by the data length detection signal. Data search circuit. 4. A CRI in a closed caption signal.
Generate a mask signal from the frequency divider circuit for each pulse of the signal,
The register is cleared by the mask signal.
The data search circuit described in any one of 1. 5. A data search circuit for reading a closed caption signal, a counter which is reset at the break of the data pulse of the closed caption signal and starts counting the CPU clock, and a data pulse of the closed caption signal according to the output of the counter. A data search circuit comprising: a decoder that generates a sampling pulse at a timing corresponding to a half width; and a register that captures a closed caption signal by the sampling pulse. 6. A counter is reset by detecting a transition edge of the closed caption signal, and a decoder generates a data length detection pulse at a timing corresponding to the data pulse width of the closed caption signal to reset the counter. The data search circuit according to claim 5.