JP3048866B2 - Automatic data rate recognition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data speed automatic recognition circuit for automatically detecting the start speed of data sent from a partner terminal.

[0002]

2. Description of the Related Art Since the data start speed of a partner terminal connected to a modem or a terminal is various, it is necessary to detect the data start speed of the partner terminal on the data receiving side. As a method for this, a transfer method called an "AT" command method is known.

The "AT" command system is a command system for start-stop synchronization, and is a system in which "AT" is added before all commands. The transmission rate of the other terminal is detected by the letter "A" of the AT command sent from the other terminal, and the character length, presence / absence of parity,
And the stop bit length can be detected.

FIG. 7 is a time chart showing serial data of "A" (41H). After the start bit of the serial data, High corresponding to the bit width always comes. Therefore, the data transmission speed can be detected by measuring the start bit width.

As an example of such an automatic detection circuit, there is known an automatic start data speed recognition circuit disclosed in Japanese Patent Application Laid-Open No. Hei 3-259638. In this circuit,
When a character "A" (character code is 41H) or a character "a" (character code 61H) relating to the data speed is received from the partner terminal, data faster than the baud rate set on the device side or data of the same speed is received. The data transmission speed can be automatically recognized when sent.

More specifically, clock division is performed by a counter having a bit width of 1/2 N based on a clock N times the set speed, and serial data is shifted by a shift register using the N-divided clock. Then, speed detection set by the output pattern of the shift register is performed.
To detect a speed, for example, twice as high as the set speed, serial data is shifted by a shift register with a clock of N / 2 and the speed is detected based on the output pattern of the shift register.

[0007] In addition, a specific character relating to the data rate is sampled from the partner terminal at a set rate on the receiving side, and the transmission rate is detected from the reception result.
There is also known a method of correcting data to correct data according to the detected speed by a software program or the like.

[0008]

However, in the above-mentioned conventional data rate automatic recognition circuit, in order to detect various types of data rates, the shift register and the flip-flop for latching the judgment result are replaced by the data rate. You only need to have the kind. Further, in order to distinguish between uppercase "A" and lowercase "a", a shift register and an identification circuit are required twice.

The reception of a specific character relating to the data rate is performed when the result of any one of the identification circuits (flag) becomes true. The above-described process of writing the specific character is required.

Further, there are the following problems.

38.4K, 19.2K, 9600, 48
00, 2400, 1200, 600, and 300 BPS
It is assumed that it is necessary to automatically detect eight different speeds. For example, one of the maximum speeds (38.4 KHz) to be detected is 1
When counting based on a 6-times clock, as a simple consideration, as shown in FIG. 8, in the start bit period, 38.4 KBPS for 16 counts, 19.2 KBPS for 32 counts, 64 counts in the start bit period In this case, the speed can be automatically determined based on the count result, such as 9600 BPS. Not necessarily.

In the above-mentioned conventional example, in order to detect the data speed, serial data is converted into parallel data by a shift register for each type of speed to be detected, and the converted data matches the data sent by the transmission side. In order to detect the clock rate of the register as the detection speed, for example, when noise is sent to the serial data line as shown in FIG. 9, the automatic speed recognition is activated by this noise, and the phase of the clock of the shift register is affected by this noise. Therefore, the speed cannot be correctly detected thereafter.

Also, a specific character relating to the data rate sent from the partner terminal is sampled at a rate set on the receiving side, and the data transmission rate is detected from the received data, and the data transmission rate is detected by a software program or the like. Correcting the data to the correct data according to the speed would be very complicated.

The present invention has been made in view of such a problem, and it is not necessary to have a shift register or a flip-flop for latching a determination result only for the type of data speed. An object of the present invention is to provide a data rate automatic recognition circuit capable of accurately detecting a speed without being affected by noise or the like.

[0015]

A data rate automatic recognition circuit according to the present invention has a receiving terminal connected to a terminal capable of receiving a serial transmission of a character capable of specifying a data transmission speed on a receiving side in a start-stop synchronous manner. In a data rate automatic recognizing circuit which automatically recognizes a data transmission rate based on a start bit added to the head, the start bit time of the character is counted by a clock which is N times the maximum detectable data transmission rate. The counter and the partial bit string included in the counter output
Some, partially n bits (where n <the bit of the counter output)
And a means for determining the data transmission rate based on the number of data transmissions .

Further, the automatic data rate recognition circuit of the present invention has a character which can specify a data transmission rate on the receiving side serially transferred by a start-stop synchronization system from a connected terminal, and is added to the head of the character. a counter in the data rate automatic recognition circuit which is adapted to automatically recognize, that counts the start bit time of the character at N times the clock detectable maximum data transmission rate the data transmission rate based on the start bit that, the Mosquito
Part, which is a partial bit string included in the counter output
N bits (where n <the number of bits of the counter output)
Means for temporarily determining the data transmission rate based on the data transmission rate, means for generating a clock signal N times the temporarily determined data transmission rate, and the temporary determination based on the clock signal N times the temporarily determined data transmission rate. Means for determining whether the data transmission rate is true or false.

[0017] In either configuration described above, the portion
The fractional n bits are changed according to the data transmission rate to be detected.
It can be configured as follows.

According to the first configuration, the counter output
Is a partial bit string included in
(Where n <number of bits of the counter output)
In order to determine the data transmission speed, it is not necessary to have a shift register, a flip-flop for latching the determination result, etc. only for the type of data transmission speed in order to detect various types of data speeds, and to simplify the circuit. be able to.

According to the second configuration, a clock signal of N times the temporarily determined data transmission speed is generated, and the authenticity of the temporarily determined data transmission speed is determined based on the N times clock signal. Therefore, the data transmission speed can be accurately detected without being affected by noise or the like.

[0020]

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments.

FIG. 1 is a block diagram showing a data rate automatic recognition circuit. In this embodiment, one base clock is connected to the clock lines of all the flip-flops and various counters and control circuits are provided with enable signals (in the drawing, as input ports of each module so that the circuit can be easily formed into an LSI). The operation is controlled by ENA, ENB, EN, etc.). Also, at most 38.
Up to 4 KBPS (38.4 KHz) can be detected, and 4.9152 MHz is used as a base clock. For the purpose of automatic speed detection only, the character length, the presence / absence of parity, and the stop bit length are fixed in advance.

The circuit of FIG. 1 is one that is therefore <br/> constructed following idea.

That is, as described in the conventional example, it is not always possible to accurately receive a pulse width corresponding to the detection speed due to noise on the transmission line or frequency transition of the reference clock of the partner terminal. It is necessary to have a certain width. Also, if it is assumed that this circuit is formed as an LSI, the transmission data sent from the partner terminal is an asynchronous signal when viewed from this circuit.
As shown in (a), the transmission data is transferred to a reference clock (3
Flip-flops FF1 and F
It is necessary to synchronize with F2 and take in the counter (1). In this case, as shown in FIG. 3B, there can be synchronization outputs A, B, and C, so that the judgment criterion must be at least ±. A width for one clock is provided.

Therefore, the detection width is set to 38.4 KHz × 16.
Consider that the speed is determined based on ± 2 of the double clock, that is, the counter result as shown in Table 1.

[0026]

[Table 1]

In this state, the output Q [1
[1: 0], it is necessary to make a determination using all the bits, so that the circuit scale becomes large.

Further, the detection range is always ± 2 with respect to the reference value.
(Fixed value), the lower the data speed, the lower the ratio of the detectable speed to the reference speed. For example, 3
At 8.4K, (± 2/1) for 38.4KBPS
6) A speed in a range of × 100 = ± 12.5% can be detected, but in 300, (± 2/2) for 300 BPS
048) Only the speed in the range of × 100 = ± 0.097% can be detected.

Therefore, as shown in Table 2 below, the detection width of each speed is adjusted to the detection width in the case of 38.4 KHz.

[0030]

[Table 2]

According to Table 2, the smaller values of 14, 28, 56,... Are successively doubled values of the upper row, and the larger values of 18, 36,.
72... Are sequentially doubled values in the upper stage. To double a numerical value is to shift left by one bit in a binary number state. Then, the uppermost values 14 and 1
8 can be represented by 5 bits in a binary number. Therefore, Table 2 can be represented as shown in Table 3 below.

[0032]

[Table 3]

Note that Q [4: 0] is 0 to 4 of the counter.
All five bits of the bit are indicated, and Q [11: 7] indicates all five bits of the seventh to eleventh bits of the counter. Since the data transmission rate can be detected based on the five bit strings of the bit string obtained by bit-shifting the counter output,
In order to detect various types of data rates, it is not necessary to have only a shift register or flip-flop for latching the determination result, etc. of only the type of data transmission rate.Moreover, since all bits of the counter are not used, the circuit scale is reduced. Can be extremely small.

FIG. 3 is a diagram showing Table 3 in binary number representation and partial 5-bit representation with respect to Table 2.

Now, in FIG. 1, the counter (1)
Is a counter of the above Q [11: 7], and C not shown
Upon receiving a reception enable signal from the PU and an automatic speed mode signal for causing the present circuit to enter the automatic speed detection mode, the system enters a wait state for a start bit signal of serial data. In addition, 38.4K from sequencer (6)
A clock signal EN1 which is 16 times the frequency of Hz is input, counting starts when the start bit of serial data (SD1) falls, and ends when the start bit rises.

Counter (2) and counter (3)
Inputs from the sequencer (6) EN2 which is a clock signal 16 times the detected data transmission rate (undecided) and counts it. The output value of the counter (2) is
It is a value from "0000" to "1111" in binary,
The output value of the counter (3) is "00000" in binary.
To "11111". Both of these counters are used to verify data rate determination due to noise.

The counter (4) is used after data transmission is determined, and performs data sampling for verifying a designated data length.

Shift register (7) and FIFO
(8) After the data rate is determined, serial data from the other party is sampled, and FIFO is
Data is written in (8).

Next, the operation of the automatic data rate recognition circuit will be described with reference to FIGS. FIG. 4 is a flowchart showing the contents of control by the sequencer (6).
FIG. 6 is a timing chart exemplifying that when the serial data (SD1) includes noise, the influence of the noise can be avoided by the present configuration. FIG.
FIG. 6 is a diagram corresponding to FIG. 3 and showing conditions for determining a data rate.

In FIG. 4, S0 is in the idle state, and shifts to the J1 state by the reception enable signal and the automatic speed mode signal. In FIG. 5, A
This corresponds to the state transition indicated by 1.

In the J1 state, the counter (3),
Clear (4). In addition, serial data (SD
When the falling edge (start pulse) of 1) is detected, J2
Move to state. In FIG. 5, this corresponds to the state transition indicated by A2.

In the J2 state, 38.4 kHz 16
The double clock (EN1) is continuously output. Thus, the counter (1) starts counting. Thereafter, the state immediately shifts to the J3 state. In FIG. 5, A
This corresponds to the state transition indicated by 2.

In the J3 state, the rising of the start pulse is waited. When the rising of the start pulse is detected, the data rate is determined according to the condition 1 shown in FIG. If none of the conditions 1 is met, N1
Proceed to state. In FIG. 5, this corresponds to the state transition indicated by A3. On the other hand, if any of the conditions are met, J4
Proceed to state. In FIG. 5, this corresponds to the state transition indicated by A4.

When the serial data returns to LOW within a specific period in the transition to the N1 state, J3
It automatically returns to the state and plays the role of removing noise on the start pulse. In FIG. 5, this corresponds to the state transition indicated by A5. Also, LOW within a specific period
If it does not return to, the first detected start pulse is
It is regarded as noise, and the processing shifts to the J1 state to perform the data rate determination again. In the example of FIG. 5, this transition state does not exist.

When the state shifts to the J4 state, the state immediately shifts to the J5 state, and a clock signal (EN2) 16 times the data transmission rate determined (assumed) under the condition 1 is output. The counting of the counter (2) and the counter (3) is started by the signal EN2. In FIG. 5, this corresponds to the state transition indicated by A6.

In the J5 state, the output of the counter (2) is determined and the following processing is performed.

If the output of the counter (2) is 0 or more and 7 or less and the serial data is "LOW", the process returns to J3 and the measurement of the start pulse width is continued. That is, if the start pulse period has really ended and becomes “HIGH”, the serial data (about half of 16 pulses) does not reach the middle point (about half of 16 pulses) of the “HIGH” period by the provisional data transmission rate. SD1) should not be “LOW”, so in the state transition indicated by A4 in FIG.
The provisional data rate determined as meeting condition 1 of
Recognize that this is due to noise. The reason why the intermediate point is set is to consider frequency jitter of received data and the like. Then, clear the counter (2) (C
LR2 signal) and stop the EN2 signal.
In FIG. 5, this corresponds to the state transition indicated by A7.

On the other hand, if the output of the counter (2) is 7 and the EN2 signal is "HIGH", the state shifts to the J6 state. In FIG. 5, this corresponds to the state transition indicated by A8.

In the J6 state, a shift enable signal (signal name is SFTEN) of the shift register is output, and the counter (2) is cleared. Then J
Move to 7 states. In FIG. 5, this corresponds to the state transition indicated by A9.

In the J7 state, if the output of the counter (2) is 15 and EN2 is "HIGH", the flow shifts to the J8 state. That is, when the first bit of the start bit is normal, the output of the counter (3) is 14 to 1
In the range of 8, the serial data (SD1) should transition to the “LOW” state. The reason why the counter (3) is used to execute this is that the counter (2) is initialized in the J6 state. The reason why the output of the counter (3) is set in the range of 14 to 18 as described above is that ± 2 clocks are included in the judgment criterion in consideration of frequency jitter of received data and processing at a portion for synchronizing asynchronous input. Corresponding to having a width of

Therefore, in the J7 state, the output of the counter (3) exceeds 18, the output of the counter (3) is 19, and the serial data (SD1) is "HIGH".
If so, the part itself detected as the start bit is regarded as noise, and the state shifts to the J1 state.

In the J8 state, in addition to outputting the shift enable signal (SFTEN), the counter (2) is cleared, the EN1 signal is stopped, the detected speed is set in the register, and the transmission speed is automatically updated.

Thereafter, as shown in FIG.
State, J10 state,..., The data is sampled by the shift register (7) with a clock according to the detected data transmission speed, and the reception F is received every byte.
Data is written to the IFO (8).

By performing such processing, the serial data (SD1) shown in FIG. 5 has a noise of 38.4K / 2BP once because the serial data has noise.
Judged as S, but then correctly 38.4K / 4 = 960
0 BPS will be detected.

[0055]

As described above, according to the present invention,
It is not necessary to have only a shift register or flip-flop for latching the judgment result to detect various data speeds only for the data transmission speed type, and the circuit is simplified because not all bits of the counter are used. it can. Also, there is an effect that the reliability of automatic speed detection can be improved by automatically removing noise.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data rate automatic recognition circuit according to the present invention.

FIG. 2A is a circuit diagram showing a circuit for synchronizing an asynchronous input, and FIG.
FIG. 9 is an explanatory diagram showing a synchronization output when a width corresponding to a clock is provided.

FIG. 3 is an explanatory diagram showing each data transmission speed and a count number range for its determination.

FIG. 4 is a flowchart showing a state transition and control contents of a sequencer circuit in FIG. 1;

FIG. 5 shows that even if noise is present in the start bit, it is reliably 96
6 is a timing chart illustrating a case where a transmission rate of 00BPS is detected.

FIG. 6 is a diagram showing conditions for determining a transmission rate based on the result of the counter.

FIG. 7 is a timing chart showing serial data of “A” (41H).

FIG. 8 is a timing chart showing a principle of detecting a data transmission speed by a start bit.

FIG. 9 is an explanatory diagram showing a problem when noise is placed on a start bit.

[Explanation of symbols]

 1 counter 2 counter 3 counter 4 counter 6 sequencer 7 shift register 8 FIFO

Claims (3)

(57) [Claims] 1. A character which can specify a data transmission rate on a receiving side from a connected terminal is serially transferred in a start-stop synchronous manner, and the data transmission rate is adjusted based on a start bit added to the head of the character. In a data rate automatic recognition circuit adapted to automatically recognize, a counter for counting the start bit time of the character with a clock which is N times the maximum detectable data transmission rate, and a partial bit included in the counter output.
N bits (where n <counter output
Means for determining the data transmission rate based on the number of bits of the data rate. 2. A character which can specify the data transmission rate on the receiving side from the connected terminal is serially transferred in start-stop synchronization, and the data transmission rate is adjusted based on a start bit added to the head of the character. In a data rate automatic recognition circuit adapted to automatically recognize, a counter for counting the start bit time of the character with a clock which is N times the maximum detectable data transmission rate, and a partial bit included in the counter output.
N bits (where n <counter output
Method for temporarily determining the data transmission rate based on the number of bits
Stage and, means for generating a N times the clock signal of the data transmission rate temporarily determined, N of the temporary determined data transmission rate
Means for determining the authenticity of the tentatively determined data transmission rate based on a doubled clock signal. 3. The data transmission device according to claim 1, wherein said partial n bits are data transmission data to be detected.
3. The automatic data rate recognition circuit according to claim 1, wherein the data rate is changed in accordance with a feed rate.