JPH04351031A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To attain the communication by detecting a true synchronization pattern even when a false synchronization pattern having a same bit pattern as a synchronization pattern is in existence in an information data consecutively for a long time. CONSTITUTION:A coincidence detection circuit 2 checks a bit for each synchronization bit arrangement interval in PCM data stored in a shift register 1 in the frame synchronization circuit used for the PCM communication system. The result of check is sequentially stored in a cyclic register 3, a 1st synchronization candidate detected after the end of backward protection stage is regarded as a synchronization pattern and when it is discriminated that the pattern is a false synchronization pattern, the operation of regarding the synchronization candidate detected 2nd having been stored so far in the cyclic register 3 is repeated till the true synchronization pattern.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION The present invention is applied to synchronization pull-in means used in PCM transmission. In particular, it relates to means for avoiding false synchronization.

0002

2. Description of the Related Art Conventional circuits regard a bit pattern that matches a synchronization pattern a prescribed number of times as a synchronization signal. In other words, after applying guard by the rear protection circuit,
One of the remaining synchronization candidates is regarded as a synchronization signal, and if it turns out to be a false synchronization signal, the circuit is reset and the synchronization bit is searched again from the beginning, or backward protection continues until there is only one synchronization candidate. Was.

0003

[Problem to be Solved by the Invention] Such a conventional circuit has the drawback that if the PCM input data contains the same pattern as the synchronization pattern for a long period of time, the synchronization cannot be retracted forever. there were. Since there are synchronization candidates in addition to the true synchronization pattern, some methods either do not proceed to the next state until there is only one synchronization candidate, or
Another method is to first capture the false synchronization pattern in the PCM data, proceed to the next state, and perform, for example, a CRC (cyclic redundancy check) calculation, which results in many errors, resulting in false synchronization. Even if you reset the synchronization circuit and detect synchronization from the beginning after knowing that the synchronization is Depending on the timing relationship between the reset of the circuit and the false synchronization pattern, there is a drawback that the false synchronization pattern is always captured.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a frame synchronization device that reliably detects a true synchronization pattern from among a plurality of synchronization candidates and guarantees data transparency. shall be.

[0005]

[Means for Solving the Problems] The present invention is connected to a synchronization signal determining circuit that determines the authenticity of a synchronization signal and generates a control signal when the determination result is false, and inputs PCM data. In a frame synchronization circuit that includes a first terminal and a second terminal that provides a frame pulse to the synchronization signal determining circuit, there is provided a shift register that holds PCM data that passes through the first terminal; A coincidence detection circuit that compares the bits located in the synchronous bit interval included in the PCM data with the synchronous pattern, and a cyclic register having the number of bits equal to the synchronous bit interval and in which all of the bits are set in the initial state. , a means for resetting the corresponding bit of the cyclic register when the comparison result in the coincidence detection circuit does not match; a free-running counter that supplies a pulse with a period equal to the synchronous bit interval to the second terminal; and backward protection. means for driving the free-running counter in accordance with a set bit first output from the cyclic register after counting the time necessary for and means for resetting the corresponding bit of the cyclic register at the timing of the output pulse of the free-running counter during a period in which the control signal is latched, and subsequently resetting the free-running counter and the latched control signal. It is characterized by

[0006] Here, it is desirable to provide an initial state setting means for counting the number of set bits in the cyclic register and setting the own frame synchronization circuit to an initial state when the counted value indicates zero.

[0007]

[Operation] A coincidence detection circuit checks the bits at each synchronous bit arrangement interval from the PCM data accumulated in the shift register, and sequentially stores the test results in a circular register.
The first synchronization candidate detected after the end of backward protection is regarded as a synchronization pattern, and when it turns out to be a false synchronization, the second synchronization candidate detected until then, which was held in the circular register, is regarded as a synchronization pattern. Repeat until a synchronization pattern is detected. This makes it possible to detect a true synchronization pattern even if a false synchronization pattern having the same bit pattern as the synchronization pattern continues to exist in the information data for a long time.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram of this embodiment. As shown in FIG. 1, this embodiment is a PCM that is connected to a synchronization signal determining circuit that determines the truth of a synchronization signal and generates a control signal when the determination result is false, and that inputs PCM data. A frame pulse output terminal 53 that provides a frame pulse to the input terminal 50 and this synchronization signal judgment circuit.
Furthermore, as a feature of the present invention, P
a shift register 1 that holds PCM data via a CM input terminal 50; a coincidence detection circuit 2 that compares bits located at synchronous bit intervals included in the PCM data held in the shift register 1 with a synchronous pattern; a cyclic register 3 having a number of bits equal to the synchronous bit interval, all of the bits being set in an initial state;
An AND circuit 11 is a means for resetting the corresponding bit of the cyclic register 3 when the comparison result in the coincidence detection circuit 2 is non-coincidence, and an AND circuit 11 is a means for resetting the corresponding bit of the cyclic register 3 when the comparison result in the coincidence detection circuit 2 does not match. A running counter 6, a timer 5 and an AND circuit 1 which are means for driving the free running counter 6 according to the set bit first output from the cyclic register 3 after counting the time required for backward protection.
4, when a control signal is input from the synchronization signal determining means, this control signal is latched, and the corresponding bit of the cyclic register 3 is set at the timing of the output pulse of the free-running counter 6 while this control signal is latched. Then, the latch 7, NAND circuit 8, and AND circuit 12, which are means for resetting the free-running counter 6 and the latched control signal, and the number of set bits in the cyclic register 3 are counted, and the count value is zero. It includes a candidate number counter 4, an inverter 9, and an AND circuit 13, which are initial state setting means for setting the own frame synchronization circuit to an initial state when the frame synchronization circuit is displayed.

Next, the operation of this embodiment will be explained. PC
PCM data input from the M input terminal 50 is stored in the shift register 1 and sequentially shifted bit by bit. Leader lines S1, S2, . As an example, assume that the synchronization pattern is a repetition of 6 bits of "0, 0, 1, 0, 1, 1", and that these are inserted 1 bit at a time in 772 bit intervals, and a total of 4 bits are checked at the same time. Assuming that there are four leader lines S1, S2, S3, and S4, the total bit length of shift register 1 is 772 bits x 3 blocks = 2316 bits, and one bit is taken out every 772 bits and sent to the coincidence detection circuit. Sent to 2.

An example of the coincidence detection circuit 2 is shown in FIG. Six 4-input AND circuits are provided so that the synchronization pattern can be detected from any bit position, and each input is equipped with an inverter that corresponds to the four bits of the synchronization pattern that are shifted by one bit. When any of the AND circuits detects a match with the synchronization pattern, the output of that AND circuit becomes "1" and the output line M of the 6-input OR circuit becomes "1". When all six AND circuits detect non-coincidence, the output line M becomes "0". If one of the six AND circuits detects a match when there is no bit error, the AND circuit that detects a match will be shifted one by one for every 772 bits and circulate, so the output line M "1" appears every 772 bits. If there are two synchronization candidates, there are two patterns of "1" that appear on the output line M in a 772-bit period, so if we limit the time to the 772-bit period, the "1" that appears on the output line M during this time ' will be 2. That is, the number of "1"s within 772 bit time indicates the number of synchronization candidates.

Returning to FIG. 1, the bit length of the cyclic register 3 is 772 bits, and initially all are "1". Since the output of the NAND circuit 8 is initially "1", the AND circuit 12 is open, and after the start of the test, the match circuit output line M becomes "1".
1", the output of the AND circuit 11 also becomes "1", and the bit corresponding to the bit position currently being checked in the cyclic register 3 remains "1". Conversely, when the output line M is "0", the corresponding bit of the cyclic register 3 is rewritten to "0" and stored. Once rewritten to "0", that bit position is not considered as a synchronization pattern, and even if the output line M of the coincidence detection circuit 2 becomes "1" from now on, the output of the AND circuit 11 becomes the output "0" of the cyclic register 3. ” causes “0”
, and the corresponding bit of the cyclic register 3 remains "0". The candidate number counter 4 counts the number of synchronization candidates, and the initial count value is "772". The count value represents the number of "1"s in the circular register 3, and when the output line M of the coincidence detection circuit 2 is "0" and the output of the circular register 3 is "1", the corresponding bit of the circular register 3 is teeth"
At the same time, the output of the AND circuit 13 connected to the inverter 9 becomes "1" and the count value counts down by "1". In this way, each time "1" in the cyclic register 3 is rewritten to "0", the count value decreases by "1". When all the bits of the cyclic register 3 become "0", the count value also becomes "0". This indicates that there are no synchronization candidates left. This is a case where an error occurs in the true synchronization bit due to a bit error and it cannot be captured. In this case, the synchronization circuit is reset and everything is returned to its initial state, and the test is started again.

When the timer 5 counts the time required for backward protection from the start of the test, the output of the timer 5 becomes "1" and the AND circuit 14 is opened. After that, the first "1" appearing from the cyclic register 3 is regarded as a synchronization candidate, and the AND circuit 1
The output of 4 becomes "1" and drives the self-running counter 6. Free running counter 6 is frame synchronization bit interval 772
A 1-bit pulse is generated for each bit. This is output from the frame pulse output terminal 53 as a frame synchronization pulse. Once driven, the self-running counter 6 is configured to not accept any further drive input signals until it is reset. This is to prevent the free running period from being disturbed even if there are a plurality of "1"s in the cyclic register 3.

An example of the configuration of the self-running counter 6 is shown in FIG. When the output of the AND circuit 14 is "1", the AND circuit 61
is initially open, so the 772-bit counter 62
The configuration is such that the enable terminal E of the PCM becomes "1", and a count of 772 bits is started using the clock CLK, which is equal to the bit rate of the PCM input data, and cycles every 772 bits. When the enable terminal E becomes "1", the output Q of the counter 62 also becomes "1" immediately, and this is applied to the latch terminal L of the latch 63.
The output becomes "0" and closes the AND circuit 61, and even if the output of the AND circuit 14 becomes "1" thereafter, it is ignored. When the reset signal RST becomes "0", both the counter 62 and the latch are reset, and the free-running counter 6 returns to its initial state.

Returning to FIG. 1, when a frame pulse is generated, it is determined that frame synchronization has been engaged and the process proceeds to the next state. In the case of false synchronization, "1" is given to the control signal input terminal 52, and the output of the NAND circuit 8 indicates that the frame pulse is "1".
At the timing when the signal becomes ``0'', the AND circuit 12 is closed, and at that time, the cyclic register 3 outputs ``1''.
is rewritten to "0", the candidate number count value of the candidate number counter 4 is decreased by "1", and the self-running counter 6 and the control signal are reset. If a synchronization candidate still remains, the next "1" appearing from the cyclic register 3 is regarded as a synchronization candidate, and the free-running counter 6 is driven again to generate a new frame pulse at the timing of this synchronization candidate. Thereafter, the true synchronization pattern is captured by repeating the same process.

Next, the operation of this embodiment will be explained using the time chart shown in FIG. FIG. 4 shows a case where there are two synchronization candidates between 772 bits of the synchronization frame interval. After a predetermined period of time has passed from the start of the test, the output of timer 5 becomes "1".
'' and the rear protection ends. The test time is generally an integral multiple of the synchronization frame time, and only the bits of the cyclic register 3 that continuously match the synchronization pattern during that time remain as "1". In FIG. 4, 2 bits are "1". One of the two bits corresponds to a true synchronization pattern and the other corresponds to a false synchronization pattern. After the output of timer 5 becomes "1", cyclic register 3
The “1” that appears from is a false synchronization pattern in this example, but
At this point, it is not possible to determine whether it is true or false, and this circuit regards it as a synchronization pattern and generates a frame pulse from the free-running counter 6 (A). After that, when false synchronization is determined by CRC etc., the control input is set to "1", and then the first output "1" of the free-running counter 6 generates a reset signal from the output of the NAND circuit 8, and the At the same time as the bit corresponding to the false synchronization bit in register 3 is rewritten to "0", the reset signal is released, the free-running counter 6 returns to the initial waiting state, and the count value of the candidate number counter 4 decreases by "1". do. Next, when "1" corresponding to the true synchronization pattern appears from the cyclic register 3, the free-running counter 6 is driven again by this "1" (c). In this way, the true synchronization pattern is finally detected and a frame pulse corresponding to it is generated.

[0016] The case of 772 bits has been described above as an example, but the same applies to other cases.

[0017]

[Effects of the Invention] As explained above, the present invention provides the following advantages when multiple synchronization candidates still remain after the end of backward protection.
While the first captured synchronization candidate is regarded as a synchronization pattern, the other synchronization candidates are not discarded and are held in the cyclic register, and when the current synchronization pattern is determined to be false synchronization, the next captured synchronization candidate is Since it is regarded as a synchronization pattern, there is an effect that no time is required for re-inspection and backward protection.

Furthermore, since the execution can be repeated until the true synchronization pattern is found, the true synchronization pattern can be reliably detected even if the same data as the synchronization pattern is continuously received from the opposite transmitter for a long period of time. This has the effect of ensuring complete data transparency.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a connection diagram showing the configuration of the coincidence detection circuit shown in FIG. 1;

FIG. 3 is a connection diagram showing the configuration of the self-running counter shown in FIG. 1;

FIG. 4 is a tamming diagram showing the operation of the embodiment of the present invention.

[Explanation of symbols]

1 Shift register 2 Match detection circuit 3 Circular register 4 Candidate number counter 5 Timer 6 Free-running counter 7 Latch 8 NAND circuit 9 Inverter 11, 12, 13, 14 AND circuit 50 PCM
Input terminal 51 Resumption control output terminal 52 Control signal input terminal 53 Frame pulse output terminal 61 AND circuit 62 Counter 63 Latch

Claims (2)

[Claims] Claim 1: A first terminal that is connected to a synchronization signal determining circuit that determines the truth or falsehood of a synchronization signal and generates a control signal when the determination result is false, and that inputs PCM data, and a first terminal that inputs PCM data; a second terminal that provides a frame pulse to the hand circuit; a shift register that holds PCM data passing through the first terminal;
It has a coincidence detection circuit that compares the bits located in the synchronous bit interval included in the PCM data held in this shift register with the synchronous pattern, and the number of bits equal to the synchronous bit interval, and in the initial state, all of these bits are means for resetting the corresponding bit of the circular register when the comparison result between the circular register in the set state and the coincidence detection circuit does not match; and applying a pulse with a period equal to the synchronization bit interval to the second terminal; a free-running counter; a means for driving the free-running counter in accordance with a set bit first output from the cyclic register after counting the time necessary for backward protection; and upon input of a control signal from the synchronization signal determining means; This control signal is latched, and while this control signal is latched, the corresponding bit of the cyclic register is reset at the timing of the output pulse of the free-running counter, and then the free-running counter and the latched control signal are reset. A frame synchronization circuit characterized by comprising means for. 2. The frame synchronizer according to claim 1, further comprising initial state setting means for counting the number of set bits in the cyclic register and setting the own frame synchronization circuit to an initial state when the counted value indicates zero. circuit.