EP0187758A1

EP0187758A1 - Counting apparatus having independent subcounters

Info

Publication number: EP0187758A1
Application number: EP19850901244
Authority: EP
Inventors: Bruce James Dunbar
Original assignee: American Telephone and Telegraph Co Inc; AT&T Corp
Current assignee: AT&T Corp
Priority date: 1984-03-12
Filing date: 1985-02-15
Publication date: 1986-07-23
Also published as: JPS61501421A; WO1985004297A1

Abstract

Appareil de comptage où une indication de sortie est donnée en réponse à un nombre prédéterminé N de transitions de courant ou de tension d'entrée. L'appareil est doté d'une pluralité de sous-compteurs dont chacun répond aux transitions de courant ou de tension afin de développer un nombre maximal prédéterminé d'états binaires à sa sortie, le nombre maximal d'états fourni par chaque sous-compteur étant égal à un facteur premier relativement différent du nombre prédéterminé N. Un détecteur produit l'indication de sortie lorsqu'un groupe prédéterminé d'états binaires se présente aux sorties des sous-compteurs.Metering apparatus where an output indication is given in response to a predetermined number N of input current or voltage transitions. The device is provided with a plurality of sub-counters each of which responds to current or voltage transitions in order to develop a predetermined maximum number of binary states at its output, the maximum number of states provided by each sub-counter being equal to a prime factor relatively different from the predetermined number N. A detector produces the output indication when a predetermined group of binary states occurs at the outputs of the sub-counters.

Description

COUNTING APPARATUS HAVING INDEPENDENT SUBCOUNTERS

Background of the Invention

This invention relates to counting apparatus and, more particularly, to counting apparatus that is composed of a plurality of subcounters each one of which provides at its output at least two states.

For the purposes of this invention counting apparatus is defined as apparatus that provides an indication at its output that a predetermined number of transitions have been presented to its input. The counting apparatus may be comprised of a plurality of subcounters each one of which may in turn be defined as a state machine which passes sequentially through N states advancing always from the i to the i+1 state when clocked

ΉV_ and from its final N-1 state to its 0 state. In the prior art, subcounters of this type have been arranged in a chain to form a ripple or synchronized ripple counting apparatus. In this counting apparatus the overflow from one of the subcounters is coupled to the next subcounter in order to provide a transition or enable signal to the input of this next subcounter. The rate at which the overflow propagates or ripples through each stage to the final stage is the primary factor which determines the over-all speed of the counting apparatus. The circuit at the output end of the apparatus which checks the pattern of bits or words developed at the output of the individual subcounters must wait until all of the subcounters have settled before the indication is given that the predetermined number of input transitions have occurred at the input of the counting apparatus. Summary of the Invention

Por any particular type of logic configuration that is used to provide the subcounter circuits, a faster counting apparatus is provided in accordance with the present invention wherein the counting apparatus is comprised of a plurality of subcounters that are independent from each other in the sense that no subcounter depends on any of the other subcounters for the development of its output state. In addition, each subcounter is chosen to provide a maximum number of states at its output that belongs to a set of relatively prime factors of the predetermined number, N, which is the number of input transitions that occur before an output indication is given by the apparatus. These independent subcounters when related in this way will provide a unique pattern of output words after N transitions have been provided to the input of the apparatus. Brief Description of the Drawing

The invention will be more completely understood after reading the following detailed description in combination with the drawings wherein;

FIG. 1 is a counting apparatus constructed in accordance with the prior art,

FIG. 2 is a counting apparatus constructed in accordance with the present invention, and FIG. 3 is a chart of the output states provided by the counter circuits in FIG. 2. Detailed Description

One prior art technique of constructing a counting apparatus that will generate an output indication after a predetermined number of input transitions is illustrated in FIG. 1. In this Figure, counting circuits 101 , 102 and 103 are connected such that the input transitions are provided by way of a clock line 104 to the input of a counter circuit 101. The transitions referred to in this patent specification are changes in voltage with respect to some reference potential. The transition typically forms the leading edge of a voltage pulse, the required duration of which depends on the technology used to implement the counter circuits. Counter circuit 101 and two additional counter circuits 102 and 103 are initially cleared to their zero states by a transition on the clear line 105 which sets the counters to some predetermined output. In the FIG. 1 apparatus (and the FIG. 2 apparatus to be discussed hereinbelow) , this cleared output is simply a binary zero on each of the output lines provided by the counting circuits. After resetting the counters by the transition on the clear line 105, each transition on clock line 104 causes counter circuit 101 to change the binary word provided at its output on lines 106 through 108 thereby advancing counter circuit 101 through all of its M-_| states for subsequent clock transitions. When counter circuit 101 has advanced through all of its M-_| states a transition is provided on line 109 to the clock input of counter circuit 102. This initial transition on line 109 causes counter circuit 102 for the first time to change from the state provided on its output lines 110 through 112 after the• reset transition on clear line 105. Subsequent transitions on line 109 cause counter circuit 102 to advance through' its M2 states and provide a transition on line 113 to the clock^' input of counter circuit 103 after passing through all of the 2 states. In this way, counter circuit 103 is also caused to change from the reset condition provided on its output lines 114 through 116 after the transition on the clear line 105. This arrangement of counter circuits will be recognized by one skilled in the art as a ripple counter, the term ripple referring to the transitions that are propagated from counter circuit to counter circuit as each counter passes "through a complete cycle of its output states.

The binary output lines of all counter circuits are connected to a word detector 120 which is constructed to recognize some predetermined pattern of binary states provided on these output lines before it generates a transition on its output line 121 to indicate that N transitions have occurred on the clock input line 104. As will be apparent to one skilled in the art, the output indication on line 121 from word detector 120 can only be checked after counter circuits 101 through 103 have been permitted to stabilize or settle, that is permitted to respond to transitions that are developed on lines 109 and 113. This required period of stabilization is the primary factor in limiting the speed of the ripple counter shown in FIG. 1.

It is also possible in the prior art, to "synchronize" the ripple effect with a design in which each of the counter circuits 102 and 103 respond directly to transitions on a common clock line. The counter 102 will remain in the same state at each clock transition unless an enabling signal is present on line 109. Likewise, counter circuit 103 will not advance its count unless an enabling signal is present on line 113 when a transition occurs on the clock input line. As with the ripple counter, the output indication on line 121 from word detector 120 can only be checked after the output lines of counts 101-103 have stabilized. The amount of time needed for counter circuits 102 and 103 to develop the outputs 110-112 and 114-116 after a clock transition will be longer due to dependence on the enable inputs 109 and 110 than for counters which have no such dependence on enable inputs. This will determine the overall speed at which transitions can occur on the clock line.

A counting apparatus may be constructed in accordance with the present invention by first factoring the number, N, which designates the number of input transitions that are to occur before an output indication is given, into a set of relatively prime factors. As defined in the text "Theory of Numbers", Second Edition, by B. M. Stewart, Copyright 1952 and 1964, The McMillan

Company, integers are said to be relatively prime if the greatest common divisors of the integers is a unit, for example, 8 and 15 are relatively prime even though neither is a prime number. Counter circuits are then chosen so that each counter circuit provides a maximum number of output states equal to a different one of the relatively- prime factors in the set of relatively prime factors. These counter circuits are connected as shown in FIG. 2 with the input transitions on clock line 204 being connected to each of the counter circuits 201, 202 and 203. As indicated in FIG. 2, counter circuit 201 provides K-_j states at its output, counter circuit 202 provides K₂ states at its output, and counter circuit 203 provides K3 states at its output. Each of the counter circuits 201 through 203 are first cleared by a transition on the clear line 205 before the count of input transitions on line 204 begins. This transition on the clear line presets each of. the counter circuits to some predetermined state which in the case of the present embodiment is the state during which there is a binary zero on each of the output lines from all of the counter circuits. ^' The output lines 206 through 208, 210 through 212, and 214 through 217 are connected to a word detector 220. This word detector 220 provides an output indication on line 221 when a predetermined binary pattern is provided on the output lines from counter circuits 201 through 203. Unlike the prior art, counter circuits 201 , 202 and 203 are independent of each other in that the output of any one of the counter circuits is in no way dependent on the state achieved by any of the other counter circuits. Each is connected to respond to the input transitions on clock line 204.

To further understand the present invention it is helpful to consider additional details of the specific embodiment shown in FIG. 2. In that embodiment, the maximum states K-_j , K₂ and K3 are chosen such that the counting apparatus develops an output indication after

360 transitions have been provided on clock line 204. The number 360 can be factored into the integers 5, 8 and 9 all of which are relatively prime, the number 5 is prime in itself, 8 consists of the prime number 2 cubed, and 9 consists of the prime number 3 squared, and therefore, none of the integers have a common factor other than the unity. What makes this decomposition into relatively prime factors important to counter design is a number theory result known as the "Chinese Remainder Theorum", so-called because it was known in ancient China. A succinct definition of this theorum is provided on page 103 of the above-identified text by D. M. Stewart. Application of this theorum to the configuration of counter circuits shown in FIG. 2 insures that a unique output word will be provided by the outputs of counter circuits 201 through 203 only after- a predetermined number N (equals 360) of input transitions have occurred on clock line 204.

Clock circuit 205 is designed to provide five different binary states on its output lines 206 through 208, counter circuit 202 is designed to provide eight different output states on its output lines 210 through 212 and clock circuit 203 is designed to provide nine different output states on its output lines 214 through 217. The state assignments chosen for the counter circuits 201-203 in the embodiment of FIG. 2 are illustrated in the table set forth in FIG. 3. All of the counter circuits are reset to their S_n state by the appearance of a transition on clear line 205. As indicated in FIG. 3, counter 201 consists of a state machine with three binary output lines, which machine is caused to recycle after its 5 state S^. Counter circuit 202 is a state machine with three binary output lines, which machine is caused to cycle through all of its eight states. Counter circuit 203 is a state machine with four binary output lines, and the machine is caused to recycle after its 9 state, Sg. Word detector 220 is constructed to provide an output indication on line 221 when counter 201 has the binary word 1XX at its output, counter 202 has the binary word 110 at its output, and counter 203 has the binary word 1XXX at its output. The symbol X indicates that either binary zero or one may be present. Each of these .counters 201-203 may be constructed by circuits that are well known to those skilled in the art. Any sequence of binary numbers may be assigned, of course, to the counter states within counters 201-203. FIG. 3 represents only one possible choice. See, for example, the synchronous binary counters described in Chapters 4 and 10 of the text "Electronic Counters", R. M. M. Oberman, Copyright 1973, the McMillan Press Ltd. Chapters 4 and 10 of this text provide schematic block diagrams of arrangements that can be used for each of these counter circuits.

What has been described hereinabove is simply an illustrative embodiment of the present invention. It should be apparent to those skilled in the art that numerous departures may be made without departing from the spirit and scope of the present invention. For example, a different number of counting stages may be used to provide counting apparatus to indicate other predetermined numbers of input transitions or even the same number of input transitions. For example, a counting apparatus that is designed to give an indication after 900 input transitions may be constructed either with counting circuits that provide 4, 9 and 25 output states, or with counter circuits that provide 36 and 25 output states, or even with counting apparatus that provide 4 and 225 output states. The maximum number of output states need only be related to each other by the above-stated principles of being relatively prime. In addition, it should be apparent to those skilled in the art that the principles of the present invention are equally applicable when the counter circuits provide output words in something other than the binary system.

Claims

1. Apparatus for providing an output indication after a predetermined number, N, of input transitions, said apparatus CHARACTERIZED BY a plurality of counting means each one of which has an input and output and provides a change in state at the output in response to each transition of a predetermined type at its input thereby providing a predetermined maximum number of different states at its output before recycling, means for coupling said input transitions to the input of each of the plurality of counting means, and means for generating said output indication in response to a predetermined pattern of states developed at the outputs of all of said plurality of counting means, the maximum number of states provided by each of said plurality of counting means when considered in pairs being equal to relatively prime factors of the number N.

2. Apparatus for generating an output indication after a predetermined number, N, of transitions on an input line, said apparatus comprising at least two counting means each one of which has an input for receiving voltage or current transitions and an output which provides a sequence of binary states in response- to a sequence of said transitions,

CHARACTERIZED BY each one of said at least two counting means is adapted to have a change in binary state at its output in response to each transition of a predetermined type at its input thereby providing a predetermined maximum number of output states before recycling, means for connecting said input line to the input of each one of said at least two counting means, and means for providing said output indication in response to a predetermined group of binary states at the outputs of said at least two counting means, the predetermined maximum number of output states for all of said at least two counting means when considered in pairs being equal to relatively prime factors of the predetermined number N.

3. Apparatus for producing an output indication after a predetermined number, N, of input transitions, said apparatus comprising at least two counting means each one of which has an input and output and provides a change in state at the output in response to a voltage or current transition of a predetermined type at the input thereby providing a predetermined maximum number of output states before recycling, and means responsive to a predetermined group of states at the outputs of said at least two counting means for generating said output indication that a predetermined count of N has been achieved, CHARACTERIZED IN THAT said apparatus further includes means for directly coupling said input transitions to the inputs of all of said at least two counting means, each one of said at least two counting means being constructed .to provide a maximum number of states at its output that is a member of a paired set of relatively prime factors of the predetermined number N, the other member of the paired set being the maximum number of states provided by a second one of said at least two counting means.