JPS61154330A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit and to attain synchronism detection with high surity by storing an integrated value of presence of a frame synchronization into an RAM at each bit timing in a frame and detecting a bit timing having the largest integration. CONSTITUTION:A clock 6a synchronously with a bit constituting a frame is received by a pulse generating circuit 6, which generates a read pulse 6b and a write pulse 6c. A data in an RAM 7 is read by using the pulse 6b and an output of a counter 2 counting a clock up to the bit number corresponding to one frame as an address. A read data is added by an adder 8 when the coincidence is detected by a coincidence detection circuit 1 of the frame synchronizing pattern. Then the data is written in the RAM 7 at the same address by using the next pulse 6c from the circuit 6, and the operations above are repeated. A comparison circuit 9 compares a prescribed value with an output of the RAM 7 outputted at each bit timing and the bit timing having an output of the RAM exceeding the prescribed value fastest is used as the establishment of the frame synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit for digital transmission, and particularly to a method for detecting the beginning of received data.

[Conventional technology]

In general, in digital transmission, frame strings are rounded due to the addition of noise on the transmission path, and the 0 (zero) or 1 of each bit composing the frame string changes during transmission, resulting in a frame synchronization pattern in the frame. There is a possibility that a match may be detected incorrectly, or a match may occur at another time.

Therefore, it is necessary to detect the synchronization pattern more reliably in the seven-ray one-fifteen synchronization circuit.

There are six examples of such frame synchronization circuits, such as those shown in FIG. In the figure, 1 is a coincidence detection circuit that detects the coincidence of frame synchronization patterns, 2 is a counter that counts the number of clocks generated in synchronization with the bits that make up a frame, up to the number of bits N corresponding to one frame, and 3 is this counter. A selection circuit receives the output value of 2 and selects an adder corresponding to the output value from among the N adders 14 provided corresponding to the output values 1 to N; 5 is an OR circuit; be.

In the conventional frame synchronization circuit having such a configuration, first, the coincidence detection circuit 1 serially receives the digital signal train F shown in FIG. F1 is input continuously. At the same time, a match with a known synchronization pattern is determined in this match detection circuit. On the other hand, the counter 2 counts 9 clocks by the number of bits Nj corresponding to one frame in synchronization with the bits constituting the 7-ray 5F1,
The next bit is used to return to the original state. A selection circuit 3 receives the output value of the counter 2 for each count up to the number of bits N, and this selection circuit 3 selects one of the N adders 4 corresponding to the output value. At that time, the selected adder 4 adds if there is a coincidence output from the coincidence detection circuit 1.

At frame 17, the count value of counter 2 returns to the original value, so
The coincidence output generated at each bit timing of the next frame is added to the coincidence output generated at the same bit timing in the previous frame.

The same overflow value is set for each of the adders 4, and the OR circuit 5 detects the earliest overflow timing. The timing detected in this manner is the most reliable synchronization detection timing for detecting the start tb of received data.

[Problem that the invention seeks to solve]

Since the conventional 7-frame synchronization circuit is configured as described above, an adder is required for the number of bits N equivalent to one frame, and if the overflow value is set larger, the reliability of synchronization detection increases. However, the circuit configuration became large and t
Another method to simplify the circuit configuration is to predict the timing section (window) in which the synchronization pattern exists in the frame and search for the most reliable synchronization detection timing in that section. There were problems such as the need for a separate setting circuit.

The present invention has been made to solve the above-mentioned problems, and aims to simplify the circuit and provide a frame synchronization circuit that can detect synchronization with high reliability.

[Means for solving problems]

The frame synchronization circuit according to the present invention stores the integrated value of frame synchronization presence/absence for each bit timing in a frame in a random access memory, and detects the bit timing with the largest integrated value.

[For production]

In the frame synchronization circuit according to the present invention, the integrated value of whether or not frame synchronization is present is stored in a random access memory whose storage contents are variable, and the comparator detects the maximum bit timing of the integrated value, thereby simplifying the circuit and improving reliability. The value will be high.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a frame synchronization pattern match detection circuit;
2 synchronizes with the bits that make up the frame and 1
A counter that counts up to the number of bits N of the 7-rhyme phase music,
6 is a pulse generation circuit that generates read and write pulses in synchronization with the above clock, 7 is a random access memory whose address is the output value of the counter 2, and 8 is a connection between the output value of the coincidence detection circuit 1 and the random access memory 7. The adder 9 which adds up the output value is a comparator circuit 6.

Next, the operation will be explained. In the pulse generation circuit 6, frame F
A clock synchronized with the bits that constitute 1 [61 in Figure 2]
], the readout pulse 6b in FIG.
Write pulse 6 (21!I pulses as shown in IK, in which high and low levels do not overlap each other) are generated.These read pulses 6b and write pulses 66 are synchronized with the rise and fall of the clock 6a, for example. Then, using the read pulse Bbo & the first pulse 6b', data is read from the random access memory 7 using the output value of the counter 2 as an address.This read data is used for coincidence detection. When a match is detected in the circuit 1, the adder 8 adds the data.Next, the next pulse 6G'1=J-7 from the pulse generating circuit 6 is written to the random access memory 7vc at the same address as above.

The above steps are repeated for each bit timing, and the number of matches at the same bit timing in each frame is added up. The comparator circuit 9 compares the constant value and the output value of the random access memory output at each bit timing, and selects the 7th frame at the bit timing at which the output value of the random access memory 7 exceeds the constant value earliest. This is the detection timing of synchronization establishment.

In the above embodiment, the coincidence detection circuit 1 outputs a signal indicating that there is a coincidence when all the bits of the frame synchronization pattern match. No match is found. Therefore, the coincidence detection circuit 1 is configured to output the number of matched bits in the frame synchronization pattern, and the write in the random access memory 7, the addition in the read adder 8, and the ratio in the comparison circuit 9 are also made to output the number of matched bits in the frame synchronization pattern. If you operate based on the number of matched bits, the first
With the configuration shown in the figure, it is possible to detect the most reliable timing for establishing frame synchronization.

In addition, even after frame synchronization is established, the random access memory 7
Frame synchronization maintenance can be verified by completely resetting the memory contents of the memory, detecting the frame synchronization establishment timing again, and comparing whether it is the same as the timing before the reset.

〔Effect of the invention〕

As described above, according to the present invention, the cumulative value of frame synchronization presence/absence for each bit timing in a frame is stored in a random access memory, and the bit timing with the largest cumulative value is detected. This has the effect of providing a frame synchronization circuit that is compact, simple, and highly reliable.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a frame synchronization circuit according to an embodiment of the present invention, FIG. 2 is a time chart showing the clock input to the pulse generation circuit 6 of FIG. 1 and output pulses, and FIG.
The figure is a circuit diagram showing a conventional frame synchronization circuit, and FIG. 4 is a frame configuration diagram showing a frame string of a general digital signal. In the figure, 1 is a coincidence detection circuit, 2 is a kakunta, 6 is a pulse generation circuit, 7F1 is a random access memory, 8 is an adder, and 9 is a comparison circuit. Note that the same reference numerals in each figure indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation Procedural amendment (voluntary)

Claims (1)

[Claims] a coincidence detection circuit that receives a frame sequence of a digital signal and detects a match with a predetermined frame synchronization pattern; a counter that counts a clock that is synchronized with the bits of the frame of the digital signal; a pulse generation circuit that generates pulses and write pulses, and an output value of the counter as an address;
a random access memory that stores an integrated value of frame synchronization presence/absence for each bit timing in the frame; an adder that adds the read output value of the random access memory to the output value of the coincidence detection circuit; and the random access memory. a comparator for detecting a bit timing at which the output of the random access memory is maximized by comparing an output value outputted at each bit timing with a predetermined value.