JPS627577B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data majority voting circuit that selects data of the same content that accounts for a majority from among n pieces of data in data composed of m pieces of bits.

Conventionally, when a multi-system configuration of processing devices that gives meaning to data consisting of m bits and processes it, and a device with hole length is configured, it is necessary to correct the data output from each processing device. Or, to detect processing discrepancies, majority voting was performed on the data. However, all conventional data majority voting circuits are constructed by combining AND elements, so when the processing device has an n-fold system configuration, in order to take a majority vote of n pieces of data, A (A is an integer and n+2 /2≧A>n/2
) requires m × nC _A input AND input elements and nC _A m input AND AND elements, and the number of AND elements is proportional to the number n of data that takes a data majority vote and the number m of data bits. The disadvantage is that the number of circuits increases, the circuit becomes more complex, the size increases, and the cost also increases. For example, when taking a majority vote among three pieces of data D ₁ to D _{3 each} consisting of 16 bits, according to the conventional system, a block diagram as shown in FIG. 1 is obtained. That is, in order to take a data majority vote of data D ₁ to _{D 3} , two data D ₁ and
D ₂ , D ₂ and D ₃ , D ₃ and D ₁ bits D _1-1 ~ D _1-16 , D _2-1
〜D _2-16 , D _3-1 〜D _3-16 , AND element 1 ₁ 〜1
₁₆ , 2 ₁ to 2 ₁₆ , 3 ₁ to 3 ₁₆ , and then AND elements 4, 5, 6 and AND elements 7 ₁ to
7 ₁₆ , 8 ₁ to 8 ₁₆ , and 9 ₁ to 9 ₁₆ were successively logically ANDed the outputs.

Now, if data D ₁ , D ₂ , and D ₃ are all of the same logic, the outputs of AND elements 4, 5, and 6 are all logic 1, and data D ₁ , D ₂ , and D ₃ are the majority data.
At the same time as being output as MJD, OR element 1
An output of 0 becomes a logical value of 1.

Also, even if one bit of data D ₁ is different from other data D ₂ ,
Unlike D ₃ , if data D ₂ and D ₃ match, only the output of AND element 6 will have a logical value of 1,
At the same time that data _D3 is output as majority data MJD, the output of OR element 10 becomes a logical value of 1.

However, if all of the data D ₁ to _{D 3} are different, or if two or more data are different, the outputs of ANDs 4, 5, and 6 will all have a logical value of 0, so
The output of the OR element 10 becomes a logical value of 0.

Therefore, by checking the output of the OR element 10, it is possible to know whether a majority vote of the data has been obtained.

In this manner, conventional majority voting circuits all perform majority voting by combinations of AND elements, which leads to the circuit becoming more complex and larger as described above, resulting in higher costs.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a data majority voting circuit that can easily take majority voting on data by using a small number of logic elements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The content of the present invention will be specifically explained in detail below with reference to the accompanying drawings which are examples.

FIG. 2 is a block diagram of a data majority decision circuit according to the present invention, and FIG. 3 similarly shows a timing chart of signals at various parts. In this embodiment, a data majority decision circuit is shown for three pieces of data _D1 to _D3 each consisting of 16 bits, but the circuit can be similarly applied to a larger or smaller number of bits or data. is possible.

In Figure 2, 11D ₁ , 11D ₂ , 11D ₃
is a shift register circuit provided for each data _D1 to _D3 . The shift register circuit 11D ₁
to _11D3 have the number of inputs corresponding to the number of bits of each data _D1 to _D3 .

12 is a shift pulse generation circuit. This shift pulse generating circuit 12 generates a shift pulse a serving as a clock signal, and the processing in the data majority decision circuit proceeds in accordance with this shift pulse a.

13 is a shift pulse counting circuit. This shift pulse counting circuit 13 counts shift pulses a given from the shift pulse generating circuit 12.

14 is a majority circuit. The majority circuit 14
is configured to include AND elements 14a to 14c, the number of which corresponds to the number of data _D1 to _D3 , and an OR element 14d which calculates the logical sum of their outputs.

15D ₁ , 15D ₂ , and 15D ₃ are exclusive OR elements, and the number thereof corresponds to the number of data D ₁ to _{D 3} . This exclusive OR element 15D ₁ ~
_15D3 is for each bit of data serially sent from the shift register circuits _11D1 to _11D3 in synchronization with shift pulse a, which is a clock signal.
This is provided to check for discrepancies with the output e of the majority circuit 14.

16 ₁ , 16 ₂ , 16 ₃ are memory circuits for storing the match/mismatch states for each bit output from the exclusive OR elements 15D ₁ to 15D ₃ , and in this embodiment, they are constructed by flip-flops. .

A storage circuit 17 temporarily stores the output of the majority circuit 14, and is constituted by a shift register circuit.

18 is a majority circuit that takes a majority vote of the outputs of the flip-flops 16 ₁ to 16 ₃ ; 19 is a circuit that connects the output of the majority circuit 18 and the shift pulse counting circuit 1;
This is an AND element that performs AND with the output of 3.

Next, the operation will be explained.

First, three pieces of data D ₁ to _{D 3} are respectively input to shift register circuits 11D ₁ to 11D ₃ and stored. When three data D ₁ to D ₃ are stored,
In order to serially output the data D ₁ to D ₃ stored in each of the shift register circuits 11D ₁ to 11D ₃ bit by bit, the shift pulse generation circuit 12 outputs the data D 1 to D 3 stored in each of the shift register circuits 11D ₁ to 11D ₃ . A number of shift pulses a equal to the number of bits, ie 16 in this embodiment, are provided. In synchronization with the fall of this shift pulse a, the data stored in the shift register circuits 11D ₁ to 11D ₃ is serially supplied to the majority circuit 14 one bit at a time.

When all the bits of each data sent to the majority circuit 14 have a logic value of 1, or when two or more bits have a logic value of 1, the logic element 14
Since all or any one of the outputs of a to 14c has a logical value of 1, the output e of the OR element 14d has a logical value of 1. On the other hand, when all or two bits of each data have a logical value of 0, all outputs of the AND elements 14a to 14c have a logical value of 0, so the output e of the OR element 14d also has a logical value of 0. Therefore, in this majority circuit 14, for each bit of each data _D1 to _{D3 , 3C2}
A majority vote will be taken.

The majority decision result e of the majority decision circuit 14 is synchronized with the fall of the shift pulse a given from the shift pulse generation circuit 12 to the shift register circuit 17.
Each bit is stored in the shift register circuit 17.

On the other hand, simultaneously with the majority decision operation, the majority decision circuit 1
The output e of 4 is input to the exclusive OR elements 15D ₁ to 15D ₃ one by one for each bit, and there is a discrepancy with the bit data b, c, d that is input serially from the shift register circuits 11D ₁ to 11D ₃ . is taken. The outputs of the exclusive OR elements 15D ₁ to 15D ₃ are input to the set input terminals S of the flip-flops 16 ₁ to 16 ₃ , respectively, and the outputs of the shift pulses a applied from the shift pulse generation circuit 12 to the flip-flops 16 ₁ to 16 3 are input to the set input terminals S of the flip-flops 16 1 to 16 ₃ , respectively. In sync with the descent,
The data is stored in flip-flops ₁₆₁ to ₁₆₃ .
This storage state is determined when the shift pulse counting circuit 13 counts the number of shift pulses corresponding to the number of bits, that is, ₁₆ shift pulses a in this embodiment. ₃ reset input terminal R
The flip-flops 16 1 to 16 3 are held until they are reset by the clear pulse l applied to the flip-flops 16 ₁ to 16 ₃ .

The above-mentioned exclusive OR elements 15D ₁ to 15D ₃ and flip-flops 16 ₁ to 16 ₃ occupy important parts as a circuit for detecting whether a majority vote has been taken. This will be explained in more detail with reference to the timing chart shown in FIG.

As an example, the timing chart in Figure 3 is as follows:
Shift register circuit 11D ₁ corresponding to data D ₁
The output b is [1101001110001010], and the data
Shift register circuit 11D ₂ , corresponding to D ₂ , D ₃
The case where both outputs c and d of 11D ₃ are [1101001110011010] is shown.
In other words, the 12th bit of data D ₁ is
It is different from D ₂ and D ₃ . In this case, as is clear from the figure, the shift register circuit 1
Since the output b of 1D ₁ becomes a logical value 0, the logical value 1
It is inconsistent with the output e of the majority circuit 14, which is
The output f of the exclusive OR element _15D1 has a logical value of 1. This output f having a logical value of 1 is input to the set input terminal S of the flip-flop ₁₆₁ , and the flip-flop ₁₆₁ is set in synchronization with the fall of the 12th shift pulse a.

In this way, the output of the majority circuit 14 and the bits of each data are checked for each bit of data, and if they do not match, the corresponding flip-flop 16 ₁ , 16 ₂ or 16 ₃ is set.

When the shift pulse generation circuit 12 finishes generating 16 shift pulses a, the shift pulse counting circuit 13 outputs a clear pulse l for resetting the flip-flops 16 ₁ to 16 ₃ and a data majority check timing pulse (hereinafter referred to as MJDCK). j) is output, and the series of operations ends.

Further, the outputs g, h, and i of the flip-flops 16 ₁ to 16 ₃ are input to the majority circuit 18 , and the output of the majority circuit 18 is input to the AND element 19 .
It is ANDed with MJDCK signal j.

Now, if all three data D ₁ to _{D 3} have the same content, the output e of the majority circuit 14 and the output b of the shift register circuits 11D ₁ to 11D ₃ ,
c and d match, exclusive OR elements 15D ₁ to 1
Since all outputs f of _5D3 have a logic value of 0, none of the flip-flops 16 ₁ to 16 ₃ are set, and the output of the majority circuit 18 has a logic value of 1.
At the input timing of the MJDCK signal j, the output k of the AND element 19 becomes a logical value 1.

Also, one of the three data D ₂ to _{D 3} is the other 2
If the two data are different, the flip-flops 16 ₁ , 16 ₂ corresponding to the different data
Alternatively, only the flip-flop ₁₆₃ is set and the other flip-flops are not set, so the output of the majority circuit 18 becomes a logic value 1, and at the input timing of the MJDCK signal j, the output k of the AND element 19 becomes a logic value 1.

At this time, the majority decision data MJD ₁ to MJD ₁₆ outputted from the shift register circuit 17 have the same content as two pieces of data that match each other.

Furthermore, if all three data D ₁ to _{D 3} are different from other data, the flip-flops 16 ₁ to 16
Two or more ₁₆₃ are set, and the output g,
Since two or more of h and i have a logical value of 0, and the output of the majority circuit 18 has a logical value of 0,
At the input timing of the MJDCK signal j, the output signal k is not output from the AND element 19.

Therefore, it can be determined from the output signal k of the AND element 19 whether or not a majority vote has been taken on the data. And when a majority vote of the data is obtained,
The majority data becomes the storage data of the shift register circuit 17.

In the above embodiment, a data majority decision circuit for three pieces of data with a 16-bit configuration was explained.
When configuring a data majority circuit for n bit-configured data, the shift register circuit 11D ₁
~11D ₃ , exclusive OR circuit 15D ₁ ~15D ₃ ,
The flip-flops 16 ₁ to 16 ₃ and the AND elements of the majority circuits 14 and 18 may be provided in m pieces corresponding to the number of data.

As described above, the data majority decision circuit according to the present invention is of a type that serially processes each data bit by bit in synchronization with a clock signal.
Logic elements in majority circuits, elements for detecting data mismatches, etc. only need to be provided for the number of data items, regardless of the increase in the number of bits, which greatly reduces the number of logic elements used compared to the past, simplifying the circuit configuration. Effects such as reduction in size, size, cost reduction, and improvement in reliability are achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional data majority decision circuit, FIG. 2 is a block diagram of a data majority decision circuit according to the present invention, and FIG. 3 is a timing chart of signals in each part thereof. 11D ₁ to 11D ₃ ...shift register circuit, 12
...Shift pulse generation circuit, 13...Shift pulse counting circuit, 14...Majority circuit, 15D ₁ to 15D ₃ ...
Exclusive OR element, ₁₆₁ to ₁₆₃ ...Flip-flop, 17...Shift register circuit, 18...Majority circuit, 19...Logic product element.

Claims (1)

[Claims] 1 Select data with the same content that accounts for the majority from n data consisting of m bits,
and a data majority circuit that detects the result of the selection, a majority circuit that takes a majority vote for each bit of n serial data synchronized with a clock signal, and a storage circuit that stores the output of the majority circuit;
an exclusive OR circuit for detecting a mismatch between the output of the majority circuit and serially input data; a memory circuit for storing the match/mismatch state for each bit output from the exclusive OR circuit; and the memory. 1. A data majority circuit comprising: a majority circuit that takes a majority vote of the outputs of the circuit; and an AND circuit that takes an AND of the output of the majority circuit and the output of a counter that counts clock signals.