JPH03263921A - Counter with preset - Google Patents

Abstract

PURPOSE:To realize an n-bit counter with preset in which the number of input terminals are reduced to a minimum by detecting the rise or fall of a signal inputted to the input terminal, and outputting a loading signal to the n-bit counter after the lapse of bits >=(n). CONSTITUTION:When the preset data of (n) bits converted to serial data is inputted to the input terminal 11 in a state where a shift register 1 is enabled, the preset data is stored in the shift register 1, and the preset data is inputted to the preset data input terminal 4 of the counter 2 with preset. Meanwhile, a loading signal delay circuit 13, in the case of detecting the rise of the input terminal 11, the loading signal is outputted to the counter 2 with preset after the lapse of time of the bits >=(n) after the rise is detected. A preset operation can be performed since the preset data inputted from the input terminal 11 is inputted to the preset input terminal of the counter 2 with preset.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a counter with presets.

BACKGROUND OF THE INVENTION In recent years, the scale of integrated circuits has increased, and the number of input/output terminals of integrated circuits has increased, and many efforts have been made to fit the integrated circuits into a package with a predetermined number of terminals.

First, in order to reduce the number of input terminals in the conventional example, a shift register was used to input the preset data.
A preset counter with a reduced number of input terminals will be described below with reference to the drawings.

FIG. 3 is a block diagram of a conventional counter with preset that uses a shift register to input preset data as a measure to reduce the number of input terminals. In Fig. 3, 1 is an n-bit shift register that stores preset data of a counter with preset, 2 is an n-bit counter with preset, 3 is an output terminal of shift register 1, and 4 is an input of preset data of counter 2 with preset. Terminal 5 is the output terminal of counter 2 with preset,
6 is a clock input terminal, 7 is a preset data input terminal of the shift register 1, 8 is an enable signal input terminal of the shift register 1, and 9 is a load signal input terminal of the counter with preset.

FIG. 4 is a timing diagram of the conventional preset counter shown in FIG.

The operation of the preset counter configured as described above will be described below. First, the shift register 1 is enabled and preset data converted into serial data is input to the preset data input terminal 7 of the shift register 1. The input serial data is sequentially fetched into the shift register in synchronization with the clock, and if the shift register is disabled when the n-bit data to be preset is complete, the output terminal 3 of shift register 1 and the preset Since the input terminals of the counter are connected, preset data will be input to the preset data input terminal 4 of the counter 2 with preset. If a load signal is input to the preset counter 2 in this state, the output of the preset and sort counter will become the preset data. In this conventional example, by using a shift register to input preset data, the number of preset data input terminals of the counter 2 with preset is reduced from n to two terminals: the preset data input terminal of the shift register and the enable signal input terminal of the shift register. It is now possible.

Problems to be Solved by the Invention However, in the above configuration, in addition to the load signal input terminal and clock input terminal of the counter with preset, there are two input terminals: the preset data input terminal of the shift register and the enable signal input terminal of the shift register. is needed.

In view of the above problems, the present invention provides a counter with a preset in which the load signal input terminal of the counter with a preset also serves as an input terminal of preset data, thereby minimizing the number of input terminals.

Means for Solving the Problems In order to solve the above problems, the present invention provides an n-bit counter with presets having n preset data input terminals, and preset data of the n-bit counter with presets converted into serial data. an input terminal that also serves as an input for the input of the n-bit counter with a preset and a load signal for the n-bit counter with a preset; an n-bit shift register that stores the n-bit preset data input from the input terminal; a shift enable signal generation circuit that detects a rising edge or a falling edge and generates an enable signal for the n-bit shift register; and a shift enable signal generation circuit that detects a rising edge or a falling edge of a signal input to the input terminal, and detects a rising edge or a falling edge of the signal input to the input terminal, and detects a rising edge or a falling edge of the signal input to the input terminal, and a shift enable signal generating circuit that detects a rising edge or a falling edge of the signal and generates an enable signal for the n-bit shift register. and a load signal delay circuit for outputting a load signal to the n-bit counter with preset.

Function: With the above-described configuration, the present invention enables the load signal input terminal of the preset counter to also serve as the preset data input terminal, thereby realizing an n-bit counter with preset with a minimum number of input terminals.

EXAMPLE Hereinafter, the present invention will be explained by way of an example with reference to the drawings.

FIG. 1 is a block diagram of this embodiment. In FIG. 1, 1 is an n-bit shift register that stores preset data of a counter with preset, 2 is an n-bit counter with preset, 3 is an output terminal of shift register 1,
4 is a preset data input terminal of n-bit counter 2 with preset, 5 is n-bit counter 2 with preset
, 6 is a clock input terminal, 8 is an enable signal input terminal for the shift register 1, and 9 is a load signal input terminal for a preset counter, which has the same structure as the conventional example. 10 is an input terminal which also serves as an input of preset data of the n-bit counter 2 with preset converted into serial data and a load signal of the n-bit counter 2 with preset, and 11 is a rising edge of the signal input to the input terminal 11, or A shift enable signal generation circuit detects a falling edge and generates an enable signal for the shift register 1. 12 is an output terminal of the shift enable signal generation circuit. 13 detects a rising edge or a falling edge of a signal input to the input terminal 11. 14 is an output terminal of the load signal delay circuit which outputs a load signal to the n-bit counter 2 with preset after n bits or more have elapsed.

FIG. 2 is a timing diagram of the conventional preset counter shown in FIG.

Next, the operation of the preset counter of the present invention constructed as described above will be explained with reference to FIGS. 1 and 2. In the present explanation, it is assumed that the loading operation is started when the input terminal 10 becomes high level, that is, at the rising edge of the input signal. First, when the shift enable signal generation circuit 11 detects the rising edge of the signal input to the input terminal 10, it outputs a signal that enables the n-bit shift register to the n-bit shift register 1. If n-bit preset data converted to serial data is input to the input terminal 11 while the shift register 1 is in the enabled state, the preset data is stored in the shift register 1.
Preset data is input to the preset data input terminal 4 of the counter 2 with preset. on the other hand,
When the load signal delay circuit 13 detects the rising edge of the input terminal 11, the load signal delay circuit 13 does not detect the rising edge for n bits thereafter, and waits for a time of n bits or more after detecting the rising edge to detect the rising edge of the input terminal 11. outputs the load signal. If n bits or more have elapsed since the rising edge was detected, the preset data input from the input terminal 11 has been input to the preset input terminal of the counter 2 with preset, so that the preset operation can be performed. Note that in order for the n-bit counter with preset of this embodiment to operate normally,
The preset interval must be n+1 bits or more.

As described above, according to this embodiment, the n-bit counter with preset has n preset data input terminals, and the input of preset data of the n-bit counter with reset that has been converted into serial data. an input terminal that also serves as an input for the load signal of the n-bit counter with preset, an n-bit shift register that stores n-bit preset data input from the 7i input terminal, and a rising edge of the signal input to the input terminal; or a shift enable signal generation circuit that detects a falling edge and generates an enable signal for the n-bit shift register, and a rising edge of the signal input to the input terminal;
Or after detecting a falling edge and elapsed after n bits or more,
By providing a load signal delay circuit that outputs a load signal to the n-bit counter with preset, the number of input terminals of the n-bit counter with preset can be minimized, that is, the number of input terminals of the n-bit counter with preset is reduced to a clock input terminal and n-bit with preset converted into serial data. It can be made into two input terminals, which serve both as an input of preset data for the counter 2 and as an input of a load signal for the n-bit counter 2 with preset.

Effects of the Invention According to the present invention, there is provided an n-bit counter with a preset having n preset data input terminals, an input of preset data of the n-bit counter with a preset converted into serial data, and an input terminal of the n-bit counter with a preset that is converted into serial data. an input terminal that also serves as an input for a load signal; an n-bit shift register that stores n-bit preset data input from the input terminal; and an n-bit shift register that stores n-bit preset data input from the input terminal; a shift enable signal generating circuit that generates an enable signal for the n-bit shift register; and a shift enable signal generation circuit that detects the rising edge or falling edge of the signal input to the input terminal, and after n bits or more have elapsed, the n-bit with preset By providing a load signal delay circuit that outputs a load signal to the counter, the load signal input terminal of the counter with preset can also serve as the input terminal of preset data, making it possible to create an n-bit counter with preset that minimizes the number of input terminals. can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a preset counter according to an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of this embodiment.
FIG. 3 is a block diagram of a conventional counter with preset, and FIG. 4 is a timing diagram of a conventional counter with preset. 1...n-bit shift register, 2...
・N-bit counter with preset, 3...n
Bit preset data output terminal, 4...
Input terminal of n-bit counter with preset, 5...
... Output terminal of n-bit counter with preset, 6
...... Clock input terminal, 8... Shift register enable signal input terminal, 9... Load signal input terminal, 10... Input terminal, 11.
...Shift enable signal generation circuit, 12...
...Output terminal of shift enable signal generation circuit, 13
...Load signal delay circuit.

Claims (1)

[Claims] An n-bit counter with presets having n preset data input terminals, and an input terminal that also serves as an input of the preset data of the n-bit counter with presets converted into serial data and as an input of a load signal of the n-bit counter with presets. an n-bit shift register that stores n-bit preset data input from the input terminal; and an enable signal for the n-bit shift register by detecting the rising or falling edge of the signal input to the input terminal. a shift enable signal generation circuit that generates a shift enable signal, and a load signal delay circuit that detects the rise or fall of a signal input to the input terminal and outputs a load signal to the n-bit counter with a preset after n bits or more have elapsed. A counter with presets.