JPS6276327A - Digital signal generating circuit - Google Patents

Abstract

PURPOSE:To reduce number of components by inserting an isolator on the way of a data line through which a serial signal is sent so as to use only three isolators even when number of signal lines through which a parallel signal is outputted. CONSTITUTION:When a 4-bit signal is inputted sequentially to a shift register 13a via an isolator 6 from a data line 10, the 4-bit signal is shifted at each input of a clock signal 11 and the 4-bit signal is held in the shift register 13a. When one-bit signal is outputted from the data line 10, the signal is shifted to next shift registers 13b, 13c. When data are set to the shift registers 13a-13c, a 4-bit BCD signal is outputted from the shift registers 13a-13c through signal lines 7a-7l by using a strobe signal 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal generation circuit that converts serial signals into parallel signals while isolating them.

[Prior Art] FIG. 2 shows a general example of a digital signal generation circuit that outputs isolated parallel signals.

In Figure 2, (1) is the central processing unit, (2) is the address bus coming out of the central processing unit, (3) is the data node also coming out of the central processing unit, and (4) is the address bus ( 2) are connected to decoders, (51) to (
53) are latch circuits that are connected to the data bus and temporarily hold signals sent from the data bus, (8a) to
(6th sentence) is an isolator composed of a photocoupler, etc., and (7d) to (7fL) are B as parallel signals.
This is a signal line for extracting CD signals.

In this example, it is assumed that four signal lines come out as a data bus, and two signal lines come out as an address 7 bus.

Next, the operation of the digital signal generation circuit configured as described above will be explained.

First, the data bus (3) coming out from the central processing unit (1)
), when a 4-bit parallel signal is output from the address bus (2), the decoder (4) operates three latch circuits (51) to (5) using the 2-bit signal output from the address bus (2).
3), one of the latch circuits (51) is set.

When the next 4-bit signal is output to the data bus (3), the decoder (4) outputs the three latch circuits (
One latch circuit (52) among 51) to (53) is set.

In this way, each time a 4-bit signal is sequentially output to the data bus (3), the decoder (4) synchronizes and sequentially sets the latch circuits (51) to (53).

Then, the 4-bit signal temporarily held in the latch circuits (51) to (53) is output as a BCD signal to the signal lines (7a) to (7th line) via the isolators (8a) to (6th line). It turns out.

[Problems to be Solved by the Invention] However, in the conventional digital signal generation circuit described above, not only isolators are required for the number of signal lines that output BCD signals, but also the decoder signal that controls the set state of the latch circuit is required. There is a problem in that the number of lines must be increased in accordance with the number of signal lines that output BCD signals.

Also, BC output from signal m (7a) to (7 sentences)
The output of the D signal is performed while the signals output from the data bus (3) are sequentially latched by the latch circuits (51) to (53), resulting in a time lag, which causes the problem of not being in a stable state. be.

Therefore, an object of the present invention is to reduce the number of parts by reducing the number of isolators, and to output parallel signals such as BCD signals as simultaneously as possible to facilitate data processing after outputting the parallel signals.

[Means for Solving the Problems] Therefore, the digital signal generation circuit according to the present invention has a data line to which a serial signal is sent, a clock line to which a clock signal is sent, and a strobe line to which a strobe signal is sent. It is equipped with an isolator that blocks the influence of other electrical systems interposed in the middle of each line, and a conversion means that converts the serial signal sent from the data line into a parallel signal, and the conversion means converts the serial signal into a parallel signal. The present invention is characterized in that it is latched in synchronization with the clock signal and converted into a parallel signal, and the latched parallel signal is taken out in response to the strobe signal.

[Operation] The isolator transmits the serial signal sent from the data line to the conversion means without being influenced by other electrical systems.

The converting means converts the serial signal into a parallel signal while latching it in synchronization with the clock signal, and the latched parallel signal is taken out by the strobe signal.

[Example] An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In Figure 1, (1) is the central processing unit, (10) is the data line coming out of the central processing unit, (11) is the clock line coming out of the central processing unit (1), and (12) is the central processing bag. and strobe lines coming out from (1), (6a) to (6
(13a) to (+3c) are isolators such as photocouplers that are interposed in the middle of the data line (10), clock line (11), and strobe m (12), respectively.
is a shift register that sequentially stores and shifts the serial signal output from the data line (10) and outputs a 4-bit parallel signal. This is a signal line that outputs a signal.

Here, the shift registers (+3a) to (t3c) constitute a conversion means (14) that converts a serial signal into a parallel signal.

Next, the present invention configured as described above will be explained in detail.

The serial signal output from the data line (1o) from the central processing unit (1) is isolated by an isolator placed in the middle of the data line so that it will not be affected by other electrical systems. 1/Jista (13a
) is input.

Here, if a 4-bit signal is sequentially input to the shift register (13a) from the data line (10), each time a clock signal synchronized with data from the clock line (11) is input to the shift register (13a), The 4-bit signal is shifted and held in the shift register (13a).

Further, when a signal of one pin is output from the data line (10), it is shifted to the next shift register (+3b) and (13c).

In this way, data is sent sequentially by the clock signal, and when the data is set in each shift register (+3a) to (13c), the 4-bit BCD signal is changed to each by the strobe signal output from the strobe line (12). From the shift registers (13a) to (13c) to the signal line (7a)
) to (7 intersections).

In this case, since the speed of data output from the data line (10) can be slowed down by software, the photocoupler used as the isolator may operate at a low speed.

[Effects of the Invention] As explained above, this digital signal generation circuit is capable of isolating the serial signal by interposing an isolator in the middle of the data line to which the serial signal is sent.
Since the configuration is configured so that serial-to-parallel conversion is performed in one step after conversion, even if the number of signal lines from which parallel signals are output increases, it is sufficient to use three isolators, which has the effect of reducing the number of parts. .

Further, since the parallel signal is converted into a parallel signal by the converting means and then extracted using the strobe signal, it is possible to easily extract each digit of the parallel signal at the same time when the parallel signal is extracted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital signal generation circuit.

Claims (1)

[Claims] An isolator is inserted between the data line to which the serial signal is sent, the clock line to which the clock signal is sent, and the strobe line to which the strobe signal is sent, to cut off the influence of other electrical systems, and the above-mentioned data. and converting means for converting the serial signal sent from the line into a parallel signal, and the converting means converts the serial signal into a parallel signal while latching it in synchronization with the clock signal and latching it by the strobe signal. A digital signal generation circuit characterized in that it extracts parallel signals.