KR100266574B1 - Sinchronizing signal delay circuit - Google Patents

Abstract

PURPOSE: A circuit for delaying a synchronous signal is provided to gain synchronous delay by using a counter and a latch in case that the pulse delay width of the synchronous signal is larger of less than the delay time. CONSTITUTION: The circuit for delaying the synchronous signal includes an edge detecting portion(10), an R-down counter(20), an N-down counter portion(30) and latches(L1-Ln). The edge detecting portion(10) inputs the shortest synchronous signal(MS) and detects the edge. The R-down counter(20) counts the quantity of delay as the rest(R) by dividing the delay time(X) into the basic pulse width time(S) and outputs it to the enable signal of the latch(40). The N-down counter portion(30) counts the delay signal as N-1 of the basic pulse width time(S). The latches(L1-Ln) input the latch enable signals output from the N-down counter portion(30) and output the input signals to the latch of the rear step.

Description

Synchronous signal delay circuit

1 is a block diagram of a synchronization signal delay circuit of the present invention.

2 is a detailed circuit diagram of FIG.

3 is an output waveform and timing diagram of each part according to the operation of FIG.

* Explanation of symbols for main parts of the drawings

10: edge detector 20: R-down counter

30: N-down counter 40: latch

L ₁ to L _n : Latch

The present invention relates to delays of various synchronization signals. In particular, a synchronization signal delay suitable for obtaining a desired synchronization delay using a counter and a latch regardless of a case where the pulse delay width of the ventilation signal is larger or smaller than the delay time. It is about a circuit.

In general, in delaying a variety of synchronization data such as multi-synchronization, a delay of several clocks delays signals by connecting multiple latches in series and uses a first-in first-out memory when the delay width is large.

However, when the signal is delayed by using a latch, a latch having a proportional delay is required. Therefore, when the delay amount is relatively large, many latches are required. When using a first-in-first-out memory, the control is convenient but the cost of the memory is high. This will be.

Accordingly, the present invention can obtain the desired synchronization delay by using the counter and the latch for the case where the pulse delay width of the synchronization signal is greater or less than the delay time in order to solve the defect caused by the conventional synchronization signal delay circuit as described above. A synchronization signal delay circuit is provided.

First, in the present invention, the desired delay amount can be obtained using only the counter and the latch, regardless of whether the pulse width of the synchronization signal is greater than or less than the time to be delayed.

1 is a block diagram of a synchronization signal delay circuit of the present invention. As shown in FIG. 1, an edge detector 10 for receiving the shortest synchronization signal as a reference for delay of a synchronization signal, and detecting the edge thereof, R- which counts the delay amount by the residual R obtained by dividing the delay time X by the basic pulse width time S from the signal detected by the edge detector 10 and outputs the enable signal of the latch 40 as R-. Counted to obtain a delay signal equal to (N-1) times the basic pulse width time S by the down counter 20 and the quotient N divided by the delay time X divided by the basic pulse width time S. A latch (L ₁ -L _n ) for receiving a latch enable signal output from the N-down counter unit 30 and the latch enable signal output from the N-down counter unit 30, and outputting the input signal to the latch at a later stage. It consists of.

FIG. 2 is a circuit diagram of the embodiment of FIG. 1, and as shown in FIG. ₁ , the latches L _{1 to} L _n have n latches cascaded in series and a clock signal CLOCK is common to the clock terminals thereof. The latch enable signal EN is applied and is received from the N-down counter unit 30.

The R-down counter 20 receives initial delay data as a reference for the delay to its input terminals A to H, and counts down according to the clock clock to generate a carry R-CAR when the count is finished. Is configured to.

When the structure of the N-down counter 31 receives the initial data of the down count to the input terminals A to H similarly to the R-down counter 20 and all the specified values are counted (TRPPLE, TUPO) It is supposed to generate.

In the edge detector 10, the synchronization signals MS and FS are applied to the flip-flops FF10 and FF11, respectively, and the output Q and the synchronization signals MS and FS of the flip-flops FF10 and FF11 are respectively exclusive. Inputs are respectively input to the gates XOR10 and XOR11 and are configured such that their outputs are combined at the AND gate AND10.

The operation and effect of the circuit of the present invention configured as described above will be described in detail based on the timing diagram of FIG.

In order to obtain the signal delayed by R, the edge of the MS signal is detected, and the signal is delayed by R by using the R down counter 20 to generate a carry R_CAR when the counter 20 counts all of the specified values. .

In order to obtain a signal delayed by S × N, which is the closest to the delay time as an integer multiple of S, which is the shortest pulse, the input is as much as S using the N-down counter 31 loaded with S · N−1 values. When down counting, the latch enable signals (TUPPLE, TUPO) are generated, and the number of latches is set to N, resulting in a delay of N × S.

In this case, the N-th latch Ln is a latch for generating the final enable signal, so that the S × N delay amount can be obtained by down counting the value of N-1.

This is because the N-1 enable signal is required until the last latch enable signal is generated when the edge of the MS appears last.

First, the edge signal EDGE is generated through the AND gate AD10 for edge detection of the FW and the MS. Here the circuit is active low.

The edge detection of the FW must also take into account its delay since there is a part going low after the MS signal ends.

Then, the rest (R = 4) is loaded into the R-down counter 20 to generate the enable signal R_CAR when the result is 2, which is set in consideration of the latch result delay amount of the latch 11. .

That is, three clocks are delayed at the R-1 down counter 20 and one clock is latched at the latch 40 so that the delay to the latch L ₁ becomes four. Therefore, when latched with the R_CAR enable signal, four clocks are delayed. Get

In order to obtain the next N × S delay, the value of N · S-1 (= 15) was loaded and counted down. Therefore, 15 (HEX: F), which is (N + 1) · S-1, is set to N, Since this is 2, two latches L2 and L3 are placed.

This latch enable signal TUPO uses logic to be active low when HEX ((S · N-1) -S + 1 = 8) down S · N-1 to S with respect to the latch L2. , Will occur.

Therefore, the latch L2 loads the value of the latch L1 at the first active low.

Again, after R_CAR is input and down N-counted by 8, latch L3 latches the value of latch L2, latch L2 latches the value of latch L1, resulting in a delay of 20 clocks. (L3) you get the output.

Here, the outputs of the input latch stages L2 and L3 are correct, but the enable signal for outputting to FW "when the last enable is enabled at the output of the latch L3 is shortened by one.

That is, since the output from the end to the latch L2 is not outputted correctly or does not lead to the output of the latch L3, the enable signal must be generated so that the output to the latch L2 is outputted to the latch L3 correctly. .

Therefore, enable signals TUPPLE and TUPO are generated when the N-S value is inputted into the N-down counter 31, down-counted, and down by S.

Here, two enable signals (TUPPLE, TUPO) are generated when 8 and 0.

The two enable signals TUPPLE and TUPO are passed through the AND gate AD30 and used as an enable signal of the latch L3.

When N is a general value other than 2, since there are N latches L _{1 to} L _n , the Nth latch enable signal has a load input of S · N-1 of (S · N-1) -KS +. Each time down by 1, the enable signal is generated by the gate combination, and the resultant N inputs are input as the enable signal through the AND gate AD30.

K-1 and N-1th latches L _n-1 have N-1 enable signals through the AND gate AD30 except that the enable signal is generated when the output of the N-down counter 31 is zero. It acts as the L _n-1 latch enable signal.

As described above, the present invention has the effect of obtaining an accurate delay regardless of whether the pulse delay width of the synchronization signal is greater than or less than the delay time.

Claims (4)

The edge detection unit 10 which receives the shortest synchronization signal MS, which is a reference for the delay of the synchronization signal, detects the edge thereof, and the delay time X is determined from the signal detected by the edge detection unit 10. R-down counter 20 which counts the amount of delay divided by time S and outputs it as enable signal R_CAR of latch 40, and delay time X as the basic pulse width time. An N-down counter section 30 which counts to obtain a delay signal equal to (N-1) times the basic pulse width time S by the quotient (N) divided by (S), and the N-down counter And a latch (L _{1 to} L _n ) for receiving the latch enable signals (TUPPLE, TUPO) outputted from the unit (30) and outputting the input signal step by step to a latch at a later stage. 2. The R-down counter 20 receives initial delay data as a reference for the delay from the input terminals A to H and performs a down count according to the clock CLOCK to carry the count when the count is finished. And a signal delay circuit configured to generate a signal R_CAR. The N-down counter unit 30 is configured to carry the TUPPLE, when the initial data of the down count is input to the input terminals A to H of the N-down counter 31 and all the specified values are counted. And a TUPO to be generated and applied as a latch enable signal to the latches L _{1 to} L _n . 2. The edge detector 10 of claim 1, wherein the edge detection unit 10 is applied with the sync signals MS and FS to the flip-flops FF10 and FF11, respectively, and the output Q and the sync signal MS of the flip-flops FF10 and FF11. And FS are respectively input to exclusive OR gates (XOR10, XOR11) and their outputs are combined at AND gate (AND10).