JPS6428747A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPS6428747A
JPS6428747A JP62183531A JP18353187A JPS6428747A JP S6428747 A JPS6428747 A JP S6428747A JP 62183531 A JP62183531 A JP 62183531A JP 18353187 A JP18353187 A JP 18353187A JP S6428747 A JPS6428747 A JP S6428747A
Authority
JP
Japan
Prior art keywords
cycle
period
input
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183531A
Other languages
Japanese (ja)
Inventor
Toshirou Harui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62183531A priority Critical patent/JPS6428747A/en
Publication of JPS6428747A publication Critical patent/JPS6428747A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily check the malfunction of a microprocessor from the external by outputting contents of an arbitrary internal register to the external at the timing when a data input/output terminal is not used. CONSTITUTION:At the time of input, an external resource designated by an address outputs data during the period from the latter half of a cycle S2 to the first half of a cycle S3 out of cycles S0-S3 because a microprocessor 10 takes data inputted from a data input/output terminal 8 into an input data buffer 7 by the last of an instruction. At the time of output, the processor 10 outputs data written in an output data buffer 5 to the external through the data input/output terminal 8 during the period from the latter half of the cycle S1 to the first half of the cycle S3 and outputs a write strobe signal in the period of the cycle S2. Since the data input/output terminal 8 is not used in the period of the cycle S0 in case of input as well as output, contents of a test register 4 are outputted to the terminal 8 in this period. At the time of checking the malfunction by the processor 10, the code of the register whose change of contents should be checked is preliminarily set to a register selecting circuit 3.
JP62183531A 1987-07-24 1987-07-24 Microprocessor Pending JPS6428747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183531A JPS6428747A (en) 1987-07-24 1987-07-24 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183531A JPS6428747A (en) 1987-07-24 1987-07-24 Microprocessor

Publications (1)

Publication Number Publication Date
JPS6428747A true JPS6428747A (en) 1989-01-31

Family

ID=16137461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183531A Pending JPS6428747A (en) 1987-07-24 1987-07-24 Microprocessor

Country Status (1)

Country Link
JP (1) JPS6428747A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH086918A (en) * 1994-06-15 1996-01-12 Nec Corp Microcomputer
US5872961A (en) * 1991-05-29 1999-02-16 Nec Corporation Microcomputer allowing external monitoring of internal resources

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872961A (en) * 1991-05-29 1999-02-16 Nec Corporation Microcomputer allowing external monitoring of internal resources
JPH086918A (en) * 1994-06-15 1996-01-12 Nec Corp Microcomputer

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