JPS5461438A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5461438A
JPS5461438A JP12757477A JP12757477A JPS5461438A JP S5461438 A JPS5461438 A JP S5461438A JP 12757477 A JP12757477 A JP 12757477A JP 12757477 A JP12757477 A JP 12757477A JP S5461438 A JPS5461438 A JP S5461438A
Authority
JP
Japan
Prior art keywords
mode
register
history
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12757477A
Other languages
Japanese (ja)
Inventor
Hiroto Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12757477A priority Critical patent/JPS5461438A/en
Publication of JPS5461438A publication Critical patent/JPS5461438A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To enable to take desired history of register, by changing over the mode given at first, through the detection of the error state when intermittent error is taken place and through the designation of mode according to the types of error.
CONSTITUTION: The output from the failure detection circuit 1 is delivered to the mode register 4 with the state analysis circuit 2 and the state analysis circuit 3 constituted with the firm ware performing further detailed analysis. The register 4 is set to a given value with the result of analysis of the dircuits 2 and 3 and either of the data mode signals MDo to MDm is selected with this. Further, the content of the entire block 5 such as registers in information processor, device table and logic circuits is selected with the data mode signals MDo to MDm and is led to the mode operation circuit 6 subsequent and after that, it is stored in n3 words of the history data areas HRo to HR n3 of the history registor 7. Then, the stored data is displayed externally with the history register display circuit 8
COPYRIGHT: (C)1979,JPO&Japio
JP12757477A 1977-10-26 1977-10-26 Information processor Pending JPS5461438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12757477A JPS5461438A (en) 1977-10-26 1977-10-26 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12757477A JPS5461438A (en) 1977-10-26 1977-10-26 Information processor

Publications (1)

Publication Number Publication Date
JPS5461438A true JPS5461438A (en) 1979-05-17

Family

ID=14963408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12757477A Pending JPS5461438A (en) 1977-10-26 1977-10-26 Information processor

Country Status (1)

Country Link
JP (1) JPS5461438A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105964329A (en) * 2015-03-11 2016-09-28 株式会社佐竹 Control device of grain preparation equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105964329A (en) * 2015-03-11 2016-09-28 株式会社佐竹 Control device of grain preparation equipment

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