JPS54146939A - Abnormal waveform detection display system using logic scope - Google Patents

Abnormal waveform detection display system using logic scope

Info

Publication number
JPS54146939A
JPS54146939A JP5527278A JP5527278A JPS54146939A JP S54146939 A JPS54146939 A JP S54146939A JP 5527278 A JP5527278 A JP 5527278A JP 5527278 A JP5527278 A JP 5527278A JP S54146939 A JPS54146939 A JP S54146939A
Authority
JP
Japan
Prior art keywords
ecc
check
circuit
inspection
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5527278A
Other languages
Japanese (ja)
Inventor
Takehisa Miyagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5527278A priority Critical patent/JPS54146939A/en
Publication of JPS54146939A publication Critical patent/JPS54146939A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain simply and surely error-on signals to detect and display abnormal waveforms by providing an ECC check circuit, etc., in a logic scope and using ECC for normal waveforms to check waveforms.
CONSTITUTION: When inspection signal S1 of an inspected circuit is a normal waveform, the ECC part is written in ECC storage register 9. Next, inspection signals S1 are inputted to sequential waveform displaying memory 7 and ECC check circuit 8 line by line. ECC check circuit 8 uses ECC from ECC part storage register 9 to check inspection signals S1; and if an error is detected in inspection signals S1 as the result, error-on signal S2 and inspection signal S1 are inputted to ECC check control.ECC analysis control circuit 10. Then, control circuit 10 stops the update of memory 7 and displays memory contents at this time on display screen 14.
COPYRIGHT: (C)1979,JPO&Japio
JP5527278A 1978-05-10 1978-05-10 Abnormal waveform detection display system using logic scope Pending JPS54146939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5527278A JPS54146939A (en) 1978-05-10 1978-05-10 Abnormal waveform detection display system using logic scope

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5527278A JPS54146939A (en) 1978-05-10 1978-05-10 Abnormal waveform detection display system using logic scope

Publications (1)

Publication Number Publication Date
JPS54146939A true JPS54146939A (en) 1979-11-16

Family

ID=12993958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5527278A Pending JPS54146939A (en) 1978-05-10 1978-05-10 Abnormal waveform detection display system using logic scope

Country Status (1)

Country Link
JP (1) JPS54146939A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2481461A1 (en) * 1980-04-25 1981-10-30 Radiotechnique Compelec Programmable pulse length tester for ATE - uses registers in cascade for memorising pulse sequence for comparison with reference

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2481461A1 (en) * 1980-04-25 1981-10-30 Radiotechnique Compelec Programmable pulse length tester for ATE - uses registers in cascade for memorising pulse sequence for comparison with reference

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