JPS57203149A - Microprocessor analyzer - Google Patents

Microprocessor analyzer

Info

Publication number
JPS57203149A
JPS57203149A JP56087825A JP8782581A JPS57203149A JP S57203149 A JPS57203149 A JP S57203149A JP 56087825 A JP56087825 A JP 56087825A JP 8782581 A JP8782581 A JP 8782581A JP S57203149 A JPS57203149 A JP S57203149A
Authority
JP
Japan
Prior art keywords
memory
bus
data
fault
tsw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56087825A
Other languages
Japanese (ja)
Inventor
Kazuaki Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp, Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Electric Corp
Priority to JP56087825A priority Critical patent/JPS57203149A/en
Publication of JPS57203149A publication Critical patent/JPS57203149A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To speed up an analysis of a fault by forecasting several sequence elements which may cause a fault mode, and storing a memory with data on a bus during the sequence execution of the elements. CONSTITUTION:Under the control of a control circuit 5, a multiplexer MX3 is changed over to the side of an internal data bus D, a predetermined trace word TSW is applied to a detection memory 4, and a write signal (e) is supplied to write 1 in the memory 4. Further, a trigger word TGW indicating a specific fault mode is set in a register previously. Then, the MX3 is connected to an external data bus D1 to operate an external equipment. Every time the TSW appears on the bus D1, the memory 4 outputs a detection pulse P to a pulse width generating circuit 8 and while a write signal C is 1, a constant-width pulse is inputted from the circuit 8 to a memory 10 to write the sequence data on the bus D1 in the memory 10. Once the bus D1 has a fault, fault data is compared with the TGW in the register 1 by a comparator 2 and data near the TSW in the memory 10 is displayed on a display part 11.
JP56087825A 1981-06-08 1981-06-08 Microprocessor analyzer Pending JPS57203149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56087825A JPS57203149A (en) 1981-06-08 1981-06-08 Microprocessor analyzer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56087825A JPS57203149A (en) 1981-06-08 1981-06-08 Microprocessor analyzer

Publications (1)

Publication Number Publication Date
JPS57203149A true JPS57203149A (en) 1982-12-13

Family

ID=13925723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56087825A Pending JPS57203149A (en) 1981-06-08 1981-06-08 Microprocessor analyzer

Country Status (1)

Country Link
JP (1) JPS57203149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59216256A (en) * 1983-05-24 1984-12-06 Iwatsu Electric Co Ltd Operation analyzing device of microprocessor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136841A (en) * 1974-09-17 1976-03-27 Nippon Electric Co
JPS5421149A (en) * 1977-07-18 1979-02-17 Toshiba Corp Memory unit for input and output bus information

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136841A (en) * 1974-09-17 1976-03-27 Nippon Electric Co
JPS5421149A (en) * 1977-07-18 1979-02-17 Toshiba Corp Memory unit for input and output bus information

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59216256A (en) * 1983-05-24 1984-12-06 Iwatsu Electric Co Ltd Operation analyzing device of microprocessor
JPS6342296B2 (en) * 1983-05-24 1988-08-23 Iwasaki Tsushinki Kk

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