JPS5764396A - Multi-processor - Google Patents
Multi-processorInfo
- Publication number
- JPS5764396A JPS5764396A JP55137798A JP13779880A JPS5764396A JP S5764396 A JPS5764396 A JP S5764396A JP 55137798 A JP55137798 A JP 55137798A JP 13779880 A JP13779880 A JP 13779880A JP S5764396 A JPS5764396 A JP S5764396A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- address
- inputted
- counter
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To elevate the reliability of a multi-processor, by confirming an output data of a memory, which is inputted to a program counter, by a address checking circuit, also outputting a signal in the event of a fault, and executing a memory access again. CONSTITUTION:When a clock pulse CLK is applied to a program counter 2, an address signal (e) is inputted to an address checking circuit 3 and a memory 1, and a signal (c) which has passed through a decoding circuit 4, in a data signal (a) outputted by the memory 1 is inputted to the counter 2 and the checking circuit 3. When the address signal (e) or a jump address signal (d) is inputted to the check- ing circuit 3, whether said signal has been set to the counter 2 or not is confirmed, a signal (f) is outputted in the event of a fault, a timing controlling circuit 6 outputs a strobe signal (g) to the counter 2, and a memory access is executed again from the same address. In this way, the reliability of a multi-processor is elevated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55137798A JPS6059608B2 (en) | 1980-10-03 | 1980-10-03 | multiprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55137798A JPS6059608B2 (en) | 1980-10-03 | 1980-10-03 | multiprocessor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5764396A true JPS5764396A (en) | 1982-04-19 |
JPS6059608B2 JPS6059608B2 (en) | 1985-12-26 |
Family
ID=15207092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55137798A Expired JPS6059608B2 (en) | 1980-10-03 | 1980-10-03 | multiprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6059608B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61234456A (en) * | 1985-04-11 | 1986-10-18 | Nippon Denso Co Ltd | On-vehicle controller |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6418302A (en) * | 1987-07-14 | 1989-01-23 | Futaba Denki Kk | Antenna |
JPH01126710U (en) * | 1988-02-23 | 1989-08-30 | ||
JPH0327110U (en) * | 1989-07-25 | 1991-03-19 |
-
1980
- 1980-10-03 JP JP55137798A patent/JPS6059608B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61234456A (en) * | 1985-04-11 | 1986-10-18 | Nippon Denso Co Ltd | On-vehicle controller |
Also Published As
Publication number | Publication date |
---|---|
JPS6059608B2 (en) | 1985-12-26 |
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