JPS6488858A - Interface circuit - Google Patents

Abstract

PURPOSE:To suitably obtain an IC and to prevent the data of a timing from being written to an erroneous data accumulating means or from being read from the erroneous data accumulating means by providing a control signal generating circuit. CONSTITUTION:A reset signal R is supplied to AND gates 52 and 54 of a reset signal forming circuit, which is provided in an interface circuit, and an NAND gate 55. While the signal R goes to be true, in case that a clock CK is detected with succeeding twice or in larger number times, a signal is generated to reset a quaternary counter from the non-inverting output terminal of an FF 56. In the interface circuit, an increment signal preparing circuit is provided further and when an increment signal is supplied, the increment signal is outputted through the inside AND gate or the FF, etc., to the quaternary counter. Thus, by providing the reset and increment signal generating circuits and controlling the counter, a writing to the erroneous data accumulating means or a reading can be avoided.