JPS5635239A - Data memory device - Google Patents

Data memory device

Info

Publication number
JPS5635239A
JPS5635239A JP11042579A JP11042579A JPS5635239A JP S5635239 A JPS5635239 A JP S5635239A JP 11042579 A JP11042579 A JP 11042579A JP 11042579 A JP11042579 A JP 11042579A JP S5635239 A JPS5635239 A JP S5635239A
Authority
JP
Japan
Prior art keywords
data
signal
circuit
written
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11042579A
Other languages
Japanese (ja)
Other versions
JPS6242287B2 (en
Inventor
Hideaki Iemura
Yoshiaki Furuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11042579A priority Critical patent/JPS5635239A/en
Publication of JPS5635239A publication Critical patent/JPS5635239A/en
Publication of JPS6242287B2 publication Critical patent/JPS6242287B2/ja
Granted legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To realize a reduction of the hard quantity of assurance of the data level, by utilizing the function of the memory circuit provided and carrying out both the writing and reading for the memory circuit to realize the same function.
CONSTITUTION: When the data signal 101 for chattering of the data key has a change after the data is written into the memory circuit 10, the signal 101 becomes equal to the reading signal 104 of the circuit 10. Here the output of the comparator 13 has a high rank, and the writing indication signal 105 is delivered from the AND gate 12 and in synchronization with the clock signal CL1 to be written again into the circuit 10 corresponding to the data pressed down. This action is repeated until the output of the circuit 13 has a low rank. And finally the signal written into the circuit 10 turns into the correct data with elimination of the noise. In such way, the hard quantity can be reduced.
COPYRIGHT: (C)1981,JPO&Japio
JP11042579A 1979-08-31 1979-08-31 Data memory device Granted JPS5635239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11042579A JPS5635239A (en) 1979-08-31 1979-08-31 Data memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11042579A JPS5635239A (en) 1979-08-31 1979-08-31 Data memory device

Publications (2)

Publication Number Publication Date
JPS5635239A true JPS5635239A (en) 1981-04-07
JPS6242287B2 JPS6242287B2 (en) 1987-09-08

Family

ID=14535423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11042579A Granted JPS5635239A (en) 1979-08-31 1979-08-31 Data memory device

Country Status (1)

Country Link
JP (1) JPS5635239A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57185037U (en) * 1981-05-18 1982-11-24

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092641A (en) * 1973-12-14 1975-07-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092641A (en) * 1973-12-14 1975-07-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57185037U (en) * 1981-05-18 1982-11-24

Also Published As

Publication number Publication date
JPS6242287B2 (en) 1987-09-08

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