JPS554604A - Buffer register - Google Patents

Buffer register

Info

Publication number
JPS554604A
JPS554604A JP7638078A JP7638078A JPS554604A JP S554604 A JPS554604 A JP S554604A JP 7638078 A JP7638078 A JP 7638078A JP 7638078 A JP7638078 A JP 7638078A JP S554604 A JPS554604 A JP S554604A
Authority
JP
Japan
Prior art keywords
bit
register
supply
content
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7638078A
Other languages
Japanese (ja)
Inventor
Masao Yamazawa
Tetsuo Soejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7638078A priority Critical patent/JPS554604A/en
Publication of JPS554604A publication Critical patent/JPS554604A/en
Pending legal-status Critical Current

Links

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE: To store desired N-bit data definitely with simple circuit constitution by reading the data into a shift register when the content of the "N"-th bit is shifted to the terminal bit of the shift register and by stopping the supply of clocks.
CONSTITUTION: Shift register 3 with a capacity for at least "N+1" bits and detection circuit 34 which generates a detection output on detecting the timing of a read start signal are both provided and the contents of "N-1" of register 3 are set either logical state by the detection output. Then, the content of the "N"-th bit from the hind terminal of register 3 is set to the other logical state; the supply of a read clock to register 3 starts on the generation of the detection output through control 39 while the supply of the read clock to register3 stops on the shift of the "N"-th bit content to the terminal bit of register. Consequently, the circuit constitution is simplified and desired N-bit data can definitely be stored.
COPYRIGHT: (C)1980,JPO&Japio
JP7638078A 1978-06-26 1978-06-26 Buffer register Pending JPS554604A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7638078A JPS554604A (en) 1978-06-26 1978-06-26 Buffer register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7638078A JPS554604A (en) 1978-06-26 1978-06-26 Buffer register

Publications (1)

Publication Number Publication Date
JPS554604A true JPS554604A (en) 1980-01-14

Family

ID=13603722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7638078A Pending JPS554604A (en) 1978-06-26 1978-06-26 Buffer register

Country Status (1)

Country Link
JP (1) JPS554604A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06110654A (en) * 1992-03-11 1994-04-22 Samsung Electron Co Ltd Data-coincidence detecting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06110654A (en) * 1992-03-11 1994-04-22 Samsung Electron Co Ltd Data-coincidence detecting circuit
JP3080341B2 (en) * 1992-03-11 2000-08-28 三星電子株式会社 Data match detection circuit

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