JPS5640952A - Microprogram control system - Google Patents

Abstract

PURPOSE: To ensure an assured reading of the data in accordance with the microorder including the memory control, by giving a writing control to the next microorder in an integer-fold cycle compared with the basic cycle when the microorder is written into the instruction register.

CONSTITUTION: With supply of the 0 signal from the cycle selection circuit 4, the counter 2 counts down the pulses supplied from the pulse generator 1 and then counts up the pulses with supply of the 1 signal. The output of the counter 2 is supplied to the decoder 3, and the output is generated at the outputs A and B and in correspondence to the count contents 0 and 1 supplied to the decoder 3 to be then supplied to the cycle selection circuit 4. When the instruction including no memory control is written into the register 8, the 0 signal is delivered from the decoder 9. Thus the 1 signal is generated from the selection circuit, and accordingly the pulse is generated from the clock pulse generator 5 via the pulse supplied from the generator 1. And the next instruction is written into the register 8. When the instruction including the memory control is written into the register 8, the 1 signal is delivered from the decoder 9. And the instruction is written in the double cycle time compared with the basic cycle time.

COPYRIGHT: (C)1981,JPO&Japio