JPS54158120A - Signal phase conversion device - Google Patents

Signal phase conversion device

Info

Publication number
JPS54158120A
JPS54158120A JP6748878A JP6748878A JPS54158120A JP S54158120 A JPS54158120 A JP S54158120A JP 6748878 A JP6748878 A JP 6748878A JP 6748878 A JP6748878 A JP 6748878A JP S54158120 A JPS54158120 A JP S54158120A
Authority
JP
Japan
Prior art keywords
memory unit
main memory
state
digital information
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6748878A
Other languages
Japanese (ja)
Other versions
JPS6160625B2 (en
Inventor
Yoshikazu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6748878A priority Critical patent/JPS54158120A/en
Publication of JPS54158120A publication Critical patent/JPS54158120A/en
Publication of JPS6160625B2 publication Critical patent/JPS6160625B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To secure is simple detection of occurrence of the outrunning by memorizing the display symbol showing the eriting or reading state at the main memory unit into the secondary memory unit.
CONSTITUTION: The clock signal relating the digital information signal is drawn out, and the digital information signals are written in sequence into the fixed addresses of the main memory unit based on the drawon-out clock signal. After this, the digital information signals are read out in sequence from the main memory unit via the reference clock signal. On the other hand, the display signal showing the writing state in synchronization with the writing action to the main memory unit is memorized into the secondary memory unit. At the same time, the display signal showing the reading state in synchronization with the reading action is memorized in the secondary memory unit. Then the outtunning state is detected for the writing or reading action to the main memory via the signals read out from the secondary memory unit.
COPYRIGHT: (C)1979,JPO&Japio
JP6748878A 1978-06-05 1978-06-05 Signal phase conversion device Granted JPS54158120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6748878A JPS54158120A (en) 1978-06-05 1978-06-05 Signal phase conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6748878A JPS54158120A (en) 1978-06-05 1978-06-05 Signal phase conversion device

Publications (2)

Publication Number Publication Date
JPS54158120A true JPS54158120A (en) 1979-12-13
JPS6160625B2 JPS6160625B2 (en) 1986-12-22

Family

ID=13346405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6748878A Granted JPS54158120A (en) 1978-06-05 1978-06-05 Signal phase conversion device

Country Status (1)

Country Link
JP (1) JPS54158120A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240726A (en) * 1985-04-17 1986-10-27 Nec Corp Memory circuit device
JPS63224538A (en) * 1987-03-14 1988-09-19 Fujitsu Ltd Synchronizing control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240726A (en) * 1985-04-17 1986-10-27 Nec Corp Memory circuit device
JPS63224538A (en) * 1987-03-14 1988-09-19 Fujitsu Ltd Synchronizing control circuit
JPH0559623B2 (en) * 1987-03-14 1993-08-31 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6160625B2 (en) 1986-12-22

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