JPS6160625B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal phase conversion device suitable for application to a memory control device used in a frame synchronizer or the like.

Currently, a frame synchronizer is being developed as a method for synchronizing video signals sent and received between broadcast stations. The frame synchronizer uses a memory with a memory capacity for one frame (or one field), writes the digital signal of the input video signal with a clock pulse synchronized with the input video signal, and reads data from a key station asynchronous to the writing clock pulse. This is done by using the reference clock pulse of 2000, from which a video signal coupled to the reference clock is obtained.

FIG. 1 is a system diagram of the main parts of an example of a memory control device used in this frame synchronizer. In this example, the memory section is divided into two memory blocks.

1 is the video signal sent from the local station or
An input terminal for a reproduced video signal from a VTR, 2 a synchronization separation circuit, and 3 a clock pulse generation circuit.
4 is an A/D conversion circuit which performs A/D conversion using a clock pulse synchronized with the input video signal. In this example, one sample is digitally converted into 8 bits, this input digital signal is supplied to an input buffer circuit 5 for serial-to-parallel conversion, and the input digital signal for M samples is converted into a parallel signal. When composed of two buffer circuits 5A and 5B,
These circuits 5A and 5B sequentially convert input digital signals into parallel digital signals.

After M samples have been parallel-converted, the parallel digital signals are sequentially written into the corresponding memory blocks 6A and 6B of the memory 6. 7 is a memory control circuit on the writing side.

The read operation is performed as follows. Reference numeral 8 denotes a reference signal generation circuit, which has a frequency of 3.58 MHz. This reference signal is supplied to a reference clock pulse generation circuit 9, and the reference signal is multiplied by 4, for example, to form a reference clock pulse. 10 is a memory control circuit on the read side.

The data (parallel digital signals) sequentially read out from the memory blocks 6A and 6B are converted into series by output buffer circuits 11A and 11B for parallel-to-serial conversion, and the converted serial digital signals are subjected to DA conversion at the subsequent stage. The signal is supplied to the circuit 12 and decoded into an input video signal.

Since the decoded video signal is synchronized with the reference signal, even if the synchronization relationship with the input video signal is asynchronous, a video signal synchronously coupled to the key station can be obtained.

By the way, asynchrony between input and output of video signals is manifested as asynchrony between write requests and read requests to the memory unit 6, so if the synchronization is off, a write request and a read request will occur to the same memory block at the same time. obtain.

When a MOS-RAM is used as a memory element, writing and reading cannot be performed on the RAM at the same time, so in order to avoid the above-mentioned situation, one conventional solution was to divide one memory cycle into one cycle of the RAM, which is a memory element. 3 times the time, and adopt a method of dividing this one memory cycle into three phases. By allocating the third phase to a phase dedicated to read access and allocating the other phases to phases dedicated to write access, write and read deletions are prevented.

However, with this configuration, the capacity of the buffer circuit increases; for example, if M=8, the capacity of the buffer circuit increases.
Since one buffer capacity is required for 24 samples, a buffer register for 96 samples is required in total.

Now, if we configure the memory using RAM with a cycle time of 400nS and a capacity of 16K,
When the frequency of clock pulses WC and RC is 4sc, in the configuration shown in Figure 1, the number of samples M for parallelizing data must be M = 7, so the total memory capacity is 672K samples (16K
x 3 phases x 7 samples x 2 times). Therefore, this configuration has the drawback that the required maximum capacity (477750 samples) for one frame is greatly exceeded, resulting in a large amount of wasted capacity.

Furthermore, this configuration requires memory control circuits 7 and 10 on the write side and the read side, respectively, making it impossible to share the circuits and making it impossible to simplify the configuration.

The configuration shown in Figure 2 takes these points into consideration, and it eliminates input data write errors due to asynchrony between input and output, and also reduces the memory capacity required by the device by minimizing wasted capacity. It is a diagram.

In this example, the frame or field memory section 6 is divided into N memory blocks. The example shows a case study with N=4. On the input side of the four memory blocks 6A to 6D, input buffer circuits 5A to 5 for converting input digital signals from serial to parallel are provided.
D is provided, and on the output side, an output buffer circuit for parallel-to-serial conversion is provided in common for every other memory block. Therefore, the output buffer circuit 11 for memory blocks 6A and 6C
An output buffer circuit 11B is provided for the remaining memory blocks 6B and 6D.

And each input/output buffer circuit 5A to 5D,
Each buffer capacity of 11A and 11B is selected to have a write capacity for one memory cycle of the memory block.

15 is a multiplexer. Reference numeral 16 denotes a control circuit for controlling writing and reading, and the writing and reading execution timings are both synchronously coupled to the reference phase of the key station. The write request signal is obtained in synchronization with the input video signal as in the conventional case. 1
7 is a cycle counter on the write side, and a write cycle pulse WCC is obtained every M samples. 18
is a cycle counter on the read side.

The basic operation of this device is as follows.

One memory cycle is selected as one cycle time of a memory element (RAM) constituting a memory block.

The digital outputs are sequentially written to the corresponding memory blocks every memory cycle. In this case, since the write request and the memory cycle are asynchronous, the write request occurs in the middle of the memory cycle. The write request is then executed at the beginning of the next memory cycle. In other words, the writing side makes concessions to the reading side.

When write requests to different memory blocks occur within the same memory cycle, write operations are performed to those memory blocks simultaneously.

The memory contents of the memory block are read out sequentially in each memory cycle. In this case, when a request for a read operation is made after receiving a write request, the CPU yields to the write side and transfers the read execution to the memory cycle after the write operation.

If the reading side yields to the writing side, a break will occur in the data series that was uninterrupted at the time of input.
Output buffer circuit 1
The read timing of 1A and 11B is determined.

FIG. 3 shows a specific circuit of the device shown in FIG. The configuration and operation will be explained along the signal path.

A clock pulse WC (W indicates the input side, that is, the write side; the same applies hereinafter) synchronized with the input video signal supplied to the terminal 3a is supplied to the write cycle counter 17, and a cycle pulse WCC (the clock pulse WCC indicating the start of the write cycle) is supplied to the write cycle counter 17. 4A) is formed, and this pulse WCC is supplied to the address counter 21. The counter 21 is used to designate physical addresses for the memory blocks 6A to 6D, and the lower two bits of the counter output of the counter 21 are used as a block designation pulse WB.

WCCBR is a borrow signal obtained from the cycle counter 17, which is supplied to the multiplexer 22, and the control signal WCBR designated according to the block designation pulse WB is applied to each memory block 6A to 6A.
6D are sequentially supplied to corresponding control circuits 16A to 16D. An example of the control signal _WCBR0 is shown in FIG. 4B. 24 is the enable signal WEN ₀ ~ _{WEN 3}
Gate circuits 25A to 2 sequentially corresponding to each sample
This is a multiplexer for supplying 5D.

On the other hand, a reference clock pulse RC (R indicates the read side) of the read side, that is, the key station is supplied to the terminal 9a.
Similarly to the write side, the cycle counter 18 generates a pulse RCC (FIG. 4F) indicating the beginning of the read cycle, and the borrow signal RCCBR of the cycle counter 18 is supplied to the multiplexer 32, and a block command is generated. pulse
The control signal RCBR is sequentially distributed at the RB and supplied to each control circuit 16A to 16D. Control circuit 1
The control signal RCBR ₀ supplied to 6A is shown in FIG. 4G.

Next, the write operation will be explained, but the control circuit 16A
The RS-flip-flop circuit 35A is set by the control signal WCBR ₀ supplied to the memory block 6A, and a write request signal is sent from the Q terminal to the memory block 6A.
WREQ ⁰ (FIG. 4C) is generated and is applied to the D input of D-flip-flop circuit 36A. If the cycle pulse RCC on the read side has a phase difference with the cycle pulse WCC on the write side as shown in the figure, the Q output of the flip-flop circuit 35A rises at the time when the cycle pulse RCC is obtained immediately after the control signal WCBR ₀ is input. Since the write execution command signal WE ₀ (FIG. 4D) is obtained, at this point the parallel digital signals of the input buffer circuit 5A are written into the desired memory of the memory block 6A.

The RS-flip-flop circuit 35A is reset by the AND output WAND (Fig. 4E) of the cycle pulse RCC and the write execution command signal _WE0 .
As a result, the Q of the D-flip-flop circuit 36A is
Since the output is inverted, writing is performed only during period T.

When a write request is made in the middle of a memory cycle in this way, the write is not executed immediately, but is executed for a period T from the beginning of the next memory cycle.

Next, the operation of reading data written in the memory block 6A will be explained. The control signal RCBR ₀ in FIG. 4G is the RS-flip-flop circuit 37.
When supplied to A, the read request signal RREQ ₀ (fourth
Figure H) is obtained, and this and the write request signal WREQ ₀
The AND output RAND (J in the same figure) of the inverted signal WREQ ₀ ' (in the same figure) is supplied to the D-flip-flop circuit 38A, so that at the beginning of the memory cycle following the memory cycle in which the read request was issued. A read execution command signal RE ₀ (K in the figure) is obtained at a certain cycle pulse RCC ₁ .

The RS-flip-flop circuit 37A is reset by the NAND output of the read execution command signal RE ₀ and the cycle pulse RCC ₁ (L in the same figure), and since the read execution command signal RE ₀ is obtained only during the period T, the data cannot be read during this period. Reading is performed.

Note that, after data is read, when this data is serially converted and supplied to the terminal 15a, the read request is made taking this into consideration in order to ensure that there is no interruption in the flow of the serially converted output. It is determined that the serial conversion output is obtained in the third cycle from the time when Therefore, the output buffer circuit 11
The load signal PSLD supplied to A and 11B and the enable signal PSEN for enabling the parallel-to-serial conversion clock pulse (inverted pulse of the reference clock pulse RC) are formed as follows.

As the load signal PSLD _A supplied to the output buffer circuit 11A, the AND output of the OR output of the read execution command signals RE ₀ and RE ₂ supplied to the blocks 6A and 6C and the borrow signal RCCBR is used.
On the other hand, the other load signal PSLD _B differs only in the formation of the OR output, and the OR output of the read execution command signals RE ₁ and RE ₃ is used.

The enable signal PSEN _A is a signal that is inverted every memory cycle, and in this example, the counter output of the address counter 31 is used. The other enable signal PSEN _B is an inverted enable signal
PSEN _A ′.

Therefore, as shown by G and N in FIG. 4, the output buffer circuit _11A is configured such that a serial digital signal is obtained from the output buffer circuit 11A corresponding to the block 6A in the third cycle after the read request signal RREQ 0 is generated. Enable signal supplied to
The signal level (polarity) of PSEN _A is determined. In this example, "1" is enabled.

In this way, in the case shown in FIG. 4, a continuous input video signal can be obtained that is synchronized with the key station.

By the way, since the write operation and read operation are asynchronous, the data rate is such that the memory cycle is longer than the write cycle and two or more cycle pulses WCC are included in one memory cycle, as shown in Figure 5. In the case, two write requests may occur within a memory cycle starting from time _t1 .

In such a case, writing is executed simultaneously to two different memory blocks in the memory cycle starting from time _t2 . A time chart in that case is shown in FIG. The numbers given in the figure correspond to memory blocks 16A to 16D ("0" is 16A, "1" is 16B, etc.). In FIG. E, cycles numbered 2 or more within the same cycle indicate execution of simultaneous writing.

Next, a read operation at such a data rate will be explained. First, regarding the memory block 6A, when _the writing shown in FIG _. is supplied, the read execution command signal _RE0 of H in the figure is generated, and at this point the data in the memory block 6A is read out.

Control circuit 16B of second memory block 6B
The write and read request signals WCBR ₁ ' and RCBR ₁ shown in I and J of the same figure are supplied to the third memory block 6C, and the request signals L and M of the same figure are supplied to the third memory block 6C.
WCBR ₂ ' and RCBR ₂ are supplied, and the read request signals RCBR ₁ and RCBR ₂ fall simultaneously, so the second
The read execution command signals RE ₁ and RE ₂ are simultaneously generated for the third memory blocks 6B and 6C. Therefore, data is read simultaneously.

As a result of the above, the read operation is as shown in FIG. 5R, and data is read out without interruption in a regular time series.

Here, if we take the above-mentioned operations into consideration, the read request signal RREQ ₁ for the block 6B is generated at the end of _the memory cycle _M1 shown in FIG. Write request signal for 6B
Since WREQ ₁ is obtained, a concession is made to the write side, and the read operation will not be executed in the next memory cycle _M2 , but will be executed in the next memory cycle _M3 (K in the figure).

Data is loaded into the output buffer circuit 11B by the load signal PSLD _B generated at the end of memory cycle _M3 , and data is loaded into the output buffer circuit 11B at the same time as the load signal PSLD B generated at the end of memory cycle M3.
Serial output is performed at M ₄ (third cycle after request signal RREQ ₁ is obtained).

On the other hand, at the end of memory cycle _M2 , the read request signal for block 6C is
When RREQ ₂ is obtained, that memory cycle
Since writing to this block 6C has already been completed in _M2 , this request signal RREQ ₂ is immediately accepted, and data reading is executed in the next memory cycle _M3 (same as above). Figure N).

The read data is loaded into the output buffer circuit 11A by the load signal PSLD _A generated at the end of memory cycle _M3 . However, if the output buffer circuit 11B is enabled in the following memory cycle _M4 , the other output buffer circuit 11A is enabled in the next memory cycle _M5 , so the data in block 6C is serially output in memory cycle _M5 . be done.

The same applies even if the data rate is reversed to that shown in FIG.

In addition, when writing operations are executed simultaneously within the same memory cycle as shown in FIG. 6, writing is performed to the same address in memory blocks 6A and 6B of "0, 1" as shown in FIG. 6E. However, in the case of "3,0", the address for memory block 6D and the address for memory block 6A are
The addresses for are different. Therefore, an address information holder (not particularly shown) is actually provided between blocks 6B and 6C, and address information is supplied to blocks 6C and 6D via the holder. The read execution command signal WE ₀ may be used to transfer the address and information to the holder.

In FIG. 2, the memory device is constructed by dividing into four memory blocks for the following reason. As shown in Fig. 5, if the periods of clock pulses WC and RC are T _W and T _R and one cycle is M samples, one cycle is M _W ,
It becomes _MTR . Now, while the converted digital signal of a certain input buffer circuit is being stored in the memory, the input buffer that is necessary to prevent the next new data from being input to the same input buffer circuit and causing a data write error. The number of circuits is N
Then, (N-1)MT _W 2MT _R ...(1) must be satisfied. Equation (1) becomes N2T _R /T _W +1 (2). From FIG. 5, since TR>T _W , the smallest integer in equation (2) that satisfies this condition is 4.

If N=4, it is possible to deal with time axis fluctuations up to T _R /T _W 3/2, so N=4 is actually sufficient. Therefore, the memory can be divided into four memory blocks.

Note that, as is clear from equation (2), the number of memory divisions N is unrelated to the buffer capacity M, and in this example, as stated earlier, the buffer capacity M is equal to the write capacity of the memory block for one memory cycle. selected.

According to the configuration shown in Figure 3, when the input video signal has time axis fluctuations and write requests are made to different memory blocks within the same memory cycle, the writes are executed simultaneously in the next memory cycle. , can easily absorb time axis fluctuations. By increasing the number of input buffer circuits to four, writing errors in input data can be eliminated.

If a write request and a read request are received for the same memory block at the same time, the write operation is prioritized (however, the execution timing is synchronized with the read side timing), and the read operation is executed next. Since it is used for memory cycles, one memory cycle time is
Simultaneous access can be solved by making it equal to one cycle time of RAM. However, the data interruption that occurs in this case is handled by the two output buffer circuits as described above.

In this way, the buffer capacity can be significantly reduced compared to the conventional method. While conventional methods require memory capacity for 672K samples, this configuration requires M
By simply setting = 8, the result is 524,288 samples (16K x 8 samples x 4 samples), which makes it possible to significantly reduce memory capacity compared to the conventional method, and improve cost performance.

Also, since the write execution is synchronized with the reference clock RC on the read side, memory blocks 6A to 6D
On the other hand, only one control circuit 16A to 16D is required for each, and there is no need for control circuits for each of the reading and writing sides as in the conventional case.

By the way, if the data rate T _W of the input information signal is different from the data rate T _R of the reference signal, after some time has elapsed, for example, when T _W < T _R , the data rate T W of the input information signal is different from the data rate T R of the reference signal.
is thinned out, and when T _W < _TR , the same unit data may be read out repeatedly. That is, overtaking occurs on the writing side or on the reading side.

A color video signal will be explained as an example of the information signal. In the case of a color video signal, the maximum allowable frequency deviation between the standard carrier frequency _sc of the key station and the carrier frequency of the local station is 10Hz, so let's assume that we are dealing with a color video signal in which the frequency deviation between these stations is 10Hz. When the clock frequency is selected to be 3 _sc , one frame of overtaking occurs on either the write side or the read side approximately every 3 hours and 20 minutes.

When this overtaking occurs, if data from the line after the occurrence to the next overtaking is read out using the previous clock sequence, the following problem will occur. That is, since the spatial arrangement of picture elements constituting opposing horizontal scanning lines of adjacent frames is different, if the clock frequency is selected to be 3 _sc , not only the luminance component but also the color component will not be reproduced correctly. When the clock frequency is 4 _sc , only the color components are not correctly demodulated.

Therefore, the present invention makes it possible to easily detect the occurrence of overtaking.

In this invention, when the memory 6 shown in FIG. 2 is used as a main memory device, a sub memory device is provided for this main memory device, and a display indicating the write status in the main memory device is provided in synchronization with the write operation to the main memory device. The signal is stored in a secondary memory device. Similarly, display signals indicating the read status in the main memory device are stored in the secondary memory device in synchronization with the read operation, and these display signals are used to detect overtaking of the write or read operation to the main memory device. It is something. An example of the present invention will be described in detail with reference to the drawings.

In the embodiment shown in FIG. 7, the display signal is composed of a binary signal, and in this example, the display signal indicating the write state is "1" and the display signal indicating the read state is "0".
stipulated in Display signals are stored in units of a predetermined data group, in this example, data for one horizontal line. Therefore, a flag string of "1" or "0" is stored in the sub-memory device for each line.

Then, i of a predetermined block of the main memory device 6 is
After writing data to the line, i of the flag column
-Write display signal "1" to line 1. When reading the j-line data from the main memory device 6,
Before starting this reading, a display signal "0" is written in the flag column of the j-1 line. If the writing time and display signal to the flag column are selected in this way,
The occurrence of overtaking can be detected simply by determining the contents of the display signal when writing and reading data to and from the main memory device 6.

That is, when writing data to the main memory device 6, if the display signal read from the flag column of the i-1 line is "0" before writing "1" to the flag column of the i-1 line, indicates that the data on the i line to be rewritten has been read out at least once. If the display signal is "1", it indicates that the i-line has not been read out even once. This overtaking occurs when T _W < _TR .

Before reading the data on the j line, detect the content of the display signal written on the j-1 line of the flag column, and if this is "0", read the previously successive data again. Therefore, when it is "1", the data is read for the first time. This overtaking occurs when T _W > T _R .

An example of a configuration for achieving the above operation is shown in FIG. As shown in the figure, the sub-memory device 50 is composed of a flag array 50A and a decoder 50B having a capacity corresponding to at least 525 horizontal lines. For example, a 1K.times.1 bit static RAM is used for the flag column 50A, and a key station cycle pulse RCC (FIG. 8A) is used for the display signal.

51W is the line address signal LAW on the writing side
This counter is used to form a horizontal synchronizing pulse H _DW that is synchronized and separated from the input video signal. Further, 51R is a counter for forming the line address signal LAR on the read side, and is driven by the pulse _HDR obtained by the horizontal synchronizing pulse forming circuit 52. Address signals LAW, LAR are supplied to multiplexer 53, and in connection with write and read operations for main memory device 6, address signals LAW, LAR are selected and supplied to decoder 50B. Selection of address signals LAW and LAR is performed by cycle pulse RCC, and when it is "1", address signal LAW is selected.

The chip select terminal 54a of the decoder 50B has an inverted enable signal for the flag column 50A.
FLGEN (E in the same figure) is supplied, and the writing side has one flag per line for the flag row 50A.
This is the NOR output of the access signal WT (C in the figure) for accessing the data once and the access signal RD (D in the same figure) on the read side.

In FIG. 8, FCC is a pulse having twice the frequency of cycle pulse RCC, which forms the write enable signal WE (FIG. 8H) for decoder 50B. When the enable signal WE is obtained (periods W ₁ and W ₀ ), a display signal is written in the flag column 50A. 55
A and 55B are mono multivibrators, and their outputs Q ₁ and Q ₂ are shown in FIGS. 8F and 8G.

Reference numeral 60 denotes an overtaking detection circuit, and a display signal read from the flag column 50A is supplied to a pair of AND circuits 61W and 61R constituting a comparison circuit 61. The above-mentioned access signals WT and RD are used as comparison signals.
is used. The outputs of the AND circuits 61W and 61R are supplied to a D-type flip-flop circuit 63 via an OR circuit 62.

Note that 65 is a delay circuit for the reference clock signal RC used when overtaking occurs, and the delay time is selected to be an odd multiple of 1/2 of one period of the color subcarrier. In this example, it is set to 140 nsec, which is 1/2 period. The multiplexer 66 is controlled by the detection output of the overtaking detection circuit 60, and its output is controlled by the detection output of the overtaking detection circuit 60.
etc. will be supplied.

Next, the operation of the device configured as described above will be explained. By using pulses RCC, FCC, WT, RD and enable signal WE, the first half of one memory cycle can be used as a cycle for writing data to the main memory device 6, and the second half can be used as a cycle for reading data. If the AND output of the AND circuit 61W is "1", overtaking has occurred, so the Q output of the circuit 63 at this time switches the reference clock signal to the delay circuit 65 side. By this switching, the phase of the color subcarrier signal is forcibly shifted by 1/2 cycle (140 nsec). Then, a display signal "1" is written in period _W1 .

The operation on the reading side will be omitted.

As described above, according to the present invention, the occurrence of overtaking can be detected simply by providing the sub-memory device 50 and determining its output, thereby simplifying the device. If the reference clock signal is delayed by the detection output when overtaking occurs, the color components can be reproduced correctly and the deterioration in color reproducibility can be compensated for.

FIG. 9 shows another embodiment of the invention. This example is a case where a discrimination number LINID indicating whether the display signal is an odd-numbered horizontal line or an even-numbered horizontal line is used. That is, the discrimination signal to be written in the flag example 50A is the one formed based on the input information signal. A line discrimination signal (odd lines are set to "1") is stored. Then, when reading each line, the above-mentioned discrimination signal and a similar line discrimination signal formed at the key station are used.
LINIDR and if the line types match, no overtaking has occurred, so A-D conversion is performed using a normal clock sequence. If the line types do not match, by changing the clock sequence by 140 nsec, the color components can be corrected and demodulated in the same way as described above.

FIG. 9 shows an example of such an overtaking detection circuit. Although the detailed explanation is omitted, 60 is a discrimination signal.
This is a comparison circuit consisting of an exclusive OR circuit for comparing LINIDW and LINIDR, and output is obtained only when the line types are different. The inversion control circuit 72, which includes a multiplexer 72A and an inverter 72B, provided on the transmission line of the discrimination signal LINIDR is for inverting the discrimination signal LINIDR when overtaking occurs until the next overtaking occurs. In multiplexer 72A
The output of the JK type flip-flop circuit 73 is supplied as a control signal.

D-type flip-flop circuits 75A-75C are for timing adjustment. WENBL and RENBL indicate write-side and read-side enable signals in the main memory device 6.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are system diagrams for explaining the present invention, and FIG. 3 is a system diagram showing a specific example of the main parts thereof.
Figures 4 to 6 are diagrams for explaining the operation, Figure 7
9 and 9 are system diagrams showing an example of the present invention, and FIG. 8 is an explanatory diagram of the operation of FIG. 7. 5A to 5D are input buffer circuits, 6 is a main memory device, 6A to 6D are memory blocks, 11
A and 11B are output buffer circuits, 50 is an auxiliary memory device, and 60 is an overtaking detection circuit.

Claims (1)

[Scope of Claims] 1. A clock signal related to a digital information signal is extracted, the digital information signal is sequentially written to a predetermined address of a main memory device based on the clock signal, and the digital information is written from the main memory device using a reference clock signal. The signals are sequentially read out, the phase of the digital information signal is converted, and a display signal indicating the write state in the main memory device is sent to the sub memory device in synchronization with the write operation to the main memory device. A display signal indicating a read state in the main memory device is stored in a sub memory device in synchronization with a read operation to the main memory device, and a display signal indicating a read state in the main memory device is stored in the sub memory device. A signal phase conversion device configured to detect an overtaking state of a write or read operation. 2 A predetermined number of digital information signals are made into a data group, one display signal is assigned to this data group, and a display signal indicating the write state is sub-displayed in synchronization with the writing operation of the data group to the main memory device. The signal according to claim 1, wherein the signal is stored in a memory device, and a display signal indicating a read state is stored in the secondary memory device in synchronization with the reading operation of the data group from the main memory device. Phase conversion device. 3. The digital information signal is a digital video signal, and the main memory device has a capacity to store at least one frame of information of the video signal, and one line of the digital video signal is regarded as the data group. The signal phase conversion device according to claim 2, wherein a display signal is assigned. 4 A binary signal indicating odd lines and even lines of the video signal is used as the display signal, and these two
4. The signal phase conversion device according to claim 3, wherein the value signal is written to or read from the sub-memory device in response to writing or reading of the digital video signal line by line. 5. Claim No. 5, wherein a circuit is provided for comparing the write display signal and the read display signal, and when the respective binary signals do not match, the read digital video signal is delayed by a predetermined time. 4. The signal phase conversion device according to item 4. 6. Claim 5, wherein the means for delaying the digital video signal by a predetermined time delays the reference clock signal by a time corresponding to an odd multiple of 1/2 of the period of the color subcarrier signal of the video signal. The signal phase conversion device described.