JPH06302127A - Equipment and method for switching signal - Google Patents

Abstract

PURPOSE: To reduce the omission of effective data by speedily switching a channel to any channel with no error corresponding to a timing signal when there is an error in any one of respective channel data streams outputted from plural heads. CONSTITUTION: A selector 5 selects a channel A out of the data streams of channels A and B and defines it as one output signal 6 and assuming that a GEF signal A is changed to low showing the state of error existent in the channel A and a GEF signal B is still high during the output, the selector 5 is controlled by a preprocessor 8 and NAND gates 9, 10 and 11 of control means so that the data stream of the channel B selected by the 1st pulse of timing pulse signal of the channel B can be outputted as the new output signal 6. Therefore, the amount of invalid data in the outputted data stream can be suppressed to a minimum.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a signal switching device and method.

[0002]

2. Description of the Related Art Switching many signals and selecting only one signal as an output signal is required for many circuits. For example, a digital video tape recorder (DVT)
R) has a main channel and an auxiliary "leading head"
There are two data sources for channels. The data streams output by the two playheads must be stored in one memory, for example in the time base collector, after processing. When there is more than one data channel, it is necessary to perform the channel switching by a control method that reduces the error caused by the switching during the next processing. It is also important that the switch does not excessively lose valid data.

Conventionally, an external data flag is used to indicate that one of two data channels is valid at a certain time, and this flag makes one data valid and the other invalid. It is known to switch between two channels so that

A device for switching between two asynchronous clock signals is also described in GB-A-2181025. The purpose of this device is to prevent omissions in the output clock signal, ie to ensure that the output signal always holds a complete clock cycle. This device provides two clock signals, clock X and clock Y.
Two control signals, enable signal X and enable signal Y
It is switched under the control of. If the corresponding clock signal is the output of the device, enable signals X and Y
Each goes low and the other goes high. The enable signals X and Y are input to the D flip-flops by the corresponding clock signals. The output signals of these flip-flops are used to output one control signal X / Y (bar). That is, it indicates that the output signal of the device is switched from one of the clock signals to the other by the change of the state of the control signal. This control signal X / Y
(Bar) is input by inversion of the respective clock signals via the two shift registers. The next time output signals of these shift registers erase the currently selected clock signal to select the reference level (0 volts) as the output signal of the device, and the output signal of the device instead of the reference level. As a trigger for selecting another clock signal. Since the erasure of the currently selected clock signal is triggered by inverting the clock signal, this clock signal is not shortened during the erase. Similarly, the selection of the new clock signal is triggered by inverting the clock signal, avoiding the mid-cycle selection of the new clock signal.

The point of the device described above is that after one complete clock cycle, one clock signal is erased to select the reference level and then a new signal starting with one complete clock pulse, It is to avoid a dropout in the output signal.

[0006]

The former method using the flag is poor in reliability and cannot be sufficiently controlled so that an error will not occur in the next processing as a result of switching.

Also, the latter device requires that at least two clock pulses of the new clock signal are present after the previous signal has been erased and before the new signal is selected as the device output. Is. While this prevents loss of signal, the loss of clock pulses in the switched signal is not desirable and may result in an unsuitable device depending on the particular application. In particular, when the device is adapted to switch the data stream from the playback head of the DVTR with the sync signal applied as the clock input signal of the device and output from the playback head, the output signal is of the new channel. At least two blocks (eg 256 bytes) of the valid data of the new data stream each time the device is switched to a new channel because it is maintained at the reference level for at least two synchronization cycles.
Is lost.

[0008]

According to the present invention, for example, as shown in FIG. 2, each of a plurality of timing pulse signals is a display signal indicating the first or second state according to the corresponding timing pulse signal. And a device for switching a plurality of timing pulse signals, the device having the following configuration. A selector 5 for inputting a plurality of timing pulse signals and selecting one timing pulse signal as one output signal, and a timing pulse signal and a display signal are input, and a display signal corresponding to the currently selected timing pulse signal is displayed. , The second of this selected timing pulse signal
And the first state is indicated by a corresponding display signal with respect to one or more other timing pulse signals, the selector 5 is controlled to select one new timing pulse signal as an output signal. Control means 8, 9, 1
0, 11 is selected by the first pulse signal of the other timing pulse signals having the first state, and the timing signal having the first pulse is selected as the new output signal. It was to so.

Further, each of the plurality of data streams is
A device for switching a plurality of data streams when having a timing pulse signal synchronized with this and a corresponding display signal indicating the first or second state according to the corresponding data stream, and having the following configuration. . A selector 5 which inputs a plurality of data streams and selects one data stream as one output signal, a timing pulse signal and a display signal are input, and the display signal corresponding to the currently selected data stream is selected by this selection. A second state of the data stream that has been recorded, the first state being indicated by a corresponding display signal for one or more other data streams, controlling the selector 5 to create a new data stream. The selection is made by means of a first pulse of the timing pulse signal, which has control means 8, 9, 10, 11 for selecting it as an output signal, the first state of which is indicated for the corresponding data stream. The data stream corresponding to the timing pulse signal having the pulse of is selected as the new output signal.

Further, the present invention is a method of switching a plurality of timing pulse signals when each of the plurality of timing pulse signals has a display signal indicating the first or second state according to the corresponding timing pulse signal. It consists of the following steps. By supplying a plurality of timing pulse signals to the selector 5, one timing pulse signal
And a display signal corresponding to the currently selected timing signal indicates a second state of the selected timing pulse signal, the first state being one or more other timing pulses. When the signal is indicated by the corresponding display signal, the selector is controlled to 1
Selecting one new timing pulse signal as the output signal, the timing pulse signal having the first pulse is selected by the first pulse of the other timing pulse signals having the first state. , So that it is selected as a new output signal.

Further, each of the plurality of data streams is
A method of switching a plurality of data streams, comprising a timing pulse signal synchronized with this and a corresponding display signal indicating the first or second state according to the corresponding data stream, comprising the following steps: . The step of supplying a plurality of data streams to the selector 5 to select one data stream as one output signal, and the display signal corresponding to the currently selected data stream are the second state of the selected data stream. And the first state is indicated by corresponding display signals to one or more other data streams, the selector is controlled to select one new data stream as an output signal. , A first state is indicated for the corresponding one or more data streams, the selection being made by a first pulse of the timing pulse signal,
The data stream corresponding to the timing pulse signal having the first pulse is selected as the new output signal.

[0012]

It is assumed that each display signal has an error signal, that is, a first state indicating that the target data stream has no error and a second state indicating that the target data stream has an error. In this case, the condition under which the switch occurs is that the currently selected data stream has an error and at least one of the other data streams is error free. When the condition for switching to a new output signal occurs, the switching is made by the first timing pulse signal of the error-free data stream which follows. As a result, switching is performed by the predetermined control means during the period in which the loss of valid (error-free) data from the new data that is the switched output signal is minimized.

If the device switches between only two data streams, the control means controls the selector to cause another data stream to be selected for output.
At this time, the display signal corresponding to the currently selected data stream indicates the second state, and the first state indicates to the other data stream. At this point, the timing corresponding to the other data stream The selection is made by the first pulse of the pulse signal.

The selector is configured to receive the timing pulse signal and select the timing pulse signal corresponding to the selected data stream as the next output signal. Similarly, the selector may be configured to receive the display signal and select the display signal corresponding to the selected data stream as the next output signal.

If each display signal is an error signal, this error signal can be derived in many ways. For example, when the data stream is output from the reproducing head of the DVTR, the sync pulse derived from the data stream is added to the device as a timing pulse signal, so that the state of each error signal is such that the corresponding sync pulse has a predetermined time. It depends on whether or not the intervals match exactly. The sync pulses derived from the data stream are thus time-spaced so that if there is an error in the data stream (during tape cross-out or cross-tracking as a result of shuttle playback), error recovery will occur. , The first sync pulse will indicate the position of the error-free first data block.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the signal switching apparatus and method of the present invention will be described in detail below with reference to FIGS. In FIG. 1, the data stream consists of a series of word blocks, one of which is shown. The beginning portion of this word block has, for example, 2 words, and synchronous (SYNC) data is arranged therein. The next word block contains a group or field identifier (ID)
Are placed. Most of the word block is occupied by video data as shown in the figure, and an error correction code (ECC) is arranged in the last block, so that the error can be corrected in the reproduced data in the reproducing processor of the DVTR. The reproduction processor processes the reproduction data, converts it into a parallel word, and outputs the timing pulse signal 1. The timing pulse signal 1 is a series of start pulses (S
P) 2, and this start pulse 2 indicates the start of synchronous data, that is, the start of each word block in the parallel-converted data stream.

FIG. 2 shows a switching circuit according to an embodiment of the present invention, which switches between two data streams in a DVTR playback processor. D
The two converted data streams output from each playback head of the VTR are supplied as inputs to a switching circuit, indicated by reference numeral 3. These two data streams are designated channel A and channel B in the figure and are input via parallel buses 4a and 4b, respectively. The data buses 4a and 4b are connected to the selector 5, and its input terminal S
One of the data streams on the buses 4a and 4b is selected on the basis of the control of the signal applied to the output terminal 6 and is output to the output terminal 6 of the selector 5. First-in first-out (FI) which gives a delay time to each bus 4a and 4b
FO) elements 7a and 7b are connected.

The switching circuit 3 has control means consisting of two preprocessors (preprocessors) 8a and 8b connected to the data buses 4a and 4b, respectively. In this example, the preprocessors 8a and 8b are PAL elements,
Their operation is shown in detail in FIG. Further, the control means are NAND gate arrays, 9a, 9b, 10a,
It has 10b, 11a and 11b. As is clear from the figure, the NAND gates 11a and 11b constitute an SR flip-flop, and the output signal Q of the NAND gates 11a and 11b is the selector 5
Is supplied to the input terminal S of.

FIG. 3 shows the preprocessors 8a and 8 of FIG.
Signal names are added to the input and output terminals of b. Each preprocessor 8a and 8b has a corresponding channel A
And a start pulse input signal (hereinafter referred to as SP signal) for inputting a timing signal or start pulse 1 (FIG. 1) synchronized with the channel B data stream. The pre-preprocessor 8a or 8b inputs an error flag input signal (hereinafter referred to as an EF signal) for inputting an error signal indicating an error state or an error-free state to the corresponding channel A or channel B data stream. .). In this example, the state of each error signal depends on whether or not the pulse 2 of the corresponding SP signal has a predetermined time interval, but the EF signal can be derived by various methods. . The EF signal can be derived by a known method in the initial stage of the reproducing processor. Each EF signal has a logical value of 1 to indicate that the corresponding data stream is error-free, and has a logical value of 0 to indicate that there is an error.

The clock input signal CK of each preprocessor 8a and 8b captures the SP and EF signals into the respective preprocessor at the word rate of the corresponding channel A or channel B data stream. These SP and EF signals are processed in the preprocessor and four signals are output as shown. The first of these four signals is the gated error flag output signal (hereinafter referred to as the GEF signal), and the EF signal is the SP.
It is extended beyond the period of adjacent pulses of the signal. The second output is a gate-controlled start pulse (hereinafter referred to as a GSP signal), and the input start pulse (SP signal) is cut off for a period in which the GEF signal indicates an error state. It is a thing. The third and fourth outputs are a delayed start pulse (hereinafter referred to as a DSP signal) and a delayed error flag output signal (hereinafter referred to as DEF).
Called a signal. ), The SP and EF signals are delayed by a time corresponding to the processing time of the next control circuit. The delay time generated here corresponds to the delay time generated by the FIFO elements 7a and 7b in the two data streams, and the delay time is usually several clock cycles long.

In FIG. 2, preprocessors 8a and 8a
The input and output signals to b are shown as A or B, corresponding to channel A or channel B, and the clock input signal CK is omitted. As is clear from the figure, the DEF and DSP signals of each preprocessor 8a and 8b are
It is directly supplied to the selector 5. The GEF signal of each preprocessor 8a and 8b is supplied to the input terminals of the NAND gates 9a and 9b, and the channel detection signal is supplied to the other input terminal of these gates. This channel detection signal is used for the switching circuit 3 when there is no clock signal in either of the preprocessors due to disconnection, for example.
Is given to prevent the apparent closed state by suppressing. These inputs are maintained at a logic one when the device is in operation and at a logic zero otherwise.

The output signal of the NAND gate 9a is supplied to the NAND gate 1 together with the GSP output signal of the preprocessor 8b.
It is gated by 0b. The output signal of the NAND gate 10b becomes the reset input signal R of the SR flip-flop composed of the NAND gates 11a and 11b. Similarly, the output signal of the NAND gate 9b is
It is gate-controlled by the NAND gate 10a together with the GSP signal of the preprocessor 8a, and the output signal of the NAND gate 10a is the SR flip-flop (11a, 11a).
It becomes the set input signal S of b). The output signal Q of the SR flip-flop (11a, 11b) is output to the input terminal S of the selector 5. The signal applied to this input terminal S becomes an A / B select signal that triggers the switching of the channel A and channel B data streams. At the same time as selecting the new data stream as the output signal, the selector 5 selects the DEF and DSP signals according to the selected channel and outputs the EF and SP signals, respectively.

The operation of the apparatus will be described with reference to FIG. In Figure 4, first from Channel A to Channel B,
Next, it is a timing diagram showing SP, GEF, and GSP signals corresponding to each data channel during a period of switching from channel B to channel A. The A / B select signal applied to the input terminal S of the selector 5 is also shown together with the EF signal. In the figure, the lowermost part shows that the data on the output terminal 6 of the selector 5 is the data stream of the channel A or the channel B.

In the initial stage of FIG. 4, the GEF signal A is high and the GEF signal B is low, indicating that channel A is error-free and channel B is error-free. Therefore, at this point, the data of channel A is output to the output terminal 6 of the selector 5. The A / B select signal, which is the output signal Q of the flip-flops (11a, 11b), becomes low, and the flip-flops (11a, 11b)
NAND gate 10b which becomes the reset input signal R of b)
The output signal of becomes high. Since the output signal of the NAND gate 10a is an inverted signal of the GSP signal, the switching circuit 3 is stable when the A / B select signal is low.

Immediately after the start of the timing diagram of FIG.
The F signal B goes high, indicating that channel B is error free, but channel A is still maintained error free. As a result, the NAND gate 9
Since the output signal of b becomes low, the flip-flop (1
The set input signal S of 1a, 11b) becomes a constant high level signal, and its reset input signal R is still maintained in the high state, so that the output signal Q, that is, the A / B select signal is maintained low and switched. Is not done.

Immediately after this, the GEF signal A shifts to low indicating the error state of the channel A, and the start pulse corresponding to the channel A is cut off by the preprocessor 8a like the GSP signal A. At this point,
The GEF signal B is still high, indicating that channel B is error free. When the output signal of the NAND gate 9a becomes high, the output signal of the NAND gate 10b becomes low at the next pulse of the GSP signal B. Since the set input signal S of the flip-flops (11a, 11b) is still in the high state, the first low pulse of the reset input signal R causes the flip-flop (11a, 11b,
The output signal Q which is the A / B select signal of 11b) becomes high. Due to this change on the input terminal S of the selector 5,
The channel B data is switched and output to the output terminal 6, and the DSP signal B and the DEF signal B are switched and output to the SP and EF output terminals. When the reset input signal R of the flip-flops (11a, 11b) becomes high following each low pulse appearing at the output of the NAND gate 10b, the state of the output signal Q, which is the A / B select signal, is maintained and the device operates on the channel B. Stable in the output data stream of.

Next, the GEF signal B becomes low, which indicates that the channel B has an error, and the start pulse of the SP signal B is cut off like the GSP signal B. At this point, GEF signal A is low, so channel A contains an error. Flip-flop (11a,
Although the reset input signal R of 11b) is maintained at a constant high level, the set input signal S is still at a high level, so that the A / B select signal which is the output signal Q of the flip-flops (11a, 11b) is not There is no change and therefore switching of the selector 5 does not occur. After this, the GEF signal A goes high indicating that channel A is error free. At this time, the output signal of the NAND gate 10a is GS
It is an inverted signal of the P signal A. Since the flip-flop (11a, 11b) is reset by the first low pulse applied to the output signal of the NAND gate 10a, that is, the set input signal S of the flip-flop (11a, 11b), the output signal Q which is the A / B select signal. Becomes low. The A / B select signal applied to the input terminal S of the selector 5 switches the selector 5 to cause the output terminal 6 to output the data of the channel A, and the SP and EF output terminals D
The SP signal A and the DEF signal A are output. At this time, the switching circuit 3 becomes stable until an error occurs in the channel A and no error occurs in the channel B, and as a result, the above-described processing becomes stable until it is restarted.

Therefore, it will be understood that when there is an error in both channels, or when there is no error in both channels, there is no change in the output state. When a switching condition occurs, that is, when an error occurs in the currently selected channel and there is no error in other channels, the switching operation is promptly performed by the pulse next to the gate control start pulse of the error-free channel. Done. Therefore, the switching can be performed by an appropriate control means, and the amount of invalid data in the output signal can be maintained to be minimum. This is illustrated in FIG. 4 by the low region of the FE output signal and the shaded portion of the data output.

In FIG. 5, the switching circuit 3 is a DVT.
It is shown in a block diagram showing a part of the R reproducing processor. Serial data streams output from the two reproducing heads of the channel A and the channel B of the DVTR are supplied to the synchronization / identification and ECC processors 12a and 12b, respectively, the data streams are converted into parallel data, and the synchronization data is decoded. Then, the start pulse signal and the error flag signal are derived. These signals are then output to the switching circuit 3 and processed in the manner described above. The output signal of the switching circuit 3 is output to the preprocessor 13 for the time base collector, and the data switched by this preprocessor 13 is supplied as the address information of the write data to the time base collector TBC (not shown), and is there. It is stored temporarily.

Needless to say, various configurations are possible without being limited to the above-mentioned embodiment. In particular, it is feasible for a device with more than one data stream, in which case the currently selected data has an error and at least one of the other data streams is error free,
Switching can be performed. The first pulse of the timing signal corresponding to the error-free channel occurring after the occurrence of the switching condition causes the switching and the output signal is switched to the error-free channel.

[0031]

As described above, according to the present invention,
If there is an error in one of the data streams of each channel output from multiple heads, the timing signal of the error-free channel promptly switches to that error-free channel, thereby invalidating the output data stream. There is an advantage that the amount of data can be suppressed to the minimum.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of a DVTR data stream format and its timing signal.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a detailed view of a part of the embodiment.

FIG. 4 is a timing chart showing the operation of the embodiment.

FIG. 5 is a block diagram showing a part of a DVTR playback processor using the embodiment.

[Explanation of symbols]

 1 timing pulse signal 2 start pulse (first pulse) 3 switching circuit 5 selector 8 preprocessor (control means) 9, 10, 11 NAND gate (control means)

Claims (12)

[Claims] 1. Each of the plurality of timing pulse signals comprises:
A device for switching the plurality of timing pulse signals when having a display signal indicating the first or second state according to the corresponding timing pulse signal, wherein the plurality of timing pulse signals are input to obtain one timing pulse signal. A selector for selecting a signal as one output signal, the timing pulse signal and the display signal are input,
A display signal corresponding to the currently selected timing pulse signal indicates the second state of the selected timing pulse signal, and the first state corresponds to one or more other timing pulse signals. Control signal for controlling the selector to select one new timing pulse signal as the output signal, the control signal of the other timing pulse signal indicating the first state. A signal switching device that is selected by a first pulse, and the timing pulse signal having the first pulse is selected as a new output signal. 2. The plurality of data streams, wherein each of the plurality of data streams has a timing pulse signal synchronized therewith and a corresponding display signal indicating a first or second state according to the corresponding data stream. A device for switching data streams, wherein a selector for inputting the plurality of data streams and selecting one data stream as one output signal, the timing pulse signal and the display signal are input,
The display signal corresponding to the currently selected data stream is
Indicating the second state of the selected data stream, the first state being indicated by a corresponding display signal to one or more other data streams, controlling the selector to control the new state. Means for selecting a different data stream as the output signal, the selection being made by the first pulse of the timing pulse signal, the first state being indicated for the corresponding data stream, A signal switching device, wherein a data stream corresponding to the timing pulse signal having the pulse of is selected as a new output signal. 3. The control means controls the selector so that the display signal corresponding to the currently selected data stream indicates the second state of the selected data stream, and the first state is the other data stream. , The other data stream is selected, but at this time, the two data streams are switched so that the selection is made by the first pulse of the timing pulse signal corresponding to the other data stream. An apparatus according to claim 2. 4. The apparatus according to claim 2, wherein the selector is configured to receive the timing pulse signal and select a timing pulse signal corresponding to the selected data stream as a next output signal. . 5. The selector according to claim 2, wherein the selector is configured to receive the display signal and select a display signal corresponding to the selected data stream as a next output signal. The described device. 6. Each of the plurality of timing pulse signals comprises:
A method of switching the plurality of timing pulse signals when a display signal indicating the first state or the second state is provided according to the corresponding timing pulse signal, wherein the plurality of timing pulse signals are supplied to the selector to obtain one The step of selecting the timing pulse signal as one output signal and the display signal corresponding to the currently selected timing pulse signal indicate the second state of the selected timing pulse signal, and the first state is A step of controlling the selector to select one new timing pulse signal as the output signal when indicated by a corresponding display signal with respect to one or more other timing pulse signals; Is selected by the first pulse of the other timing pulse signal indicating the state of Signal switching method as described above timing pulse signal is selected as a new output signal with. 7. The plurality of data streams, wherein each of the plurality of data streams has a timing pulse signal synchronized therewith and a corresponding display signal indicating a first or second state according to the corresponding data stream. A method of switching a data stream, comprising the steps of supplying the data stream to a selector to select one data stream as one output signal, and a display signal corresponding to the currently selected data stream,
Shows a second state of this selected data stream,
The first state is for one or more other data streams,
Controlling the selector to select one new data stream as the output signal when indicated by a corresponding display signal, the first state being indicated for the corresponding data stream. A signal switching method, wherein selection is made by a first pulse of the timing pulse signal, and a data stream corresponding to the timing pulse signal having the first pulse is selected as a new output signal. 8. The selector is such that a display signal corresponding to the currently selected data stream indicates a second state of this selected stream of data and a first state is indicated for other data streams. If so, the other data stream is controlled to be selected as the output signal, but at this time, the selection is made by the first pulse of the timing pulse signal corresponding to the other data stream, The method of claim 7, wherein the two data streams are switched. 9. The method according to claim 7, further comprising: supplying the timing pulse signal to the selector; and controlling the selector to select the timing pulse signal corresponding to the selected data stream as the next output signal. Or the method described in 8. 10. The method according to claim 7, further comprising the steps of supplying the display signal to a selector and controlling the selector to select the display signal corresponding to the selected data stream as the next output signal. The method described in any one of. 11. Each of the display signals has a first state corresponding to an error-free state of a corresponding data stream and a second state corresponding to an error-free state of a corresponding data stream. The method according to claim 7, wherein the method is an error signal. 12. The method according to claim 11, wherein the state of each error signal depends on the presence or absence of the pulses of the corresponding timing pulse signal for a predetermined time interval.