GB2267415A

GB2267415A - Signal switching

Info

Publication number: GB2267415A
Application number: GB9210670A
Authority: GB
Inventors: James Hedley Wilkinson
Original assignee: Sony Broadcast and Communications Ltd; Sony United Kingdom Ltd
Current assignee: Sony Broadcast and Communications Ltd; Sony Europe BV United Kingdom Branch
Priority date: 1992-05-19
Filing date: 1992-05-19
Publication date: 1993-12-01
Anticipated expiration: 2012-05-19
Also published as: JPH06302127A; GB9210670D0; GB2267415B

Abstract

Apparatus 3 for switching between a plurality of data streams A and B, each of which has a pulsed timing signal (1) Fig. 1, (not shown) synchronised therewith and an associated indicator signal for indicating a first (error-free) or second (error) condition associated with the corresponding data stream, comprises a selector 5 for receiving the data streams and selecting one data stream as an output of the selector 5, and control means 8, 9, 10, 11 for receiving the timing signals (1) and the indicator signals and for controlling the selector 5 to select a new data stream as the output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for one or more of the other data streams by the associated indicator signal or signals. The selection is then effected on the first pulse (2) of the or any of the timing signals (1) for which the first condition is indicated for the associated data stream or streams, and the data stream associated with the timing signal containing the said first pulse (2) is selected as the new output. The data streams are from the reproduction heads of a digital video tape recorder. <IMAGE>

Description

SIGNAL SWITCHING This invention relates to switching of signals.

Switching between two or more signals so as to pass only one of the signals to a single output is required in many circuits. For example, in a digital video tape recorder (DVTR) there may be two possible sources of data, for instance a main channel and a supplementary "advance head" channel. The data streams derived by the two reproducing heads must be processed and stored in a single memory, for example in a timebase corrector. Where there is more than one data channel, it is desirable to ensure that switching between the channels is effected in a controlled manner to reduce the possibility of the switching introducing errors in the subsequent processing stages, for example due to misinterpretation of the switched data by the subsequent circuitry. It is also important that the switching does not cause an undue loss of valid data.

It is known to use an external data flag to indicate which of two data channels is active at any one time and to use this flag to "crash switch" between the two channels as one becomes active and the other inactive. However, the flag may be unreliable, and this method is not sufficiently controlled to ensure that errors do not arise in the subsequent processing stages as a result of the switching.

A system for switching between two asynchronous clock signals is disclosed in UK patent number 2181025. The aim of this system is avoid "gliches" in the output clock signal, ie to ensure that the output signal always contains complete clock cycles. The system described is for switching between two clock signals, Clock X and Clock Y, under the control of two control signals, Enable X and Enable Y. Each of the signals Enable X and Enable Y goes low, the other then being high, when the corresponding clock signal is to be the output of the apparatus.

The Enable X and Enable Y signals are clocked into respective D-type flip-flops by their associated clock signals. The outputs of these flip-flops are used to derive a single control signal X/Y a change in the state of which signifies that the output of the apparatus should be switched from one to the other of the clock signals. The signal X/Y is clocked through two shift registers by the inverses of the respective clock signals. The outputs of successive stages of these shift registers are used to trigger, in turn, the deselection of the currently selected clock signal in favour of a reference level (0 volts) as the output of the apparatus, and the selection of the other clock signal as the output of the apparatus in place of the reference level. Deselection of the currently selected clock signal is triggered by the inverse of that clock signal, so that the clock signal is not cut short on deselection. Similarly, selection of the new clock signal is triggered by the inverse of that clock signal to avoid selection of the new signal mid-cycle.

The essence of the described system is the deselection of one clock signal after a complete clock cycle in favour of a reference level, followed by the selection of the new signal starting with a complete clock pulse, thus avoiding gliches in the output signal.

However, this system requires there to be at least two clock pulses of the new clock signal following deselection of the previous signal and prior to selection of the new signal as the output of the apparatus.

While gliches are thereby avoided, this "loss" of clock pulses in the switched signal is undesirable and renders the system unsuitable for certain applications. In particular, if the system were to be applied in switching between data streams from the reproducing heads of a DVTR, with the sync signals derived from the reproduced data applied as the clock inputs of the apparatus, then at least two entire blocks (eg 256 bytes) of valid data on the new stream would be lost each time the system switched to a new channel since the output would be held at the reference level for the duration of at least two sync cycles of the new channel.

According to the present invention there is provided apparatus for switching between a plurality of pulsed timing signals each of which has an indicator signal associated therewith for indicating a first or second condition associated with the corresponding timing signal, the apparatus comprising: a selector for receiving the timing signals and selecting one timing signal as an output signal; and control means for receiving the timing signals and the indicator signals and for controlling the selector to select a new timing signal as the said output signal when the indicator signal associated with the currently selected timing signal indicates the second condition for that timing signal and the first condition is indicated for one or more of the other timing signals by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the said other timing signals for which the first condition is indicated, the timing signal containing the said first pulse being selected as the new output signal.

According to the present invention there is also provided apparatus for switching between a plurality of data streams each of which has a pulsed timing signal synchronised therewith and an associated indicator signal for indicating a first or second condition associated with the corresponding data stream, the apparatus comprising: a selector for receiving the data streams and selecting one data stream as an output of the selector; and control means for receiving the timing signals and the indicator signals and for controlling the selector to select a new data stream as the said output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for one or more of the other data streams by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the timing signals for which the first condition is indicated for the associated data stream or streams, the data stream associated with the timing signal containing the said first pulse being selected as the new output.

Thus, consider, for example, the case where each said indicator signal is an error signal, the said first condition corresponding to an error-free condition of the associated data stream, and the said second condition corresponding to an error condition of the associated data stream. The condition for switching to occur is then that the currently selected data stream contains errors and at least one of the other data streams is error-free. When the condition for switching to a new output signal arises, switching is effected on the first timing signal pulse of an error-free data stream which occurs thereafter.

Switching is thereby effected in a controlled manner while ensuring that there is minimum loss of valid (error-free) data from the new data stream in the switched output signal.

Where the apparatus is for switching between only two data streams, the control means controls the selector to select the other data stream as the output when the indicator signal associated with the currently selected data stream indicates the second condition and the first condition is indicated for the other data stream, the selection then being effected on the first pulse of the timing signal corresponding to the other data stream.

The selector may be arranged to receive the said timing signals and to select the timing signal corresponding to the selected data stream as a further output of the selector. Similarly, the selector may be ranged to receive the said indicator signals and to select the indicator signal corresponding to the selected data stream as an additional output of the selector.

Where each indicator signal is an error signal, the error signal may be derived in a number of ways. For example, where the said data stream is generated by the reproducing heads of a DVTR, the sync pulses derived from the data streams being applied as the timing signals to the apparatus, the state of each error signal may depend upon whether the corresponding sync pulses are at exactly the prescribed temporal spacing. The sync pulses derived from the data streams are so timed that if the data stream is subject to errors (such as may be caused by tape drop-out or during cross-tracking as a result of shuttle play) then, on recovery from the error, the first sync pulse will indicate the position of the first error-free data block.

The invention also provides a method of switching between a plurality of pulsed timing signals each of which has an indicator signal associated therewith for indicating a first or second condition associated with the corresponding timing signal, the method comprising: supplying the timing signals to a selector for selecting one timing signal as an output signal; and controlling the selector to select a new timing signal as the said output signal when the indicator signal associated with the currently selected timing signal indicates the second condition for that timing signal and the first condition is indicated for one or more of the other timing signals by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the said other timing signals for which the first condition is indicated, the timing signal containing the said first pulse being selected as the new output signal.

The invention further provides a method of switching between a plurality of data streams each of which has a pulsed timing signal synchronised therewith and an associated indicator signal for indicating a first or second condition associated with the corresponding data stream, the method comprising: supplying the data streams to a selector for selecting one data stream as an output of the selector; and controlling the selector to select a new data stream as the said output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for one or more of the other data streams by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the timing signals for which the first condition is indicated for the associated data stream or streams, the data stream associated with the timing signal containing the said first pulse being selected as the new output.

In general, where features are described herein with reference to an apparatus in accordance with the invention, corresponding features may be provided in a method of the invention and vice versa.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows schematically an example of the format of a data stream reproduced by a reproducing head of a DVTR and a timing signal derived therefrom; Figure 2 is a schematic circuit diagram of apparatus embodying the invention; Figure 3 shows in more detail part of the apparatus of Figure 2; Figure 4 is a timing diagram used in explaining the operation of the apparatus of Figure 2; and Figure 5 is a block diagram of part of a reproduction processor of a DVTR incorporating the apparatus of Figure 2.

In the example of Figure 1, the data stream consists of a series of word blocks one of which is shown in full in the figure. The initial portion of the word block, for example two words, is taken up with synchronisation (SYNC) data. The next portion of the word block contains identifiers (ID), eg group and field identifiers. The majority of the word block is taken up with video data as shown in the figure, and the final section of the block contains error correction codes (ECC) to enable correction of errors in the reproduced data in the reproduction processor of the DVTR. The reproduction processor processes the reproduced data to deserialise the data to parallel word form, and derives a pulsed timing signal, shown schematically at 1 in Figure 1, therefrom. The timing signal 1 consists of a train of start pulses (SP) 2 which mark the start of the sync data, ie the start of each word block, in the deserialised data stream.

Figure 2 shows a switching circuit embodying the invention for switching between two data streams in the reproduction processor of a DVTR. The two deserialised data streams, originally derived from respective reproducing heads of the DVTR, are supplied as inputs to the switching circuit which is generally indicated at 3. The two data streams, "Channel A" and "Channel B" in the figure, are input along respective parallel buses 4a and 4b. The data buses 4a, 4b are connected to a selector 5 for selecting the data stream on one of the buses 4a, 4b to be supplied to a data output 6 of the selector under the control of a signal supplied to an input S of the selector. A delay in the form of a first-in-first-out (FIFO) device 7a, 7b is connected in each data bus 4a, 4b.

The switching circuit 3 includes control means which comprise two pre-processors 8a, 8b each associated with a corresponding data bus 4a, 4b. In this example, the pre-processors 8a, 8b are PAL devices the operation of which will be described in more detail with reference to Figure 3. The control means further comprises an array of NAND gates 9a, 9b, lOa, lOb, ila and lib connected as shown. It will be seen that the gates lia, lib are wired as an S-R flip-flop the Q output of which is connected to the input S of the selector 5.

Figure 3 shows a pre-processor 8a, 8b of Figure 2 with the inputs and outputs labelled. Each pre-processor has a Start Pulse (SP) input for receiving the timing, or start pulse, signal 1 (Figure 1) which is synchronised with the corresponding Channel A and Channel B data stream. The pre-processor also has an Error Flag (EF) input for receiving an error signal which indicates an error or error-free condition of the corresponding Channel A or Channel B data stream. The EF signal may have been derived in a number of ways, though in this example the state of each error signal depends upon whether the pulses 2 of the corresponding SP signal are of the prescribed temporal spacing. The EF signals are derived in known manner in an earlier part of the reproduction processor. Each EF signal takes the value logic 1 to indicate an error-free condition of the associated data stream and the value logic 0 to indicate an error condition.

A clock input (CK) of each pre-processor clocks the SP and EF signals into the pre-processor at the word rate of the corresponding Channel A or Channel B data stream. The input signals are processed in the pre-processor to produce four outputs as shown in the figure. The first of these is a Gated Error Flag (GEF) output in which the input EF pulses are extended over the period between adjacent pulses of the input SP signal. The second output is the Gated Start Pulse (GSP) output in which the input start pulses are gated out over any period during which the GEF output indicates an error condition. The third and fourth outputs, ie the Delayed Start Pulse (DSP) and Delayed Error Flag (DEF) outputs, are simply the input SP and EF signals delayed by an amount corresponding to the processing time of the subsequent control circuitry. The delay introduced here corresponds to that introduced by the FIFOs 7a and 7b in the two data streams and is normally only a few clock cycles in length.

In Figure 2, the inputs and outputs to the pre-processors 8a and 8b are labelled either A or B to indicate their association with Channel A or Channel B data, and the clock inputs to the pre-processors are omitted for clarity. As shown in the Figure, the DEF and DSP outputs of each pre-processor 8a, 8b are connected directly to the selector 5. The GEF output of each pre-processor is connected to the input of a NAND gate 9a, 9b the other input to which is a Channel Detect input. The Channel Detect inputs are provided to prevent a spurious lock-out condition by disabling the switching circuit in the case where there are no clock signals to either pre-processor, for example due to a break in a connection. These inputs are held at logic 1 when the apparatus is operative, and logic 0 otherwise.

The output of the NAND gate 9a is gated with the GSP output of the pre-processor 8b by the NAND gate lOb. The output of this NAND gate forms the reset input R to the S-R flip-flop formed by- the gates lia and llb. Similarly, the output of the NAND gate 9b is gated with the GSP output of the pre-processor 8a by the NAND gate 10a, the output of which forms the set input S to the flip-flop gila, lib. The Q output of the S-R flip-flop lia, lib is connected to the input S of the selector 5. The signal on this input forms an A/B Select signal which triggers switching between the Channel A and Channel B data streams in the selector 5. At the same time as selecting a new data stream as the output, the selector 5 selects the DEF and DSP inputs associated with the selected channel for supply to an EF output and an SP output respectively of the selector 5.

The operation of the apparatus will now be described with reference to Figure 4 which is a timing diagram showing the SP, GEF and GSP signals associated with each data channel during switching first from Channel A to Channel B and then from Channel B to Channel A. The A/B select signal applied to the input S of the selector 5 is also shown, together with the signal on the EF output of the selector. The bottom line of the timing diagram indicates whether the data on the output 6 of the selector 5 is the Channel A or Channel B data stream.

In the initial portion of Figure 4, GEF A is high and GEF B is low indicating no error on Channel A and an error condition on Channel B. Thus, Channel A data is being supplied on the output 6 of the selector 5 at this stage. The A/B select signal on the Q output of the flip-flop gila, lib is low, and the output of the NAND gate lOb, which forms the reset input R of the flip-flop lia, lib is high. The output of the NAND gate lOa is the inverse of the signal GSP A, and so the circuit is stable with the A/B select signal low.

Towards the start of the timing diagram of Figure 4, GEF B goes high indicating an error-free condition on Channel B while Channel A is still error-free. This causes the output of the NAND gate 9b to go low so that a constant high level is presented at the S input to the flipflop lla, llb and since the R input is still high the Q output, ie the A/B select signal, remains low and no switching occurs.

Shortly after this, GEF A goes low indicating an error condition on Channel A, the start pulses corresponding to Channel A then being gated out in GSP A by the pre-processor 8a. GEF B is still high at this stage, ie Channel B is error-free. The output of the NAND gate 9a goes high so that on the next pulse of GSP B the output of the NAND gate lOb goes low. Since the S input of the flip-flop lla, llb is still high, the first low pulse on the R input causes the Q output of the flip-flop, ie A/B select, to go high. This change of state on the S input to the selector 5 causes switching to Channel B data on the output 6 and to DSP B and DEF B on the SP and EF outputs of the selector 5 respectively. As the R input to the flip-flop gila, lib goes high following each low pulse on the output of the gate lOb, the state of the Q output, ie A/B select, is maintained and the system is stable with Channel B as the output data stream.

Following through the timing diagram of Figure 4, GEF B then goes low, indicating an error condition on Channel B, and the start pulses on SPB are gated out in GSP B. GEF A is still low at this stage so that Channel A still contains errors. The reset input to the flip-flop lla, llb is thus held at a constant high level, and since the set input is still at a high level, there is no change in the A/B select signal on the Q output of the flip-flop and hence no switching in the selector 5. Shortly thereafter, GEF A goes high indicating an error-free condition on Channel A. The output of the NAND gate lOa is then the inverse of GSP A. The first low pulse on the output of the gate lOa, ie the set input of the flip-flop lia, llb, resets the flip-flop so that the Q output, ie A/B select, goes low. A/B select applied to the input S of the selector 5 thus causes the selector to switch to Channel A data on the output 6 and to DSP A and DEF A on the SP and EF outputs.

The circuit is then stable until a condition where Channel A contains errors and Channel B is error-free arises whereupon the above-described process starts again.

Thus, it will be appreciated that the state of the output remains unchanged while either both channels contain errors or neither channel contains errors. When the switching condition arises, ie when the currently selected channel contains errors and the other channel is error-free, then the switching occurs on the immediately next pulse of the gated start pulse signal of the error-free channel. Thus, switching is effected in a suitably controlled manner, while the amount of invalid data in the output signal, as indicated by the low regions of EF OUT and the shaded areas on the DATA OUT,line of Figure 4, is kept to a minimum.

In Figure 5, the switching circuit 3 is shown in a block diagram of part of a reproduction processor in a DVTR. The serial data streams from two reproduction heads, the Channel A head and the Channel B head, of the DVTR are supplied to respective sync/ID and ECC processors 12a and 12b wherein the data streams are deserialised, synchronisation data is decoded and the start pulse signals and error flag signals are derived. These are then supplied to the switching circuit 3 which operates as hereinbefore described. The outputs of the switching circuit are supplied to a timebase corrector pre-processor 13 wherein the switched data is used to provide address information for the writing of data to a timebase corrector TBC (not shown) wherein the data is temporarily stored.

It will be appreciated that various modifications may be made to the specific embodiment described above. In particular, the system may be implemented for more than two data streams, in which case switching is effected when the currently selected data stream contains errors and at least one of the other data streams is error-free. Switching is then effected on the first pulse of the timing signal corresponding to an error-free channel occurring after the switching condition arises whereupon the output is switched to that channel.

Claims

1. Apparatus for switching between a plurality of pulsed timing signals each of which has an indicator signal associated therewith for indicating a first or second condition associated with the corresponding timing signal, the apparatus comprising: a selector for receiving the timing signals and selecting one timing signal as an output signal; and control means for receiving the timing signals and the indicator signals and for controlling the selector to select a new timing signal as the said output signal when the indicator signal associated with the currently selected timing signal indicates the second condition for that timing signal and the first condition is indicated for one or more of the other timing signals by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the said other timing signals for which the first condition is indicated, the timing signal containing the said first pulse being selected as the new output signal.

2. Apparatus for switching between a plurality of data streams each of which has a pulsed timing signal synchronised therewith and an associated indicator signal for indicating a first or second condition associated with the corresponding data stream, the apparatus comprising: a selector for receiving the data streams and selecting one data stream as an output of the selector; and control means for receiving the timing signals and the indicator signals and for controlling the selector to select a new data stream as the said output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for one or more of the other data streams by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the timing signals for which the first condition is indicated for the associated data stream or streams, the data stream associated with the timing signal containing the said first pulse being selected as the new output.

3. Apparatus as claimed in claim 2 for switching between two data streams, wherein the control means is adapted to control the selector to select the other data stream as the said output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for the other data stream, the selection then being effected on the first pulse of the timing signal corresponding to the other data stream.

4. Apparatus as claimed in claim 2 or claim 3, wherein the selector is arranged to receive the said timing signals and to select the timing signal corresponding to the selected data stream as a further output of the selector.

5. Apparatus as claimed in any one of claims 2 to 4, wherein the selector is arranged to receive the said indicator signals and to select the indicator signal corresponding to the selected data stream as an additional output of the selector.

6. Apparatus for switching between a plurality of data streams, the apparatus being substantially as hereinbefore described with reference to the accompanying drawings.

7. A method of switching between a plurality of pulsed timing signals each of which has an indicator signal associated therewith for indicating a first or second condition associated with the corresponding timing signal, the method comprising: supplying the timing signals to a selector for selecting one timing signal as an output signal; and controlling the selector to select a new timing signal as the said output signal when the indicator signal associated with the currently selected timing signal indicates the second condition for that timing signal and the first condition is indicated for one or more of the other timing signals by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the said other timing signals for which the first condition is indicated, the timing signal containing the said first pulse being selected as the new output signal.

8. A method of switching between a plurality of data streams each of which has a pulsed timing signal synchronised therewith and an associated indicator signal for indicating a first or second condition associated with the corresponding data stream, the method comprising: supplying the data streams to a selector for selecting one data stream as an output of the selector; and controlling the selector to select a new data stream as the said output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for one or more of the other data streams by the associated indicator signal or signals; the selection then being effected on the first pulse of the or any of the timing signals for which the first condition is indicated for the associated data stream or streams, the data stream associated with the timing signal containing the said first pulse being selected as the new output.

9. A method as claimed in claim 8 for switching between two data streams, wherein the selector is controlled to select the other data stream as the said output when the indicator signal associated with the currently selected data stream indicates the second condition for that data stream and the first condition is indicated for the other data stream, the selection then being effected on the first pulse of the timing signal corresponding to the other data stream.

10. A method as claimed in claim 8 or claim 9, including supplying the said timing signals to the selector and controlling the selector to select the timing signal corresponding to the selected data stream as a further output of the selector.

11. A method as claimed in any one of claims 8 to 10, including supplying the said indicator signals to the selector and controlling the selector to select the indicator signal corresponding to the selected data stream as an additional output of the selector.

12. A method as claimed in any one of claims 8 to 11, wherein each said indicator signal is an error signal, the said first condition corresponding to an error-free condition of the associated data stream and the said second condition corresponding to an error condition of the associated data stream.

13. A method as claimed in claim 12, wherein the state of each error signal depends upon whether the pulses of the corresponding timing signal are of a predetermined temporal spacing.

14. A method of switching between a plurality of data streams, the method being substantially as hereinbefore described with reference to the accompanying drawings.