JPH0379890B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data error correction method in which redundant bits for error correction are formed based on parity bits, and data errors are corrected using the redundant bits for error correction. This is suitable for application when the data length of one block including parity bits is long.

As a basic error correction using parity bits, for n-word data (D ₁ , D ₂ ...D _o ), (D ₁ D ₂ ...D _o = P ₁ (even parity)) or ( _{1 2} ... _o = P ₁ (odd parity)) and redundant bits (parity bits, CRC code, etc.) that can detect errors in each n-word data are added to form one block of data and then transmitted. However, on the receiving side, if one word in one block is erroneous, excluding the error word Di, (D ₁ D ₂ ...D _o +P ₁ =
Di) or ( _{1 2} ... _{o 1} = Di) operation (according to the addition method of mod.2. The same applies hereinafter) can be used to obtain correct data Di. . A parallel processing method and a serial processing method are considered as configurations for realizing this error correction processing. A parallel processing method that outputs one block of n words in parallel and adds the corresponding bits of each word requires a register for (n+1) words and an adder (exclusive OR gate) for each bit. However, control when regularly reading out data and serializing it becomes complicated. In the serial processing method, which supplies received data to a shift register, feeds back its output, and adds it to the received data, only one word of register is required to store the data, and one adder is required.
However, corrected data can only be obtained by supplying n words among (D ₁ to D _o , P ₁ ), so in order to correct error data and obtain serial data in the correct order, , a buffer memory for n words is required, and in the end, (n+1) registers are required. Therefore, the configuration cannot be simplified much compared to the parallel processing method.

An object of the present invention is to realize a data error correction device that can reduce the capacity of a register (buffer memory) and has a simple and inexpensive configuration compared to the above-mentioned two methods. The present invention focuses on the fact that a RAM is provided in a PCM recording/reproducing device etc. in order to remove time axis fluctuations that occur in a transmission path, and uses this RAM to increase the reading speed to twice the writing speed. do. Then, the first data is read from one block stored in this RAM, and the second output data is read from one block before this block,
By performing error correction processing based on the first and second output data read from the RAM, the buffer memory required in the serial processing method is omitted. That is, redundant bits for error correction are formed from the first output data read out in advance from a predetermined block stored in the RAM, and at the same time the redundant bits for error correction are formed. By performing error correction processing on the read second output data using the redundant bits for error correction, the buffer memory is omitted.
For example, when one block consists of six words of data and one word of parity bit series, the second output data _Sd2 read from the RAM is shown in FIG. 1A, and in FIG. 1B. Similarly, the first output data Sd ₁ is shown. D ₁ ,n
and D _i,o+1 indicate the data of the i-th one word in the n-th and n+1-th blocks, respectively,
Fi,n and F _i,o+1 indicate determination bits indicating whether the corresponding i-th data is correct or erroneous. The parity bit series P _o and P _o+1 included in the nth and n+1st blocks are written in the RAM corresponding to the respective blocks, and are not read out unless a data error is detected. Also,
The discrimination bit is formed by error detection, such as CRC, that precedes writing to RAM.
If an error is detected, it is set to "1", and if no error is detected, it is set to "0" and stored together with the respective word. The discrimination bit for the first output data Sd ₁ is monitored. For example, the discrimination bit F _4,o+1 in the n+1st block is "1", and the data [D _4,o+1 ] is If an error is detected, the error data [D _4,o+1 ] is saved from RAM.
Instead of reading the parity bit sequence P _o+1 in that block. Then, by serially processing the output data Sd ₁ excluding the error data [D _4,o+1 ], the data of the n+1th block is
Correct error-corrected data D _4,o+1 can be formed in accordance with the timing at which the second output data is read from the RAM. This correct data D _4,o+1 can be replaced with the error data [D _4,o+1 ] that appears again in the second output data Sd ₂ read from the RAM and taken out as an output.

An example of an apparatus for correcting data errors according to the method of the present invention described above is shown in FIG. In addition, the RAM described in the present invention is as shown in FIG.
RAM1 and flip-flops 13a, 13b,
14a and 14b. In Figure 2,
Reference numeral 1 indicates a RAM, in which the playback data played back by the PCM recording/playback device is passed through a CRC checker, whereby input data in the form of a discrimination bit added to each word is supplied to the input terminal 2 of the RAM1. Ru. 3a, 4a, and 5a indicate a bit counter, word counter, and block counter, respectively, which generate write address signals; 3b, 4b, and 5b,
a bit counter that generates the read address signal;
A word counter and a block counter are shown respectively.
Either the write address signal or the read address signal is selected by the data selector 6.
Given to RAM1.

A write date signal PWG and a write bit clock PWBC are supplied to AND gate 7, and the output of AND gate 7 is supplied to bit address counter 3a. This example PCM recording/playback device is
A VTR (video tape recorder) is used as a transmission means, and the PCM signal recorded or played back has the same signal format as a television signal.
That is, as shown in FIG. 4A, a data missing period corresponding to the vertical blacking period is provided within one field (1V) period of the same length as the television signal, and as shown in FIG. A data missing period corresponding to a horizontal blanking period is provided within one horizontal period (1H) having the same length as the signal. write gate signal
PWG becomes "0" during the data missing period as shown in FIGS. 4B and 4D, and is used to stop the write operation during this data missing period.

The read bit clock as shown in FIG.
A read bit clock 2PRBC is formed which is synchronized with PRBC and has twice its frequency. The write bit clock PWBC mentioned above is formed by a PLL circuit or the like so as to be synchronized with the synchronization signal in the reproduction signal, whereas the read bit clock PWBC is
The PRBC has a constant frequency and is formed by frequency-dividing the output of the reference oscillator, and both of them are used to absorb time-axis fluctuations such as jitter. When there is a period of missing data in the reproduced data, as in this example, time axis expansion is required to remove the period of missing data.
Read bit clock frequency compared to PWB frequency
PRBC frequency has been lowered. The data selector 6 and
The RAM 1 is controlled and its control signal is generated from the R/W control circuit 8. A write bit clock PWBC and a read bit clock 2 PRBC are supplied to the R/W control circuit 8 via an AND gate, and the data is controlled to be read at a read speed approximately twice the write speed.

The output of word counter 4b on the read side is supplied to data selector 6 via address load circuit 9. Address load circuit 9 is controlled by the output of AND gate 10, and the read word address is set to be a parity bit series address only during the period in which the output of AND gate 10 is "1". This AND gate 10 is supplied with a control signal _P1 from a control circuit 12 and a read bit clock PRBC. Also, the block counter 5b on the reading side
The output of the full adder 11 is used as one addition input, and the read bit clock PRBC is supplied as the least significant bit input of the other addition input. If the timing of the rise of the read bit clock 2 PRBC shown in FIG. 5 is taken as a read command, the block address is nth in the period T _o when the read bit clock PRBC is "0", and this is the period T _o+1 when the read bit clock PRBC is "1". Then, the block address advances by one to the (n+1)th block, and therefore data is read out alternately from the nth block and the (n+1)th block within one bit period. Also,
Read bit clock PRBC to AND gate 10
is supplied, the word address of the parity bit series is specified only when a read operation is being performed for the (n+1)th block.

Read output of RAM1 is D flip-flop 1
3a and 13b, flip-flop 1
Read bit clock as clock input of 3b.
PRBC is supplied and flip-flop 1
3a is supplied as the clock input, so that the read output of the n+1th block is selected by the flip-flop 13a, and the read output of the n-th block is selected by the flip-flop 13b. Flip-flops 14a and 14b are provided to which the outputs of flip-flops 13a and 13b are respectively supplied, and a read bit clock PRBC is commonly supplied to these flip-flops 14a and 14b, so that the outputs of the flip-flops 14a and 14b are synchronized. A first data output Sd ₁ and a second data output Sd ₂ appear. In this example, one block of data is 6 words, and data outputs Sd ₁ and Sd ₂ are shown in FIGS. 3A and 3C, respectively.
The data output Sd ₂ is supplied to one input end of the selector 15 .

For example, one word of data as shown in FIG.
Discrimination bits Fi,
n is inserted, and a discrimination bit (not shown) is similarly inserted into the parity bit series. When the discrimination bit Fi,n is "0", it indicates that the word is correct data, and when it is "1", it indicates that it is error data. During PCM recording, interleaving (reordering) of multiple blocks or convolutional coding that sequentially delays the 7 words of one block is performed in order to disperse burst errors caused by dropouts, etc. An error detection code, such as a CRC code, is added to the data resulting from any of these processes and to each word of the parity bit series.
During playback, after an error is detected using the CRC code, deinterleaving or delay processing is performed to arrange the data in the original order. This processing at the time of reproduction can be done by devising the address control of RAM1. By controlling the read bit address of RAM1, it is possible to insert determination bits into the first two bit positions of one word.
In order to extract the discrimination bits from the output data Sd ₁ and Sd ₂ , flip-flops 16a and 1
6b is provided. From the word clock from the word counter 4b and the read bit clock PRBC shown in FIG. 6B, a clock pulse at a timing corresponding to the discrimination bit as shown in FIG. 6C is generated.
P ₂ is formed and this clock pulse P ₂ is applied to flip-flops 16a and 16b. Therefore, when the discriminating bit F _i,o+1 of each word of the n+1th block is obtained from the flip-flop 16a, the discriminating bit F i,n of each word of the n-th block is obtained from the flip-flop 16b,
This discrimination bit is supplied to the control circuit 12.

Further, the output data Sd ₁ is applied to one input terminal of an exclusive OR gate 17 as a (mod. 2) adder, and the output of the exclusive OR gate 17 is supplied to shift registers 18 and 21. Each of the shift registers 18 and 21 is
The number of bits is equal to the number of bits in one word. A read bit clock PRBC via AND gates 19 and 22 is applied as a clock input to shift registers 18 and 21, respectively. Gate signals P ₃ and P ₅ are supplied from the control circuit 12 to the AND gates 19 and 22, respectively.
The output of the shift register 18 is fed back to the other input terminal of the exclusive OR gate 17 via an AND gate 20. and gate 2
0 is supplied from the control circuit 12 with a gate signal _P4 which becomes "0" during the first one word period of each block. Correction calculation processing is performed by the exclusive OR gate 17, shift register 18, and AND gate 20, and the obtained correct data is taken into the shift register 21 by the gate signal _P5 , and the correct data is inputted at a predetermined timing in the output data _Sd2 . Again, the correct data is taken out by the gate signal _P5 and supplied to the other input terminal of the selector 15. The selector 15 is switched so as to lead correct data from the shift register 21 to the output terminal 23 during a period in which the selector control signal P ₆ from the control circuit 12 is "1". Note that the gate signal _P3 supplied to the AND gate 19 becomes "0" during the first two bits of each word as shown in FIG. It is intended to prevent

In the embodiment of the present invention described above, the operation when the third word of the (n+1)th block is incorrect will be described. In this case, since the discrimination bit F3 _,o+1 becomes "1", this is detected by the flip-flop 16a and sent from the control circuit 12 to the third
A control signal _P1 shown in Figure B is generated. This control signal
_P1 causes the word address to become the address of the parity bit series for the (n+1)th block, and the parity bit series P _o+1 for the (n+1)th block is read out. On the other hand, since the word address of the n-th block is a data address, one word of data D ₃ ,n is read out as is, regardless of whether it is correct or incorrect (see FIG. 3C). Note that the first two bits of the parity bit series P _o+1 are also discriminating bits, so if the second discriminating bit is detected by the flip-flop 16a and the parity bit series P _o+1 is incorrect, Since correction is impossible, the error data [D _3,o+1 ] is read out as is without setting the control signal P ₁ to "1", and other correction processing such as average value interpolation is performed. Also, if two or more words in one block are incorrect, correction is impossible, so even if two or more words contain errors,
Correction processing similar to that described above is performed. The information necessary for these correction processes is output data Sd ₁
These correction processes are performed on the output side of the selector 15.

Furthermore, the output of the AND gate 20 becomes "0" in the first word period of each block due to the gate signal _P4 shown in FIG. As shown in Figure E, the first word of each block, for example D _1,o+1
appears. Of D1 _,o+1, the bits other than the discrimination bit are taken into the shift register 18. Since the gate signal _P4 is "1" from the next word time to the first timing of the next n+2th block, D1 _,o+1 is sent from the shift register 18 to the exclusive OR gate 17 via the AND gate 20. is fed back, and the operation result of (D _2,o+1 D _1,o+1 ) is transferred to shift register 1 at the second word time.
Occurs at 8. Hereafter, this calculation operation is repeated, and n
+In the first 6th word time of the 1st block, (D _6,o+1 D _5,o+1 D _4,o+1 P _o+1 D _2,o+1
D _1,o+1 ) operation result, that is, error-corrected data
D _3,o+1 occurs. Here, as shown in Figure 3F, the gate signal _P5 becomes "1" at the 6th word time of each block, so the obtained correct data
D _3,o+1 can be taken into the shift register 21.

Furthermore, as shown in FIG. 3C, the output data Sd ₂ includes the error data [D _3,o+1 ] of the n+1th block as it is, and therefore the discrimination bit F _3,o+ taken out by the flip-flop 16b. ₁ is “1”
becomes. As a result, the gate signal _P5 becomes "1" at the word time of [D _3,o+1 ] as shown in Fig. 3F, and becomes "1" at the same timing as shown in Fig. 3G. A selector control signal P ₆ is generated from control circuit 12 . Correct data D _3,o+1 stored in the shift register 21 is read out by these gate signal P ₅ and selector control signal P ₆ and is also read out from the output terminal 23 via the selector 15.
It is taken out. Since the next data _D4,o+1 is correct, the selector 15 extracts the output data _Sd2 . Through the above operations, error-corrected output data can be obtained at the output terminal 23.

As described above, according to the present invention, the shift register 18 for one word for correction calculation, the shift register 21 for one word for storing the result, and one exclusive OR gate 17 are used. It is possible to realize an error correction device that can correct errors and has a very simple configuration. In particular, 1
A feature of the present invention is that even if the block length is as long as 7 words or longer as in the above-described embodiment, the configuration required for error correction processing does not become complicated at all. Furthermore, as in the above example, the second
If the read address is controlled so that the output data Sd ₂ of 2 contains the error data as is, there is an advantage that the process of replacing the error data with correct data can be easily performed.

Note that instead of storing the correct data obtained through the correction calculation processing in the shift register 21, this correct data is temporarily written to the address of the corresponding data in RAM1 to replace the error data, and then the data in RAM1 is read. You may also try to release it. In this case, there is no need for a storage means for storing error-corrected data.

[Brief explanation of drawings]

FIG. 1 is a diagram used to explain the present invention, FIG. 2 is a block diagram of an example of a device for correcting data errors according to the method of the present invention, FIG. 3 is a time chart used for the explanation, and FIG. 4 is a write gate. FIG. 5 is a waveform diagram used to explain the signals, FIG. 5 is a waveform diagram used to explain the read bit clock, and FIG. 6 is a waveform diagram used to explain the discrimination bit. 1 is a RAM, 3a, 4a, 5a are counters that generate write address signals, 3b, 4b, 5b are counters that generate read address signals, 6 is a data selector, 9 is an address load circuit, 11 is a full adder, 12 is a control circuit, 15 is a selector,
17 is exclusive or gate, 18, 21
is a shift register.

Claims (1)

[Claims] 1. A parity word formed of a predetermined number of data words and a parity determination bit of each data word, and determination information for each data word indicating whether or not there is a possibility of an error in the data word. write data having one block into the RAM, sequentially read the data words and discrimination information of the first data block from the RAM at a first timing, and sequentially calculate the read data words word by word; When a possibility of an error is detected in the data word based on the read discrimination information, the data word is replaced with the parity word, and the above parity word is calculated, a corrected data word is formed by the above calculation, and the first data block is Each data word is sequentially read out at a second timing that is sent from the first timing, and the data word in which the possibility of an error has been detected among the data words read out at the second timing is converted into the corrected data word. A data error correction method characterized by replacing the . 2. One block of data having a parity word formed by a predetermined number of data words and parity determination bits of each data word, and determination information for each data word indicating whether or not there is a possibility of an error in the data word. The data words and discrimination information of the first data block are sequentially read from the RAM at the first timing, and the read data words are sequentially calculated word by word, and the read discrimination information is written to the RAM as follows. When a possibility of an error is detected in the data word, the data word is replaced with the above parity word, and a corrected data word is formed by the above operation. write to the address of the detected data word to replace the erroneous data word, and write the first data block containing the corrected data word replaced from the RAM at a second timing delayed from the first timing. A data error correction method characterized in that a data word is read out.